Microchip Technology Inc 93LC56BXT-I-SN, 93LC56BXT-SN, 93LC56BX-SN, 93LC56BT-I-ST, 93LC56BT-I-SN Datasheet

M 93LC56A/B

2K 2.5V Microwire Serial EEPROM

FEATURES

•Single supply with operation down to 2.5V

•Low power CMOS technology

-1 mA active current (typical)

-1 A standby current (maximum)

•256 x 8 bit organization (93LC56A)

•128 x 16 bit organization (93LC56B)

•Self-timed ERASE and WRITE cycles (including auto-erase)

•Automatic ERAL before WRAL

•Power on/off data protection circuitry

•Industry standard 3-wire serial interface

•Device status signal during ERASE/WRITE cycles

•Sequential READ function

•1,000,000 E/W cycles guaranteed

•Data retention > 200 years

•8-pin PDIP/SOIC and 8-pin TSSOP packages

•Available for the following temperature ranges:

-	Commercial (C):	0°C	to	+70°C
-	Industrial (I):	-40°C	to	+85°C

PACKAGE TYPE

		DIP									SOIC
CS	1		8	Vcc
		93LC56A/B			CS					1		93LC56A/B		8				VCC
CLK	2		7	NC
					CLK					2				7				NC
DI	3		6	NC
										3				6
					DI													NC
DO	4		5	Vss
										4				5
					DO													Vss

BLOCK DIAGRAM

	MEMORY	ADDRESS
	ARRAY	DECODER
		ADDRESS
		COUNTER
	DATA	OUTPUT	DO
	REGISTER	BUFFER
DI
	MODE
	DECODE
CS	LOGIC
CLK	CLOCK	Vcc
		Vss
	GENERATOR
DESCRIPTION

The Microchip Technology Inc. 93LC56A/B are 2K-bit, low-voltage serial Electrically Erasable PROMs. The device memory is configured as x8 (93LC56A) or x16 bits (93LC56B). Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. The 93LC56A/B is available in standard 8-pin DIP, surface mount SOIC, and TSSOP packages. The 93LC56AX/BX are only offered in a 150-mil SOIC package.

SOIC TSSOP

			1	93LC56A/BX	8					CS	1	93LC56A/B	8	Vcc
NU									NC	CLK	2		7	NC
										DI	3		6	NC
Vcc			2		7				Vss	DO	4		5	Vss
			3		6
CS									DO
			4		5
CLK									DI

Microwire is a registered trademark of National Semiconductor.

1997 Microchip Technology Inc.

Preliminary

DS21208A-page 1

93LC56A/B

1.0ELECTRICAL CHARACTERISTICS

1.1Maximum Ratings*

VCC...................................................................................		7.0V
All inputs and outputs w.r.t. Vss ................	-0.6V to Vcc +1.0V
Storage temperature .....................................	-65°C to +150°C
Ambient temp. with power applied.................	-65°C to +125°C
Soldering temperature of leads (10 seconds) .............		+300°C
ESD protection on all pins................................................		4 kV

*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1	PIN FUNCTION TABLE
Name	Function
CS	Chip Select
CLK	Serial Data Clock
DI	Serial Data Input
DO	Serial Data Output
VSS	Ground
NC	No Connect
VCC	Power Supply

TABLE 1-2	DC AND AC ELECTRICAL CHARACTERISTICS
All parameters apply over the specified		Commercial (C):		VCC = +2.5V to +6.0V		Tamb = 0°C to +70°C
operating ranges unless otherwise		Industrial (I):		VCC = +2.5V to +6.0V		Tamb = -40°C to +85°C
noted
Parameter		Symbol		Min.	Max.	Units	Conditions
High level input voltage		VIH1		2.0	Vcc +1	V	2.7V ≤ VCC ≤ 5.5V (Note 2)
		VIH2		0.7 Vcc	Vcc +1	V	VCC < 2.7V
Low level input voltage		VIL1		-0.3	0.8	V	VCC > 2.7V (Note 2)
		VIL2		-0.3	0.2 Vcc	V	VCC < 2.7V
Low level output voltage		VOL1		—	0.4	V	IOL = 2.1 mA; Vcc = 4.5V
		VOL2		—	0.2	V	IOL =100 A; Vcc = Vcc Min.
High level output voltage		VOH1		2.4	—	V	IOH = -400 A; Vcc = 4.5V
		VOH2		Vcc-0.2	—	V	IOH = -100 A; Vcc = Vcc Min.
Input leakage current		ILI		-10	10	A	VIN = VSS
Output leakage current		ILO		-10	10	A	VOUT = VSS
Pin capacitance		CIN, COUT		—	7	pF	VIN/VOUT = 0 V (Notes 1 & 2)
(all inputs/outputs)							Tamb = +25°C, Fclk = 1 MHz
		ICC read		—	1	mA	FCLK = 2 MHz; VCC = 6.0V
Operating current					500	A	FCLK = 1 MHz; VCC = 3.0V
		ICC write		—	1.5	mA
Standby current		ICCS		—	1	A	CS = VSS
Clock frequency		FCLK		—	2	MHz	VCC > 4.5V
					1	MHz	VCC < 4.5V
Clock high time		TCKH		250	—	ns
Clock low time		TCKL		250	—	ns
Chip select setup time		TCSS		50	—	ns	Relative to CLK
Chip select hold time		TCSH		0	—	ns	Relative to CLK
Chip select low time		TCSL		250	—	ns
Data input setup time		TDIS		100	—	ns	Relative to CLK
Data input hold time		TDIH		100	—	ns	Relative to CLK
Data output delay time		TPD		—	400	ns	Cl = 100 pF
Data output disable time		TCZ		—	100	ns	Cl = 100 pF (Note 2)
Status valid time		TSV		—	500	ns	Cl = 100 pF
		TWC		—	6	ms	ERASE/WRITE mode
Program cycle time		TEC		—	6	ms	ERAL mode
		TWL		—	15	ms	WRAL mode
Endurance		—		1M	—	cycles	25°C, VCC = 5.0V, Block Mode (Note 3)

Note 1: This parameter is tested at Tamb = 25°C and FCLK = 1 MHz.

2:This parameter is periodically sampled and not 100% tested.

3:This application is not tested but guaranteed by characterization. For endurance estimates in a specifi application, please consult the Total Endurance Model which may be obtained on Microchip’s BBS or website.

DS21208A-page 2

Preliminary

1997 Microchip Technology Inc.

93LC56A/B

2.0PIN DESCRIPTION

2.1Chip Select (CS)

A high level selects the device; a low level deselects the device and forces it into standby mode. However, a programming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed.

CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a RESET status.

2.2Serial Clock (CLK)

The Serial Clock is used to synchronize the communication between a master device and the 93LC56A/B. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK.

CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data.

CLK is a “Don't Care”if CS is low (device deselected). If CS is high, but START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for START condition).

CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle.

After detection of a START condition the specified number of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (Table 2-1 and Table 2-2). CLK and DI then become don't care inputs waiting for a new START condition to be detected.

2.3Data In (DI)

Data In is used to clock in a START bit, opcode, address, and data synchronously with the CLK input.

2.4Data Out (DO)

Data Out is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK).

This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated.

The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready.

TABLE 2-1

INSTRUCTION SET FOR 93LC56A

Instruction

SB

Opcode

Address

Data In

Data Out

Req. CLK Cycles

ERASE

1

11

X

A7

A6

A5

A4

A3

A2

A1

A0

—

12

(RDY/BSY)

ERAL

1

00

1

0

X

X

X

X

X

X

X

—

12

(RDY/BSY)

EWDS

1

00

0

0

X

X

X

X

X

X

X

—

HIGH-Z

12

EWEN

1

00

1

1

X

X

X

X

X

X

X

—

HIGH-Z

12

READ

1

10

X

A7

A6

A5

A4

A3

A2

A1

A0

—

D7 - D0

20

WRITE

1

01

X

A7

A6

A5

A4

A3

A2

A1

A0

D7 - D0

20

(RDY/BSY)

WRAL

1

00

0

1

X

X

X

X

X

X

X

D7 - D0

20

(RDY/BSY)

TABLE 2-2

INSTRUCTION SET FOR 93LC56B

Instruction

SB

Opcode

Address

Data In

Data Out

Req. CLK Cycles

ERASE

1

11

X

A6

A5

A4

A3

A2

A1

A0

—

11

(RDY/BSY)

ERAL

1

00

1

0

X

X

X

X

X

X

—

11

(RDY/BSY)

EWDS

1

00

0

0

X

X

X

X

X

X

—

HIGH-Z

11

EWEN

1

00

1

1

X

X

X

X

X

X

—

HIGH-Z

11

READ

1

10

X

A6

A5

A4

A3

A2

A1

A0

—

D15 - D0

27

WRITE

1

01

X

A6

A5

A4

A3

A2

A1

A0

D15 - D0

27

(RDY/BSY)

WRAL

1

00

0

1

X X

X

X

X

X

D15 - D0

27

(RDY/BSY)

1997 Microchip Technology Inc.

Preliminary

DS21208A-page 3

93LC56A/B

3.0FUNCTIONAL DESCRIPTION

Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS.

3.1START Condition

The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time.

Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (ERASE, ERAL, EWDS, EWEN, READ, WRITE, and WRAL). As soon as CS is high, the device is no longer in the standby mode.

An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in.

After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new START condition is detected.

3.2DATA IN (DI) AND DATA OUT (DO)

It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration, if A0 is a logic-high level, it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the READ operation. Under such a condition, the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the DO pin.

3.3Data Protection

During power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 2.2V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 2.2V at nominal conditions.

The EWDS and EWEN commands give additional protection against accidentally programming during normal operation.

After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed.

FIGURE 3-1: SYNCHRONOUS DATA TIMING

	CS VIH
	VIL	TCSS	TCKH	TCKL
	VIH				TCSH
CLK
	VIL
	VIH	TDIS	TDIH
	DI
	VIL				TCZ
			TPD	TPD
	DO VOH
(READ) VOL		TSV			TCZ
	DO VOH
				STATUS VALID
(PROGRAM) VOL
Note:	AC Test Conditions: VIL = 0.4V, VIH - 2.4V.

DS21208A-page 4

Preliminary

1997 Microchip Technology Inc.