24LC04B/08B
4K/8K 2.5V I2C Serial EEPROMs
FEATURES
•Single supply with operation down to 2.5V
•Low power CMOS technology
-1 mA active current typical
-10 A standby current typical at 5.5V
-5 A standby current typical at 3.0V
•Organized as two or four blocks of 256 bytes (2 x 256 x 8) and (4 x 256 x 8)
•2-wire serial interface bus, I2C compatible
•Schmitt trigger, filtered inputs for noise suppression
•Output slope control to eliminate ground bounce
•100 kHz (2.5V) and 400 kHz (5V) compatibility
•Self-timed write cycle (including auto-erase)
•Page-write buffer for up to 16 bytes
•2 ms typical write cycle time for page-write
•Hardware write protect for entire memory
•Can be operated as a serial ROM
•Factory programming (QTP) available
•ESD protection > 4,000V
•1,000,000 erase/write cycles guaranteed
•Data retention > 200 years
•8-pin DIP, 8-lead or 14-lead SOIC packages
•Available for extended temperature ranges
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Commercial (C): |
0°C |
to |
+70°C |
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Industrial (I): |
-40°C |
to |
+85°C |
DESCRIPTION
The Microchip Technology Inc. 24LC04B/08B is a 4K or 8K bit Electrically Erasable PROM. The device is organized as two or four blocks of 256 x 8-bit memory with a 2-wire serial interface. Low voltage design permits operation down to 2.5 volts with typical standby and active currents of only 5 A and 1 mA respectively. The 24LC04B/08B also has a page-write capability for up to 16 bytes of data. The 24LC04B/08B is available in the standard 8-pin DIP and both 8-lead and 14-lead surface mount SOIC packages.
I2C is a trademark of Philips Corporation.
1996 Microchip Technology Inc.
PACKAGE TYPES
PDIP |
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A0 |
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1 |
24LC04B/08B |
8 |
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VCC |
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A1 |
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2 |
7 |
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WP |
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A2 |
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SCL |
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VSS |
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4 |
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5 |
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SDA |
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8-lead |
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SOIC |
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1 |
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8 |
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VCC |
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A0 |
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24LC04B/08B |
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2 |
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A1 |
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WP |
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A2 |
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SCL |
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4 |
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VSS |
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SDA |
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14-lead |
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SOIC |
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1 |
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14 |
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NC |
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A0 |
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2 |
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13 |
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VCC |
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A1 |
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3 |
24LC04B/08B |
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12 |
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WP |
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NC |
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4 |
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NC |
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A2 |
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5 |
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10 |
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SCL |
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VSS |
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SDA |
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NC |
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7 |
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8 |
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NC |
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BLOCK DIAGRAM
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WP |
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HV GENERATOR |
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I/O |
MEMORY |
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EEPROM ARRAY |
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(2 x 256 x 8) or |
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CONTROL |
CONTROL |
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XDEC |
(4 X 256 X 8) |
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LOGIC |
LOGIC |
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PAGE LATCHES |
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SDA |
SCL |
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YDEC |
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VCC |
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SENSE AMP |
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VSS |
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R/W CONTROL |
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DS21051E-page 1 |
24LC04B/08B
1.0ELECTRICAL CHARACTERISTICS
1.1Maximum Ratings*
VCC................................................................................... |
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7.0V |
All inputs and outputs w.r.t. VSS .............. |
-0.3V to VCC + 1.0V |
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Storage temperature ..................................... |
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-65˚C to +150˚C |
Ambient temp. with power applied ................ |
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-65˚C to +125˚C |
Soldering temperature of leads (10 seconds) |
............. +300˚C |
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ESD protection on all pins .................................................. |
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≥ 4 kV |
*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-1: PIN FUNCTION TABLE
Name |
Function |
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VSS |
Ground |
SDA |
Serial Address/Data I/O |
SCL |
Serial Clock |
WP |
Write Protect Input |
VCC |
+2.5V to 5.5V Power Supply |
A0, A1, A2 |
No Internal Connection |
TABLE 1-2: |
DC CHARACTERISTICS |
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VCC = +2.5V to +5.5V |
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Commercial (C): Tamb = 0˚C to +70˚C |
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Industrial |
(I): Tamb = -40˚C to +85˚C |
Parameter |
Symbol |
Min |
Max |
Units |
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WP, SCL and SDA pins: |
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High level input voltage |
VIH |
.7 VCC |
— |
V |
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Low level input voltage |
VIL |
— |
.3 VCC |
V |
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Hysteresis of Schmitt trigger |
VHYS |
.05 VCC |
— |
V |
(Note) |
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Inputs |
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Low level output voltage |
VOL |
— |
.40 |
V |
IOL = 3.0mA, VCC = 2.5V |
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Input leakage current |
ILI |
-10 |
10 |
A |
VIN = .1V to VCC |
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Output leakage current |
ILO |
-10 |
10 |
A |
VOUT = .1V to VCC |
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Pin capacitance |
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CIN, COUT |
— |
10 |
pF |
V CC = 5.0V (Note) |
(all inputs/outputs) |
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Tamb = 25˚C, Fclk = 1 MHz |
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Operating current |
ICC WRITE |
— |
3 |
mA |
VCC = 5.5V, SCL = 400 kHz |
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ICC READ |
— |
1 |
mA |
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Standby current |
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ICCS |
— |
30 |
A |
VCC = 3.0V, SDA = SCL = VCC |
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— |
100 |
A |
VCC = 5.5V, SDA = SCL = VCC |
Note: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: |
BUS TIMING START/STOP |
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VHYS |
SCL |
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THD:STA |
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TSU:STA |
TSU:STO |
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SDA |
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START |
STOP |
DS21051E-page 2 |
1996 Microchip Technology Inc. |
24LC04B/08B
TABLE 1-3: |
AC CHARACTERISTICS |
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STANDARD |
VCC = 4.5 - 5.5V |
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Parameter |
Symbol |
MODE |
FAST MODE |
Units |
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Remarks |
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Min |
Max |
Min |
Max |
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Clock frequency |
FCLK |
— |
100 |
— |
400 |
kHz |
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Clock high time |
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THIGH |
4000 |
— |
600 |
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ns |
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Clock low time |
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TLOW |
4700 |
— |
1300 |
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ns |
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SDA and SCL rise time |
TR |
— |
1000 |
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300 |
ns |
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(Note 1) |
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SDA and SCL fall time |
TF |
— |
300 |
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300 |
ns |
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(Note 1) |
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START condition hold time |
THD:STA |
4000 |
— |
600 |
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ns |
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After this period the first clock |
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pulse is generated |
START condition setup time |
TSU:STA |
4700 |
— |
600 |
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ns |
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Only relevant for repeated |
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START condition |
Data input hold time |
THD:DAT |
0 |
— |
0 |
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ns |
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Data input setup time |
TSU:DAT |
250 |
— |
100 |
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ns |
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STOP condition setup time |
TSU:STO |
4000 |
— |
600 |
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ns |
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Output valid from clock |
TAA |
— |
3500 |
— |
900 |
ns |
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(Note 2) |
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Bus free time |
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TBUF |
4700 |
— |
1300 |
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ns |
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Time the bus must be free |
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before a new transmission can |
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start |
Output fall time from VIH min |
TOF |
— |
250 |
20 +0.1 |
250 |
ns |
(Note 1), CB ≤ 100 pF |
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to VIL max |
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CB |
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Input filter spike suppression |
TSP |
— |
50 |
— |
50 |
ns |
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(Note 3) |
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(SDA and SCL pins) |
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Write cycle time |
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TWR |
— |
10 |
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10 |
ms |
Byte or Page mode |
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Endurance |
24LC04B |
— |
10M |
— |
10M |
— |
cycles 25°C, Vcc = 5.0V, Block Mode |
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24LC08B |
— |
1M |
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1M |
— |
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(Note 4) |
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3:The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model whcih can be obtained on our BBS or website.
FIGURE 1-2: BUS TIMING DATA
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TF |
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TR |
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THIGH |
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TLOW |
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SCL |
TSU:STA |
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THD:DAT |
TSU:DAT |
TSU:STO |
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THD:STA |
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SDA |
TSP |
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IN |
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TAA |
THD:STA |
TAA |
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TBUF |
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SDA |
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OUT |
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1996 Microchip Technology Inc. |
DS21051E-page 3 |
24LC04B/08B
2.0FUNCTIONAL DESCRIPTION
The 24LC04B/08B supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24LC04B/08B works as slave. Both, master and slave can operate as transmitter or receiver but the master device determines which mode is activated.
3.0BUS CHARACTERISTICS
The following bus protocol has been defined:
•Data transfer may be initiated only when the bus is not busy.
•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been defined (Figure 3-1).
3.1Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
3.3Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
3.4Data Valid (D)
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last 16 will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion.
3.5Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.
Note: The 24LC04B/08B does not generate any acknowledge bits if an internal programming cycle is in progress.
The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL |
(A) |
(B) |
(D) |
(D) |
(C) |
(A) |
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SDA |
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START |
ADDRESS OR |
DATA |
STOP |
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CONDITION |
ACKNOWLEDGE |
ALLOWED |
CONDITION |
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VALID |
TO CHANGE |
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DS21051E-page 4 |
1996 Microchip Technology Inc. |