Microchip Technology Inc 28C04AFT-15-L, 28C04AF-25I-P, 28C04AF-25I-L, 28C04AF-25-P, 28C04AF-25-L Datasheet

28C04A

4K (512 x 8) CMOS EEPROM

FEATURES

•Fast Read Access Time—150 ns

•CMOS Technology for Low Power Dissipation

-30 mA Active

-100 A Standby

• Fast Byte Write Time—200 s or 1 ms

•Data Retention >200 years

•Endurance - Minimum 104 Erase/Write Cycles

-Automatic Write Operation

-Internal Control Timer

-Auto-Clear Before Write Operation

-On-Chip Address and Data Latches

•Data Polling

•Chip Clear Operation

•Enhanced Data Protection

-VCC Detector

-Pulse Filter

-Write Inhibit

•5-Volt-Only Operation

•Organized 512x8 JEDEC standard pinout

-24-pin Dual-In-Line Package

-32-pin PLCC Package

•Available for Extended Temperature Ranges:

-Commercial: 0˚C to +70˚C

-Industrial: -40˚C to +85˚C

DESCRIPTION

The Microchip Technology Inc. 28C04A is a CMOS 4K non-volatile electrically Erasable and Programmable Read Only Memory (EEPROM). The 28C04A is accessed like a static RAM for the read or write cycles without the need of external components. During a “byte write”, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. To determine when a write cycle is complete, the 28C04A uses Data polling. Data polling allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications.

1996 Microchip Technology Inc.

PACKAGE TYPES

DIP	A7		• 1						24	Vcc
	A6		2						23	A8
	A5		3						22	NC
	A4		4			28C04A			21	WE
	A3		5						20	OE
	A2		6						19	NC
	A1		7						18	CE
	A0		8						17	I/O7
	I/O0		9						16	I/O6
	I/O1		10						15	I/O5
	I/O2		11						14	I/O4
	VSS		12						13	I/O3
PLCC			A7	NC	NC	NU	Vcc	WE	NC
			4	3	2	1	32	31	30
	A6	5							29	A8
	A5	6							28	NC
	A4	7				28C04A			27	NC
	A3	8							26	NC
	A2	9							25	OE
	A1	10							24	NC
	A0	11							23	CE
	NC	12							22	I/O7
	I/O0	13							21	I/O6
			14	15	16	17	18	19	20
			I/O1	I/O2	Vss	NU	I/O3	I/O4	I/O5

• Pin 1 indicator on PLCC on top of package

BLOCK DIAGRAM

				I/O0	I/O7
VSS		Data Protection
VCC
		Circuitry
CE		Chip Enable/
		Output Enable
OE		Control Logic
WE	Auto Erase/Write		Data	Input/Output
		Timing	Poll	Buffers
	Program Voltage
		Generation
A0		Y		Y Gating
		Decoder
	L
	a
	t
	c
	h	X		4K bit
	e
	s	Decoder		Cell Matrix
A8
				DS11126F-page 1

28C04A

1.0ELECTRICAL CHARACTERISTICS

1.1MAXIMUM RATINGS*

VCC and input voltages w.r.t. VSS .......			-0.6V to + 6.25V
Voltage on		w.r.t. VSS	-0.6V to +13.5V
	OE
Output Voltage w.r.t. VSS .................			-0.6V to VCC+0.6V
Storage temperature ..........................			-65˚C to +125˚C
Ambient temp. with power applied .......			-50˚C to +95˚C

*Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name						Function
A0 - A8						Address Inputs
						Chip Enable
		CE
						Output Enable
	OE
						Write Enable
	WE
I/O0 - I/O7						Data Inputs/Outputs
VCC						+5V Power Supply
VSS						Ground
	NC					No Connect; No Internal Connection
	NU					Not Used; No External Connection is
						Allowed

TABLE 1-2:	READ/WRITE OPERATION DC CHARACTERISTICS
				VCC = +5V ±10%
				Commercial (C): Tamb =					0˚C to +70˚C
				Industrial		(I): Tamb = -40˚C to +85˚C
Parameter		Status	Symbol	Min		Max	Units				Conditions
Input Voltages		Logic ‘1’	VIH	2.0		VCC+1	V
		Logic ‘0’	VIL	-0.1		0.8	V
Input Leakage			ILI	-10		10	A		VIN = -0.1V to VCC+1
Input Capacitance			CIN			10	pF		VIN = 0V; Tamb = 25˚C;
									f = 1 MHz
Output Voltages		Logic ‘1’	VOH	2.4			V		IOH = -400 A
		Logic ‘0’	VOL			0.45	V	IOL = 2.1 mA
Output Leakage			ILO	-10		10	A	VOUT = -0.1V TO VCC + 0.1V
Output Capacitance			COUT			12	pF		VIN = 0V; TAMB = 25˚C;
								f = 1 MHz
Power Supply Current, Active		TTL input	ICC			30	mA		f = 5 MHz (Note 1)
									VCC = 5.5V
Power Supply Current, Standby		TTL input	ICC(S)TTL			2	mA				= VIH (0˚C to +70˚C)
									CE
		TTL input	ICC(S)TTL			3	mA		CE		= VIH (-40˚C to +85˚C)
		CMOS input	ICC(S)CMOS			100	A		CE		= VCC-0.3 to Vcc+1

Note 1: AC power supply current above 5 MHz; 1 mA/MHz.

DS11126F-page 2

1996 Microchip Technology Inc.

28C04A

TABLE 1-3:

READ OPERATION AC CHARACTERISTICS

AC Testing Waveform:

VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V

Output Load:

1 TTL Load + 100 pF

Input Rise and Fall Times: 20 ns

Ambient Temperature:

Commercial (C): Tamb =

0˚C to +70˚C

Industrial

(I):

Tamb

=

-40˚C to +85˚C

Parameter

Sym

28C04A-15

28C04A-20

28C04A-25

Units

Conditions

Min

Max

Min

Max

Min

Max

Address to Output Delay

tACC

150

200

250

ns

=

= VIL

OE

CE

to Output Delay

tCE

150

200

250

ns

= VIL

CE

OE

to Output Delay

tOE

70

80

100

ns

= VIL

OE

CE

to

High Output Float

tOFF

0

50

0

55

0

70

ns

CE

OE

Output Hold from Address,

tOH

0

0

0

ns

CE

or

OE,

whichever occurs first

Endurance

—

1M

—

1M

—

1M

—

cycles 25

°C, Vcc =

5.0V, Block

Mode (Note)

Note: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-1: READ WAVEFORMS

Address	VIH	Address Valid
	VIL
	VIH
CE	VIL
			tCE(2)
	VIH
OE						tOFF(1,3)
	VIL
				tOE(2)		tOH
	VOH					High Z
Data	High Z
	VOL					Valid Output

tACC

VIH

WE

VIL

Notes: (1) tOFF is specified for OE or CE, whichever occurs first

(2)OE may be delayed up to tCE - t OE after the falling edge of CE without impact on tCE

(3)This parameter is sampled and is not 100% tested

1996 Microchip Technology Inc.

DS11126F-page 3