Microchip Technology Inc 24LC65-I-SM, 24LC65-SM, 24LC65-P, 24LC65T-I-SM, 24LC65T-I-P Datasheet

24LC65

64K 2.5V I2C Smart Serial EEPROM

FEATURES

PACKAGE TYPES

•Voltage operating range: 2.5V to 6.0V

-Peak write current 3 mA at 6.0V

-Maximum read current 150 A at 6.0V

-Standby current 1 A typical

•Industry standard two wire bus protocol I2C compatible

•8 byte page, or byte modes available

•2 ms typical write cycle time, byte or page

•64-byte input cache for fast write loads

•Up to 8 devices may be connected to the same bus for up to 512K bits total memory

•Including 100 kHz (2.5V) and 400 kHz (5.0V) compatibility

•Programmable block security options

•Programmable endurance options

•Schmitt trigger, filtered inputs for noise suppression

•Output slope control to eliminate ground bounce

•Self-timed ERASE and WRITE cycles

•Power on/off data protection circuitry

•Endurance:

-10,000,000 E/W cycles guaranteed for a High Endurance Block

-1,000,000 E/W cycles guaranteed for a Standard Endurance Block

•Electrostatic discharge protection > 4000V

•Data retention > 200 years

•8-pin PDIP/SOIC packages

•Temperature ranges

-	Commercial (C):	0°C	to	+70°C
-	Industrial (I)	-40°C	to	+85°C

DESCRIPTION

The Microchip Technology Inc. 24LC65 is a “smart” 8K x 8 Serial Electrically Erasable PROM. This device has been developed for advanced, low power applications such as personal communications, and provides the systems designer with flexibility through the use of many new user-programmable features. The 24LC65 offers a relocatable 4K bit block of ultra-high-endurance memory for data that changes frequently. The remainder of the array, or 60K bits, is rated at 1,000,000 ERASE/WRITE (E/W) cycles guaranteed. The 24LC65 features an input cache for fast write loads with a capacity of eight pages, or 64 bytes. This device also features programmable security options for E/W protection of critical data and/or code of up to fifteen 4K

PDIP

	A0		1		8	VCC
	A1		2	24LC65	7	NC
	A2	3			6	SCL
	VSS		4		5	SDA

SOIC

A0			1		8			VCC
				24LC65	7
A1			2					NC
		3			6
A2					5			SCL
VSS			4					SDA

BLOCK DIAGRAM

			A0..A2		HV Generator
	I/O		Memory	XDEC	EEPROM ARRAY
	Control		Control
	Logic		Logic		Page Latches
					Cache
	I/O	SCL
					YDEC
	SDA
		Vcc
		Vss			Sense AMP
					R/W Control

blocks. Functional address lines allow the connection of up to eight 24LC65's on the same bus for up to 512K bits contiguous EEPROM memory. Advanced CMOS technology makes this device ideal for low-power nonvolatile code and data applications. The 24LC65 is available in the standard 8-pin plastic DIP and 8-pin surface mount SOIC package.

I2C is a trademark of Philips Corporation.

Smart Serial is a trademark of Microchip Technology Inc.

1996 Microchip Technology Inc.

DS21073E-page 1

24LC65

1.0ELECTRICAL CHARACTERISTICS

1.1Maximum Ratings*

VCC...................................................................................		7.0V
All inputs and outputs w.r.t. VSS...............	-0.6V to VCC +1.0V
Storage temperature ......................................		-65˚C to+150˚C
Ambient temp. with power applied ................		-65˚C to +125˚C
Soldering temperature of leads (10 seconds)		............. +300˚C
ESD protection on all pins ..................................................		≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1:	PIN FUNCTION TABLE
Name	Function
A0..A2	User Configurable Chip Selects
Vss	Ground
SDA	Serial Address/Data/I/O
SCL	Serial Clock
VCC	+2.5V to 6.0V Power Supply
NC	No Internal Connection

TABLE 1-2:	DC CHARACTERISTICS
				VCC = +2.5V to +6.0V
				Commercial (C):		Tamb = 0°C to +70°C
				Industrial	(I):	Tamb = -40°C to +85°C
Parameter		Sym	Min	Max	Units	Conditions
A0, A1, A2, SCL and SDA pins:
High level input voltage		VIH	.7 Vcc	—	V
Low level input voltage		VIL	—	.3 VCC	V
Hysteresis of Schmitt Trigger inputs		VHYS	.05 VCC	—	V	(Note 1)
Low level output voltage		VOL	—	.40	V	IOL = 3.0 mA
Input leakage current		ILI	-10	10	A	VIN = .1V to VCC
Output leakage current		ILO	-10	10	A	VOUT = .1V to VCC
Pin capacitance		CIN, COUT	—	10	pF	V CC = 5.0V (Note 1)
(all inputs/outputs)						Tamb = 25˚C, Fclk = 1 MHz
Operating current		ICC WRITE	—	3	mA	VCC = 6.0V, SCL = 400 kHz
		ICC Read	—	150	A	VCC = 6.0V, SCL = 400 kHz
Standby current		ICCS	—	5	A	VCC = 5.0V, SCL = SDA = VCC
						(Note 1)

Note 1: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:	BUS TIMING START/STOP
	VHYS
SCL
	THD:STA	TSU:STO
TSU:STA
SDA
	START	STOP

DS21073E-page 2

1996 Microchip Technology Inc.

									24LC65
TABLE 1-3:	AC CHARACTERISTICS
			Vcc = 2.5V-6.0V		VCC = 4.5-6.0V
Parameter		Symbol	STD. MODE		FAST MODE		Units		Remarks
			Min	Max	Min	Max
Clock frequency		FCLK	—	100	—	400	kHz
Clock high time		THIGH	4000	—	600	—	ns
Clock low time		TLOW	4700	—	1300	—	ns
SDA and SCL rise time		TR	—	1000	—	300	ns		(Note 1)
SDA and SCL fall time		TF	—	300	—	300	ns		(Note 1)
START condition setup time		THD:STA	4000	—	600	—	ns	After this period the first
									clock pulse is generated
START condition setup time		TSU:STA	4700	—	600	—	ns	Only relevant for
									repeated START condi-
									tion
Data input hold time		THD:DAT	0	—	0	—	ns
Data input setup time		TSU:DAT	250	—	100	—	ns
STOP condition setup time		TSU:STO	4000	—	600	—	ns
Output valid from clock		TAA	—	3500	—	900	ns	(Note 2)
Bus free time		TBUF	4700	—	1300	—	ns	Time the bus must be
									free before a new trans-
									mission can start
Output fall time from VIH min to		TOF	—	250	20 + 0.1	250	ns		(Note 1), CB ≤ 100 pF
VIL max					CB
Input filter spike suppression		TSP	—	50	—	50	ns	Note 3
(SDA and SCL pins)
Write cycle time		TWR	—	5	—	5	ms/page	(Note 4)
Endurance									25°C, Vcc = 5.0V, Block
High Endurance Block			10M	—	10M	—	cycles
Rest of Array			1M	—	1M	—			Mode (Note 5)

Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF.

2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3:The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation.

4:The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write cache for total time.

5:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2:		BUS TIMING DATA
		TF		TR
		THIGH
		TLOW
SCL
	TSU:STA	THD:DAT	TSU:DAT	TSU:STO
		THD:STA
SDA		TSP
IN				TBUF
			TAA
		TAA
SDA
OUT

1996 Microchip Technology Inc.

DS21073E-page 3

24LC65

2.0FUNCTIONAL DESCRIPTION

The 24LC65 supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24LC65 works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated.

3.0BUS CHARACTERISTICS

The following bus protocol has been defined:

•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined (Figure 3-1).

3.1Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

3.3Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

3.4Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device.

3.5Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.

Note: The 24LC65 does not generate any acknowledge bits if an internal programming cycle is in progress.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24LC65) must leave the data line HIGH to enable the master to generate the STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)	(B)	(D)	(D)	(C)	(A)
SCL
SDA
	START	ADDRESS OR	DATA	STOP
CONDITION		ACKNOWLEDGE	ALLOWED	CONDITION
		VALID	TO CHANGE

DS21073E-page 4

1996 Microchip Technology Inc.