August 1986
Revised April 2000
DM74S112
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig- gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. Data on the J and K inputs can be changed while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
Ordering Code:
Order Number |
Package Number |
Package Description |
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DM74S112 |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Connection Diagram |
Function Table |
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Inputs |
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Outputs |
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PR |
CLR |
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CLK |
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J |
K |
Q |
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Q |
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L |
H |
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X |
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X |
X |
H |
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L |
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H |
L |
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X |
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X |
X |
L |
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H |
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L |
L |
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X |
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X |
X |
H* |
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H* |
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H |
H |
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↓ |
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L |
L |
Q0 |
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Q |
0 |
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H |
H |
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↓ |
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H |
L |
H |
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L |
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H |
H |
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↓ |
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L |
H |
L |
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H |
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H |
H |
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↓ |
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H |
H |
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Toggle |
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H |
H |
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H |
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X |
X |
Q0 |
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Q |
0 |
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H = HIGH Logic Level |
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X = |
Either LOW or HIGH Logic Level |
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L = |
LOW Logic Level |
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↓ = |
Negative going edge of pulse. |
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Q0 = The output logic level of Q before the indicated input conditions were |
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established. |
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* = |
This configuration is nonstable; that is, it will not persist when either the |
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preset and/or clear inputs return to its inactive (HIGH) level.
Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse.
Complementary and Clear, Preset, with Flop-Flip K-J Slave-Master Triggered-Edge-Negative Dual DM74S112
Outputs
© 2000 Fairchild Semiconductor Corporation |
DS006459 |
www.fairchildsemi.com |
DM74S112
Absolute Maximum Ratings(Note 1)
Supply Voltage |
7V |
Note 1: The “Absolute Maximum Ratings” are those values beyond which |
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the safety of the device cannot be guaranteed. The device should not be |
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Input Voltage |
5.5V |
operated at these limits. The parametric values defined in the Electrical |
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Characteristics tables are not guaranteed at the absolute maximum ratings. |
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Operating Free Air Temperature Range |
0° C to + 70° C |
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The “Recommended Operating Conditions” table will define the conditions |
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Storage Temperature Range |
− 65° C to + 150° C |
for actual device operation. |
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Recommended Operating Conditions
Symbol |
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Parameter |
Min |
Nom |
Max |
Units |
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VCC |
Supply Voltage |
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4.75 |
5 |
5.25 |
V |
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VIH |
HIGH Level Input Voltage |
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2 |
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V |
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VIL |
LOW Level Input Voltage |
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0.8 |
V |
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IOH |
HIGH Level Output Current |
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− 1 |
mA |
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IOL |
LOW Level Output Current |
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20 |
mA |
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fCLK |
Clock Frequency (Note 2) |
0 |
125 |
80 |
MHz |
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fCLK |
Clock Frequency (Note 3) |
0 |
80 |
60 |
MHz |
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tW |
Pulse Width |
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Clock HIGH |
6 |
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(Note 2) |
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Clock LOW |
6.5 |
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ns |
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Clear LOW |
8 |
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Preset LOW |
8 |
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tW |
Pulse Width |
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Clock HIGH |
8 |
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(Note 3) |
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Clock LOW |
8 |
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ns |
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Clear LOW |
10 |
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Preset LOW |
10 |
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tSU |
Setup Time (Note 4)(Note 5) |
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7↓ |
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ns |
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tH |
Input Hold Time (Note 4)(Note 5) |
0↓ |
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ns |
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TA |
Free Air Operating Temperature |
0 |
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70 |
° C |
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Note 2: CL = 15 pF, |
RL = 280Ω , TA = |
25° C and VCC = |
5V. |
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Note 3: CL = 50 pF, RL = 280Ω , TA = |
25° C and VCC = |
5V. |
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Note 4: TA = 25° C and VCC = 5V. |
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Note 5: The symbol (↓ ) indicates the falling edge at the clock pulse is used for reference.
www.fairchildsemi.com |
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