Fairchild Semiconductor DM81LS97AN, DM81LS95AWM, DM81LS95AN Datasheet

September 1991

Revised May 1999

DM81LS95A • DM81LS96A • DM81LS97A

3-STATE Octal Buffer

General Description

These devices provide eight, two-input buffers in each package. All employ low-power-Schottky TTL technology. One of the two inputs to each buffer is used as a control line to gate the output into the high-impedance state, while the other input passes the data through the buffer. The DM81LS95A and DM81LS97A present true data at the outputs, while the DM81LS96A is inverting. On the DM81LS95A and DM81LS96A versions, all eight 3-STATE enable lines are common, with access through a 2-input NOR gate. On the DM81LS97A version, four buffers are enabled from one common line, and the other four buffers are enabled form another common line. In all cases the outputs are placed in the 3-STATE condition by applying a high logic level to the enable pins.

Features

■ Typical power dissipation
DM81LS95A, DM81LS97A	80 mW
DM81LS96A	65 mW
■ Typical propagation delay
DM81LS95A, DM81LS97A	15 ns
DM81LS96A	10 ns

■ Low power-Schottky, 3-STATE technology

Ordering Code:

Order Number	Package Number	Package Description
DM81LS95AWM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM81LS95AN	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM81LS96AWM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM81LS96AN	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM81LS97AN	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

DM81LS95A and DM92LS96A

	Pin Names						Descriptions
	A1–A8						Inputs
	Y1–Y8						Outputs
							Active LOW Output Enables (Note 1)
		G1–G2

Note 1: Both G1 and G2 must be LOW for outputs to be enabled.

			DM81LS97A
	Pin Names		Descriptions
	A1–A8		Inputs
	Y1–Y8		Outputs
			Active LOW Output Enable (Y1–Y4)
	G1
			Active LOW Output Enable (Y5–Y8)
	G2

Buffer Octal STATE-3 DM81LS97A • DM81LS96A • DM81LS95A

© 1999 Fairchild Semiconductor Corporation

DS006435

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DM81LS95A • DM81LS96A • DM81LS97A

Logic Symbols

DM81LS95A

DM81LS96A

DM81LS97A

Truth Tables

DM81LS95A

			Inputs				Output
	G1			G2		A	Y
	H			X		X	Hi-Z
	X			H		X	Hi-Z
	L			L		H	H
	L			L		L	L

DM81LS96A

			Inputs				Output
	G1			G2		A	Y
	H			X		X	Hi-Z
	X			H		X	Hi-Z
	L			L		H	L
	L			L		L	H

DM81LS97A

		Inputs		Output
	G1		A1–A4	Y1–Y4
	H		X	Hi-Z
	L		H	H
	L		L	L

G2	A5–A6	Y5–Y8
H	X	Hi-Z
L	H	H
L	L	L

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2

Absolute Maximum Ratings(Note 2)

Supply Voltage	7V
Input Voltage	7V
Operating Free Air Temperature Range	0°C to +70°C
Storage Temperature Range	−65°C to +150°C

Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol	Parameter	Min	Nom	Max	Units
VCC	Supply Voltage	4.75	5	5.25	V
VIH	HIGH Level Input Voltage	2			V
VIL	LOW Level Input Voltage			0.8	V
IOH	HIGH Level Output Current			−5.2	mA
IOL	LOW Level Output Current			24	mA
TA	Free Air Operating Temperature	0		70	°C

DM81LS97A • DM81LS96A • DM81LS95A

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