Fairchild Semiconductor DM74S374WM, DM74S374N, DM74S373WM, DM74S373N Datasheet

August 1986

Revised May 2000

DM74S373 • DM74S374

3-STATE Octal D-Type Transparent Latches

and Edge-Triggered Flip-Flops

General Description

These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the DM74S373 are transparent D-type latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up.

The eight flip-flops of the DM74S374 are edge-triggered D- type flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.

Features

■Choice of 8 latches or 8 D-type flip-flops in a single package

■3-STATE bus-driving outputs

■Full parallel-access for loading

■Buffered control inputs

■P-N-P input reduce D-C loading on data lines

Ordering Code:

Order Number	Package Number	Package Description
DM74S373WM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74S373N	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74S374WM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74S374N	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

DM74S374N

DM74S373N

Flops-Flip Triggered-Edge and Latches Transparent Type-D Octal STATE-3 DM74S374 • DM74S373

© 2000 Fairchild Semiconductor Corporation

DS006486

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DM74S373 • DM74S374

Truth Tables

DM74S373

		Output	Enable	D	Output
		Control	G
		L	H	H	H
		L	H	L	L
		L	L	X	Q0
		H	X	X	Z
H =		HIGH Level (Steady State)
L =		LOW Level (Steady State)
X =		Don’t Care
Z =		High Impedance State
↑ =		Transition from LOW-to-HIGH level,
Q0		= The level of the output before steady-state input conditions were

established.

Logic Diagrams

74S373 Transparent Latches

DM74S374

Output	Clock	D	Output
Control
L	↑	H	H
L	↑	L	L
L	L	X	Q0
H	X	X	Z

74S374 Positive-Edge-Triggered Flip-Flops

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2

Absolute Maximum Ratings(Note 1)

	Supply Voltage	7V	Note 1: The “Absolute Maximum Ratings” are those values beyond which
			the safety of the device cannot be guaranteed. The device should not be
	Input Voltage	5.5V	operated at these limits. The parametric values defined in the Electrical
			Characteristics tables are not guaranteed at the absolute maximum ratings.
	Operating Free Air Temperature Range	0° C to + 70° C
			The “Recommended Operating Conditions” table will define the conditions
	Storage Temperature Range	− 65° C to + 150° C	for actual device operation.

DM74S373 Recommended Operating Conditions

Symbol		Parameter			Min	Nom	Max	Units
VCC		Supply Voltage			4.75	5	5.25	V
VIH		HIGH Level Input Voltage			2			V
VIL		LOW Level Input Voltage					0.8	V
IOH		HIGH Level Output Current					− 6.5	mA
IOL		LOW Level Output Current					20	mA
tW		Pulse Width (Note 2)		Enable HIGH	6			ns
				Enable LOW	7.3
tW		Pulse Width (Note 3)		Enable HIGH	15			ns
				Enable LOW	15			ns
tSU		Data Setup Time (Note 4)(Note 5)			0↓			ns
tH		Data Hold Time (Note 4)(Note 5)			10↓			ns
TA		Free Air Operating Temperature			0		70	° C
Note 2: CL =	15 pF,	RL = 280Ω , TA = 25° C and VCC = 5V.
Note 3: CL =	50 pF and RL = 280Ω , TA = 25° C and VCC =		5V.
Note 4: The symbol (↓ ) indicates the falling edge of the clock pulse is used for reference.
Note 5: TA =	25° C and VCC = 5V.

DM74S373 Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted)

Symbol	Parameter		Conditions		Min	Typ	Max	Units
						(Note 6)
VI	Input Clamp Voltage	VCC =	Min, II = −	18 mA			− 1.2	V
VOH	HIGH Level	VCC =	Min, IOH =	Max	2.4	3.2		V
	Output Voltage	VIL =	Max, VIH =	Min
VOL	LOW Level	VCC =	Min, IOL =	Max			0.5	V
	Output Voltage	VIH =	Min, VIL =	Max
II	Input Current @ Max Input Voltage	VCC =	Max, VI =	5.5V			1	mA
IIH	HIGH Level Input Current	VCC =	Max, VI =	2.7V			50	µ A
IIL	LOW Level Input Current	VCC =	Max, VI =	0.5V			− 250	µ A
IOZH	Off-State Output Current with	VCC =	Max, VO =	2.4V			50	µ A
	HIGH Level Output Voltage Applied	VIH =	Min, VIL =	Max
IOZL	Off-State Output Current with	VCC =	Max, VO =	0.5V			− 50	µ A
	LOW Level Output Voltage Applied	VIH =	Min, VIL =	Max
IOS	Short Circuit Output Current	VCC =	Max (Note 7)		− 40		− 100	mA
ICC	Supply Current	VCC =	Max	Outputs HIGH or LOW		105	160	mA
				Outputs Disabled			190
Note 6: All	typicals are at VCC = 5V, TA = 25° C.

Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second.

DM74S374 • DM74S373

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