Fairchild Semiconductor DM74S74N, DM74S74MX, DM74S74M, DM74S74CW Datasheet

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Fairchild Semiconductor DM74S74N, DM74S74MX, DM74S74M, DM74S74CW Datasheet

August 1986

Revised April 2000

DM74S74

Dual Positive-Edge-Triggered D Flip-Flops

with Preset, Clear, and Complementary Outputs

General Description

This device contains two independent positive-edge-trig- gered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

Ordering Code:

Order Number

Package Number

Package Description

 

 

 

DM74S74M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

 

 

 

DM74S74N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

 

 

 

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Inputs

 

 

Outputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PR

CLR

 

CLK

D

Q

 

 

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

 

X

X

H

 

 

L

 

 

H

L

 

X

X

L

 

 

H

 

 

L

L

 

X

X

H*

 

 

H*

 

 

H

H

 

H

H

 

 

L

 

 

H

H

 

L

L

 

 

H

 

 

H

H

 

L

X

Q0

 

 

 

 

 

 

 

Q

0

 

H

= HIGH Logic Level

 

 

 

 

 

 

 

 

X = Either LOW or HIGH Logic Level

 

 

 

 

 

 

 

L = LOW Logic Level

 

 

 

 

 

 

 

 

↑ = Positive-going Transition

 

 

 

 

 

 

 

 

* = This configuration is nonstable; that is, it will not persist when either the

preset and/or clear inputs return to its inactive (HIGH) level.

Q0 = The output logic level of Q before the indicated input conditions were established.

Outputs Complementary and Clear, Preset, with Flops-Flip D Triggered-Edge-Positive Dual DM74S74

© 2000 Fairchild Semiconductor Corporation

DS006457

www.fairchildsemi.com

DM74S74

Absolute Maximum Ratings(Note 1)

Supply Voltage

7V

Note 1: The “Absolute Maximum Ratings” are those values beyond which

the safety of the device cannot be guaranteed. The device should not be

Input Voltage

5.5V

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

Operating Free Air Temperature Range

0° C to + 70° C

The “Recommended Operating Conditions” table will define the conditions

Storage Temperature Range

− 65° C to + 150° C

for actual device operation.

 

Recommended Operating Conditions

Symbol

 

Parameter

Min

Nom

Max

Units

 

 

 

 

 

 

 

VCC

Supply Voltage

 

4.75

5

5.25

V

VIH

HIGH Level Input Voltage

2

 

 

V

VIL

LOW Level Input Voltage

 

 

 

0.8

V

IOH

HIGH Level Output Current

 

 

− 1

mA

IOL

LOW Level Output Current

 

 

20

mA

fCLK

Clock Frequency (Note 2)

0

110

75

MHz

fCLK

Clock Frequency (Note 3)

0

95

65

MHz

tW

Pulse Width

 

Clock HIGH

6

 

 

 

 

(Note 2)

 

Clock LOW

7.3

 

 

ns

 

 

 

 

 

 

 

 

 

 

Clear LOW

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Preset LOW

7

 

 

 

 

 

 

 

 

 

 

 

tW

Pulse Width

 

Clock HIGH

8

 

 

 

 

(Note 3)

 

Clock LOW

9

 

 

ns

 

 

 

 

 

 

 

 

 

 

Clear LOW

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Preset LOW

9

 

 

 

 

 

 

 

 

 

 

tSU

Setup Time (Note 2)(Note

4)

3↑

 

 

ns

tSU

Setup Time (Note 3)(Note 4)

3↑

 

 

ns

tH

Input Hold Time (Note 2)(Note 4)

2↑

 

 

ns

tH

Input Hold Time (Note 3)(Note 4)

2↑

 

 

ns

TA

Free Air Operating Temperature

0

 

70

° C

Note 2: CL = 15 pF, RL = 280Ω , TA =

25° C and VCC =

5V.

 

 

 

 

Note 3: CL = 50 pF, RL = 280Ω , TA =

25° C and VCC =

5V.

 

 

 

 

Note 4: The symbol (↑ ) indicates the rising edge at the clock pulse is used for reference.

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