SGS Thomson Microelectronics ST7FLITE29F2M6, ST7FLITE29F2B6, ST7FLITE29, ST7FLITE25F2M6, ST7FLITE25F2B6 Datasheet

ST7LITE2

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI

■Memories

–8 Kbytes single voltage Flash Program memory with read-out protection, In-Circuit Programming and In-Application programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55°C.

–384 bytes RAM

–256 bytes data EEPROM with read-out protection. 300K write/erase cycles guaranteed, data retention: 20 years at 55°C.

■Clock, Reset and Supply Management

–Enhanced reset system

–Enhanced low voltage supervisor (LVD) for main supply and an auxiliary voltage detector (AVD) with interrupt capability for implementing safe power-down procedures

–Clock sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock

–Internal 32-MHz input clock for Auto-reload timer

–Optional x4 or x8 PLL for 4 or 8 MHz internal clock

–Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

■I/O Ports

–Up to 15 multifunctional bidirectional I/O lines

–7 high sink outputs

■4 Timers

–Configurable Watchdog Timer

–Two 8-bit Lite Timers with prescaler, 1 realtime base and 1 input capture

–One 12-bit Auto-reload Timer with 4 PWM

Device Summary

	DIP20	SO20
		300”

outputs, input capture and output compare functions

■1 Communication Interface

–SPI synchronous serial interface

■Interrupt Management

–10 interrupt vectors plus TRAP and RESET

–15 external interrupt lines (on 4 vectors)

■A/D Converter

–7 input channels

–Fixed gain Op-amp

–13-bit resolution for 0 to 430 mV (@ 5V VDD)

–10-bit resolution for 430 mV to 5V (@ 5V VDD)

■Instruction Set

–8-bit data manipulation

–63 basic instructions

–17 main addressing modes

–8 x 8 unsigned multiply instructions

■Development Tools

–Full hardware/software development package

–DM (Debug Module)

	Features	ST7LITE20	ST7LITE25	ST7LITE29
	Program memory - bytes		8K
	RAM (stack) - bytes		384 (128)
	Data EEPROM - bytes	-	-	256
		Lite Timer with Watchdog,	Lite Timer with	Watchdog,
	Peripherals	Autoreload Timer, SPI,	Autoreload Timer with 32-MHz input clock,
		10-bit ADC with Op-Amp	SPI, 10-bit ADC with Op-Amp
	Operating Supply		2.4V to 5.5V
	CPU Frequency	Up to 8Mhz	Up to 8Mhz (w/ ext OSC up to 16MHz
		(w/ ext OSC up to 16MHz)	and int 1MHz RC 1% PLLx8/4MHz)
	Operating Temperature		-40°C to +85°C
	Packages		SO20 300”, DIP20

	Rev. 2.0
August 2003	1/131
	1

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
6.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
6.2	MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
6.3	CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		34
8.1	NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
8.2	EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
8.3	PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		38

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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Table of Contents

10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
10.2	FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
10.3	I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
10.4	UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
10.5	LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
10.6	INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
10.7	DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		51
11.1	WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
11.2	12-BIT AUTORELOAD TIMER 2 (AT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
11.3	LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	65
11.4	SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
11.5	10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		85
12.1	ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	85
12.2	INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	88
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		91

13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 114 13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

120

14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 14.2 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 123

15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		129
16.1	EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	129
16.2	ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	129
16.3	A/ D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . .	129
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ST7LITE2

17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

130

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet

Please also pay special attention to the Section “IMPORTANT NOTES” on page 129.

4/131

ST7LITE2

1 INTRODUCTION

The ST7LITE2 is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.

The ST7LITE2 features FLASH memory with byte-by-byte In-Circuit Programming (ICP) and InApplication Programming (IAP) capability.

Under software control, the ST7LITE2 device can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

For easy reference, all parametric data are located in section 13 on page 91.

The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

Figure 1. General Block Diagram

			PLL
		Int.	8MHz -> 32MHz
		1% RC			12-Bit
		1MHz	PLL x 8
					Auto-Reload
			or PLL X4
					TIMER 2
CLKIN
		/ 2			8-Bit
					LITE TIMER 2
OSC1
	Ext.
OSC2	OSC		Internal			PA7:0
	1MHz
	to		CLOCK		PORT A	(8 bits)
	16MHz					PB6:0
					PORT B
			LVD	ADDRESS		(7 bits)
VDD		POWER			ADC
					+ OpAmp
VSS		SUPPLY
				AND	SPI
RESET		CONTROL		DATA
		8-BIT CORE		BUS
			ALU
					Debug Module
		PROGRAM
		MEMORY			DATA EEPROM
		(8K Bytes)			(256 Bytes)
			RAM
		(384 Bytes)			WATCHDOG

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1

ST7LITE2

2 PIN DESCRIPTION

Figure 2. 20-Pin SO Package Pinout

VSS

OSC1/CLKIN

1

20

VDD

2

19

OSC2

RESET

3

18

PA0 (HS)/LTIC

4

ei0

17

PA1 (HS)/ATIC

SS/AIN0/PB0

SCK/AIN1/PB1

ei3

PA2 (HS)/ATPWM0

5

16

MISO/AIN2/PB2

6

15

PA3 (HS)/ATPWM1

MOSI/AIN3/PB3

7

14

PA4 (HS)/ATPWM2

CLKIN/AIN4/PB4

8

ei2

ei1

13

PA5 (HS)/ATPWM3/ICCDATA

12

PA6/MCO/ICCCLK/BREAK

AIN5/PB5

9

AIN6/PB6

10

11

PA7(HS)

(HS)

20mA high sink capability

eix

associated external interrupt vector

Figure 3. 20-Pin DIP Package Pinout

MISO/AIN2/PB2

1

ei3

ei3

20

SCK/AIN1/PB1

MOSI/AIN3/PB3

2

19

SS/AIN0/PB0

CLKIN/AIN4/PB4

3

ei2

18

RESET

AIN5/PB5

4

17

VDD

AIN6/PB6

5

16

VSS

PA7(HS)

6

15

OSC1/CLKIN

MCO/ICCCLK/BREAK/PA6

7

ei1

14

OSC2

ATPWM3/ICCDATA/PA5(HS)

PA0(HS)/LTIC

8

13

ATPWM2/PA4(HS)

9

ei0 12

PA1(HS)/ATIC

ATPWM1/PA3(HS)

10

ei0

11

PA2(HS)/ATPWM0

(HS)

20mA high sink capability

eix

associated external interrupt vector

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1

ST7LITE2

PIN DESCRIPTION (Cont’d)

Legend / Abbreviations for Table 1:

Type:		I = input, O = output, S = supply
In/Output level:		CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level:		HS = 20mA high sink (on N-buffer only)
Port and control configuration:
–	Input:	float = floating, wpu = weak pull-up, int = interrupt, ana = analog
–	Output:	OD = open drain, PP = push-pull

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Table 1. Device Pin Description

Pin No.

Level

Port / Control

Main

SO20

DIP20

Type

Input

Output

float

wpu

int

ana

OD

PP

Pin Name

Input

Output

Function

Alternate Function

(after reset)

1

16

VSS

S

Ground

2

17

VDD

S

Main power supply

Top priority non maskable interrupt (active

3

18

RESET

I/O

CT

X

X

low)

I/O

CT

X

X

X

X

Port B0

ADC Analog Input 0 or SPI

4

19

PB0/AIN0/SS

Slave Select (active low)

ei3

5

20

PB1/AIN1/SCK

I/O

CT

X

X

X

X

Port B1

ADC Analog Input 1 or SPI Se-

rial Clock

6

1

PB2/AIN2/MISO

I/O

CT

X

X

X

X

Port B2

ADC Analog Input 2 or SPI

Master In/ Slave Out Data

7

2

PB3/AIN3/MOSI

I/O

CT

X

X

X

X

Port B3

ADC Analog Input 3 or SPI

Master Out / Slave In Data

8

3

PB4/AIN4/CLKIN

I/O

CT

X

ei2

X

X

X

Port B4

ADC Analog Input 4 or Exter-

nal clock input

9

4

PB5/AIN5

I/O

CT

X

X

X

X

Port B5

ADC Analog Input 5

10

5

PB6/AIN6

I/O

CT

X

X

X

X

Port B6

ADC Analog Input 6

11

6

PA7

I/O

CT

HS

X

ei1

X

X

Port A7

Main Clock Output or In Circuit

Communication Clock or Ex-

ternal BREAK

PA6 /MCO/

Caution: During reset, this pin

12

7

I/O

CT

X

ei1

X

X

Port A6

must be held at high level to

ICCCLK/BREAK

avoid entering ICC mode un-

expectedly (this is guaranteed

by the internal pull-up if the ap-

plication leaves the pin float-

ing).

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1

ST7LITE2

Pin No.

Level

Port / Control

Main

SO20

DIP20

Type

Input

Output

float

wpu

int

ana

OD

PP

Pin Name

Input

Output

Function

Alternate Function

(after reset)

13

8

PA5 /ATPWM3/

I/O

CT

HS

X

X

X

Port A5

Auto-Reload Timer PWM3 or

ICCDATA

ei1

In Circuit Communication Data

14

9

PA4/ATPWM2

I/O

CT

HS

X

X

X

Port A4

Auto-Reload Timer PWM2

15

10

PA3/ATPWM1

I/O

CT

HS

X

X

X

Port A3

Auto-Reload Timer PWM1

16

11

PA2/ATPWM0

I/O

CT

HS

X

ei0

X

X

Port A2

Auto-Reload Timer PWM0

17

12

PA1/ATIC

I/O

CT

HS

X

X

X

Port A1

Auto-Reload Timer Input Cap-

ture

18

13

PA0/LTIC

I/O

CT

HS

X

X

X

Port A0

Lite Timer Input Capture

19

14

OSC2

O

Resonator oscillator inverter output

20

15

OSC1/CLKIN

I

Resonator oscillator inverter input or Exter-

nal clock input

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3 REGISTER & MEMORY MAP

As shown in Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 256 bytes of data EEPROM and 8 Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh.

The highest address bytes contain the user reset and interrupt vectors.

The Flash memory contains two sectors (see Figure 4) mapped in the upper part of the ST7 ad-

Figure 4. Memory Map

dressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).

The size of Flash Sector 0 and other device options are configurable by Option byte (refer to section 15.1 on page 123).

IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the device.l

	0080h	Short Addressing
	00FFh	RAM (zero page)
0000h
HW Registers	0100h	16-bit Addressing
(see Table 2)
007Fh		RAM
0080h
	017Fh
RAM
(384 Bytes)	0180h
01FFh		128 Bytes Stack
0200h	01FFh
Reserved
0FFFh
1000h		1000h
Data EEPROM
(256 Bytes)			RCCR0
10FFh			RCCR1
1100h
		1001h
Reserved		8K FLASH	see section 7.1 on page 23
		PROGRAM MEMORY
DFFFh
E000h	E000h	7 Kbytes
Flash Memory	FBFFh	SECTOR 1
(8K)	FC00h	1 Kbyte
	FFFFh	SECTOR 0
FFDFh
FFE0h		FFDEh	RCCR0
Interrupt & Reset Vectors
(see Table 5)			RCCR1
FFFFh		FFDFh
			see section 7.1 on page 23
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ST7LITE2

Table 2. Hardware Register Map

	Address	Block	Register Label	Register Name	Reset Status	Remarks
	0000h		PADR	Port A Data Register	FFh1)	R/W
	0001h	Port A	PADDR	Port A Data Direction Register	00h	R/W
	0002h		PAOR	Port A Option Register	40h	R/W
	0003h		PBDR	Port B Data Register	FFh 1)	R/W
	0004h	Port B	PBDDR	Port B Data Direction Register	00h	R/W
	0005h		PBOR	Port B Option Register	00h	R/W2)
	0006h			Reserved Area (2 bytes)
	0007h
	0008h		LTCSR2	Lite Timer Control/Status Register 2	0Fh	R/W
	0009h	LITE	LTARR	Lite Timer Auto-reload Register	00h	R/W
	000Ah		LTCNTR	Lite Timer Counter Register	00h	Read Only
		TIMER 2
	000Bh		LTCSR1	Lite Timer Control/Status Register 1	0X00 0000h	R/W
	000Ch		LTICR	Lite Timer Input Capture Register	xxh	Read Only
	000Dh		ATCSR	Timer Control/Status Register	0X00 0000h	R/W
	000Eh		CNTRH	Counter Register High	00h	Read Only
	000Fh		CNTRL	Counter Register Low	00h	Read Only
	0010h		ATRH	Auto-Reload Register High	00h	R/W
	0011h		ATRL	Auto-Reload Register Low	00h	R/W
	0012h		PWMCR	PWM Output Control Register	00h	R/W
	0013h		PWM0CSR	PWM 0 Control/Status Register	00h	R/W
	0014h		PWM1CSR	PWM 1 Control/Status Register	00h	R/W
	0015h	AUTO-	PWM2CSR	PWM 2 Control/Status Register	00h	R/W
	0016h		PWM3CSR	PWM 3 Control/Status Register	00h	R/W
	0017h	RELOAD	DCR0H	PWM 0 Duty Cycle Register High	00h	R/W
	0018h	TIMER 2	DCR0L	PWM 0 Duty Cycle Register Low	00h	R/W
	0019h		DCR1H	PWM 1 Duty Cycle Register High	00h	R/W
	001Ah		DCR1L	PWM 1 Duty Cycle Register Low	00h	R/W
	001Bh		DCR2H	PWM 2 Duty Cycle Register High	00h	R/W
	001Ch		DCR2L	PWM 2 Duty Cycle Register Low	00h	R/W
	001Dh		DCR3H	PWM 3 Duty Cycle Register High	00h	R/W
	001Eh		DCR3L	PWM 3 Duty Cycle Register Low	00h	R/W
	001Fh		ATICRH	Input Capture Register High	00h	Read Only
	0020h		ATICRL	Input Capture Register Low	00h	Read Only
	0021h		TRANCR	Transfer Control Register	01h	R/W
	0022h		BREAKCR	Break Control Register	00h	R/W
	0023h to			Reserved area (11 bytes)
	002Dh
	002Eh	WDG	WDGCR	Watchdog Control Register	7Fh	R/W
	0002Fh	FLASH	FCSR	Flash Control/Status Register	00h	R/W
	00030h	EEPROM	EECSR	Data EEPROM Control/Status Register	00h	R/W
	0031h		SPIDR	SPI Data I/O Register	xxh	R/W
	0032h	SPI	SPICR	SPI Control Register	0xh	R/W
	0033h		SPICSR	SPI Control Status Register	00h	R/W
	0034h		ADCCSR	A/D Control Status Register	00h	R/W
	0035h	ADC	ADCDRH	A/D Data Register High	xxh	Read Only
	0036h		ADCDRL	A/D Amplifier Control/Data Low Register	0xh	R/W

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						ST7LITE2
	Address	Block	Register Label	Register Name	Reset Status	Remarks
	0037h	ITC	EICR	External Interrupt Control Register	00h	R/W
	0038h	MCC	MCCSR	Main Clock Control/Status Register	00h	R/W
	0039h	Clock and	RCCR	RC oscillator Control Register	FFh	R/W
	003Ah	Reset	SICSR	System Integrity Control/Status Register	0000 0XX0h	R/W
	003Bh			Reserved area (1 byte)
	003Ch	ITC	EISR	External Interrupt Selection Register	0Ch	R/W
	003Dh to			Reserved area (12 bytes)
	0048h
	0049h	AWU	AWUPR	AWU Prescaler Register	FFh	R/W
	004Ah		AWUCSR	AWU Control/Status Register	00h	R/W
	004Bh		DMCR	DM Control Register	00h	R/W
	004Ch		DMSR	DM Status Register	00h	R/W
	004Dh	DM3)	DMBK1H	DM Breakpoint Register 1 High	00h	R/W
	004Eh		DMBK1L	DM Breakpoint Register 1 Low	00h	R/W
	004Fh		DMBK2H	DM Breakpoint Register 2 High	00h	R/W
	0050h		DMBK2L	DM Breakpoint Register 2 Low	00h	R/W
	0051h to			Reserved area (47 bytes)
	007Fh

Legend: x=undefined, R/W=read/write

Notes:

1.The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

2.The bits associated with unavailable pins must always keep their reset value.

3.For a description of the Debug Module registers, see ICC reference manual.

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4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming.

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■ICP (In-Circuit Programming)

■IAP (In-Application Programming)

■ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM

■Sector 0 size configurable by option byte

■Read-out and write protection against piracy

4.3 PROGRAMMING MODES

The ST7 can be programmed in three different ways:

–Insertion in a programming tool. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased.

–In-Circuit Programming. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased without removing the device from the application board.

–In-Application Programming. In this mode, sector 1 and data EEPROM (if present) can be programmed or erased without removing

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the device from the application board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

–Download ICP Driver code in RAM from the ICCDATA pin

–Execute ICP Driver code in RAM to program the FLASH memory

Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.)

IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

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ST7LITE2

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC interface

ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are:

–RESET: device reset

–VSS: device power supply ground

–ICCCLK: ICC output serial clock pin

–ICCDATA: ICC input serial data pin

–OSC1: main clock input for external source (not required on devices without OSC1/OSC2 pins)

–VDD: application board power supply (optional, see Note 3)

Notes:

1.If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2.During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the appli-

cation reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3.The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4.Pin 9 has to be connected to the OSC1 pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with mul- ti-oscillator capability need to have OSC2 grounded in this case.

5.During reset, this pin must be held at high level to avoid entering ICC mode unexpectedly (this is guaranteed by the internal pull-up if the application leaves the pin floating).

Figure 5. Typical ICC Interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

OPTIONAL

(See Note 3)

APPLICATION CL2

POWER SUPPLY

VDD				OSC2

OPTIONAL

(See Note 4)

CL1

OSC1

ST7

ICC CONNECTOR

HE10 CONNECTOR TYPE

																								APPLICATION BOARD
		9			7		5			3				1
		10			8		6			4				2											APPLICATION
																									RESET SOURCE
																									See Note 2
																								See Notes 1 and 5				APPLICATION
																													I/O
																								See Note 1
							RESET				ICCCLK				ICCDATA

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FLASH PROGRAM MEMORY (Cont’d)

4.5 Memory Protection

There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually.

4.5.1 Read out Protection

Read out protection, when selected, makes it impossible to extract the memory content from the microcontroller, thus preventing piracy. Both program and data E2 memory are protected.

In flash devices, this protection is removed by reprogramming the option. In this case, both program and data E2 memory are automatically erased and the device can be reprogrammed.

Read-out protection selection depends on the device type:

–In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

–In ROM devices it is enabled by mask option specified in the Option List.

4.5.2 Flash Write/Erase Protection

Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to E2 data. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content.

Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable.

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Write/erase protection is enabled through the FMP_W bit in the option byte.

4.6 Related Documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.

4.7 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h)

2nd RASS Key: 1010 1110 (AEh)

7					0
0	0	0	0	0	OPT	LAT	PGM

Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations.

When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

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ST7LITE2

5 DATA EEPROM

5.1 INTRODUCTION

The Electrically Erasable Programmable Read Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter.

5.2 MAIN FEATURES

■Up to 32 Bytes programmed in the same cycle

■EEPROM mono-voltage (charge pump)

■Chained erase and programming cycles

■Internal control of the global programming cycle duration

■WAIT mode management

■Readout protection against piracy

Figure 6. EEPROM Block Diagram

							HIGH VOLTAGE
								PUMP
EECSR	0	0	0	0	0	0	E2LAT E2PGM
			ADDRESS		4		EEPROM
						ROW
			DECODER				MEMORY MATRIX
						DECODER
							(1 ROW = 32 x 8 BITS)
							128	128
						4	DATA	32 x 8 BITS
							MULTIPLEXER	DATA LATCHES
						4
		ADDRESS BUS					DATA BUS

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DATA EEPROM (Cont’d)

5.3 MEMORY ACCESS

The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these different memory access modes.

Read Operation (E2LAT=0)

The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared. In a read cycle, the byte to be accessed is put on the data bus in less than 1 CPU clock cycle. This means that reading data from EEPROM takes the same time as reading data from EPROM, but this memory cannot be used to execute machine code.

Write Operation (E2LAT=1)

To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs,

Figure 7. Data EEPROM Programming Flowchart

the value is latched inside the 32 data latches according to its address.

When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change.

At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.

Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit.

It is not possible to read the latched data. This note is ilustrated by the Figure 9.

	READ MODE		WRITE MODE
	E2LAT=0		E2LAT=1
	E2PGM=0		E2PGM=0
	READ BYTES	WRITE UP TO 32 BYTES
		IN EEPROM AREA
	IN EEPROM AREA
		(with the same 11 MSB of the address)
		START PROGRAMMING CYCLE
			E2LAT=1
		E2PGM=1 (set by software)
		0	1
			E2LAT

CLEARED BY HARDWARE

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DATA EEPROM (Cont’d)

Figure 8. Data E2PROM Write Operation

ß Row / Byte Þ		0	1	2	3	...	30 31	Physical Address
ROW	0							00h...1Fh
DEFINITION	1							20h...3Fh
	...
	N							Nx20h...Nx20h+1Fh
	Read operation impossible							Read operation possible
Byte 1	Byte 2	Byte 32				Programming cycle
	PHASE 1					PHASE 2
	Writing data latches			Waiting E2PGM and E2LAT to fall
E2LAT bit
Set by USER application								Cleared by hardware
E2PGM bit

Note: If a programming cycle is interrupted (by software or a reset action), the integrity of the data in memory is not guaranteed.

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DATA EEPROM (Cont’d)

5.4 POWER SAVING MODES Wait mode

The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-HALT mode.The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode.

Active-Halt mode

Refer to Wait mode.

Halt mode

The DATA EEPROM immediately enters HALT mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted.

5.5 ACCESS ERROR HANDLING

If a read access occurs while E2LAT=1, then the data bus will not be driven.

If a write access occurs while E2LAT=0, then the data on the bus will not be latched.

If a programming cycle is interrupted (by software/ RESET action), the memory data will not be guaranteed.

5.6 Data EEPROM Read-out Protection

The read-out protection is enabled through an option bit (see section 15.1 on page 123).

When this option is selected, the programs and data stored in the EEPROM memory are protected against read-out piracy (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the Option Byte, the entire Program memeory and EEPROM is first automatically erased.

Note: Both Program Memory and data EEPROM are protected using the same option bit.

Figure 9. Data EEPROM Programming Cycle

READ OPERATION NOT POSSIBLE		READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE	WRITE CYCLE
WRITE OF
DATA LATCHES	tPROG
		LAT
		PGM

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ST7LITE2

DATA EEPROM (Cont’d)

5.7 REGISTER DESCRIPTION

EEPROM CONTROL/STATUS REGISTER (EEC-

SR)

Read/Write

Reset Value: 0000 0000 (00h)

7					0
0	0	0	0	0	0	E2LAT	E2PGM

Bits 7:2 = Reserved, forced by hardware to 0.

Bit 1 = E2LAT Latch Access Transfer

This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared.

0:Read mode

1:Write mode

Bit 0 = E2PGM Programming control and status

This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware.

0:Programming finished or not yet started

1:Programming cycle is in progress

Note: if the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed

Table 3. DATA EEPROM Register Map and Reset Values

	Address	Register	7	6	5	4	3	2	1	0
	(Hex.)	Label
	0030h	EECSR							E2LAT	E2PGM
		Reset Value	0	0	0	0	0	0	0	0

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ST7LITE2

6 CENTRAL PROCESSING UNIT

6.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

6.2 MAIN FEATURES

■63 basic instructions

■Fast 8-bit by 8-bit multiply

■17 main addressing modes

■Two 8-bit index registers

■16-bit stack pointer

■Low power modes

■Maskable hardware interrupts

■Non-maskable software interrupt

6.3 CPU REGISTERS

The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions.

Figure 10. CPU Registers

Index Registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

										7										0
																							ACCUMULATOR
												RESET VALUE = XXh
										7										0
																							X INDEX REGISTER
											RESET VALUE = XXh
										7										0
																							Y INDEX REGISTER
											RESET VALUE = XXh
					PCH			8			7				PCL					0			PROGRAM COUNTER
	15
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
										7										0
												1	1	1	H	I	N		Z	C			CONDITION CODE REGISTER
				RESET VALUE = 1									1	1	X	1	X		X	X
		15						8												0			STACK POINTER
											7
RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

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CPU REGISTERS (Cont’d)

CONDITION CODE REGISTER (CC)

Read/Write

Reset Value: 111x1xxx

7							0
1	1	1	H	I	N	Z	C

The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.

0:No half carry has occurred.

1:A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 3 = I Interrupt mask.

This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.

0:Interrupts are enabled.

1:Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable

because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.

0:The result of the last operation is positive or null.

1:The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0:The result of the last operation is different from zero.

1:The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0:No overflow or underflow has occurred.

1:An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

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CPU REGISTERS (Cont’d)

STACK POINTER (SP)

Read/Write

Reset Value: 01FFh

15							8
0	0	0	0	0	0	0	1
7							0
1	SP6	SP5	SP4	SP3	SP2	SP1	SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11).

Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11.

–When an interrupt is received, the SP is decremented and the context is pushed on the stack.

–On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

Figure 11. Stack Manipulation Example

CALL

Interrupt

PUSH Y

POP Y

IRET

RET

Subroutine

Event

or RSP

@ 0180h

SP

SP

SP

Y

CC

CC

CC

A

A

A

X

X

X

SP

PCH

PCH

PCH

SP

PCL

PCL

PCL

PCH

PCH

PCH

PCH

PCH

SP

@ 01FFh PCL

PCL

PCL

PCL

PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0180h

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ST7LITE2

7 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components.

Main features

■Clock Management

–1 MHz internal RC oscillator (enabled by option byte, available on ST7LITE25 and ST7LITE29 devices only)

–1 to 16 MHz or 32kHz External crystal/ceramic resonator (selected by option byte)

–External Clock Input (enabled by option byte)

–PLL for multiplying the frequency by 8 or 4 (enabled by option byte)

–For clock ART counter only: PLL32 for multiplying the 8 MHz frequency by 4 (enabled by option byte). The 8 MHz input frequency is mandatory and can be obtained in the following ways:

–1 MHz RC + PLLx8

–16 MHz external clock (internally divided by 2)

–2 MHz. external clock (internally divided by 2) + PLLx8

–Crystal oscillator with 16 MHz output frequency (internally divided by 2)

■Reset Sequence Manager (RSM)

■System Integrity Management (SI)

–Main supply Low voltage detection (LVD) with reset generation (enabled by option byte)

–Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply (enabled by option byte)

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT

The device contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5V-5.5V). It must be calibrated to obtain the frequency required in the application. This is done by software writing a calibration value in the RCCR (RC Control Register).

Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in EEPROM for 3 and 5V VDD supply voltages at 25°C, as shown in the following table.

	RCCR	Conditions	ST7LITE29	ST7LITE25
			Address	Address
	RCCR0	VDD=5V	1000h	FFDEh
		TA=25°C	and FFDEh
		fRC=1MHz
	RCCR1	VDD=3V	1001h	FFDFh
		TA=25°C	and FFDFh
		fRC=700KHz

Note:

–See “ELECTRICAL CHARACTERISTICS” on page 91. for more information on the frequency and accuracy of the RC oscillator.

–To improve clock stability, it is recommended to

place a decoupling capacitor between the VDD and VSS pins.

–These two bytes are systematically programmed by ST, including on FASTROM devices. Consequently, customers intending to use FASTROM service must not use these two bytes.

–RCCR0 and RCCR1 calibration values will be erased if the read-out protection bit is reset after it has been set. See “Read out Protection” on page 14.

Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated.

Refer to application note AN1324 for information on how to calibrate the RC frequency using an external reference signal.

7.2 PHASE LOCKED LOOP

The PLL can be used to multiply a 1MHz frequency from the RC oscillator or the external clock by 4

or 8 to obtain fOSC of 4 or 8 MHz. The PLL is enabled and the multiplication factor of 4 or 8 is select-

ed by 2 option bits.

–The x4 PLL is intended for operation with VDD in the 2.4V to 3.3V range

–The x8 PLL is intended for operation with VDD in the 3.3V to 5.5V range

Refer to Section 15.1 for the option byte description.

If the PLL is disabled and the RC oscillator is enabled, then fOSC = 1MHz.

If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock.

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PHASE LOCKED LOOP (Cont’d)

Figure 12. PLL Output Frequency Timing

Diagram

		LOCKED bit set
4/8 x
input
freq.
		tSTAB
freq.		tLOCK
Output	tSTARTUP
		t

When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs the clock after a delay of tSTARTUP.

When the PLL output signal reaches the operating frequency, the LOCKED bit in the SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after

a stabilization time of tSTAB (see Figure 12 and 13.3.4 Internal RC Oscillator and PLL)

Refer to section 7.6.4 on page 33 for a description of the LOCKED bit in the SICSR register.

7.3 REGISTER DESCRIPTION

MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR)

Read / Write

Reset Value: 0000 0000 (00h)

7					0
0	0	0	0	0	0	MCO	SMS

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = MCO Main Clock Out enable

This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock.

0:MCO clock disabled, I/O port free for general purpose I/O.

1:MCO clock enabled.

Bit 0 = SMS Slow Mode select

This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock fOSC or fOSC/32.

0:Normal mode (fCPU = fOSC

1:Slow mode (fCPU = fOSC/32)

RC CONTROL REGISTER (RCCR)

Read / Write

Reset Value: 1111 1111 (FFh)

7

0

CR70 CR60 CR50 CR40 CR30 CR20 CR10 CR0

Bits 7:0 = CR[7:0] RC Oscillator Frequency Adjustment Bits

These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The application can store the correct value for each voltage range in EEPROM and write it to this register at start-up.

00h = maximum available frequency FFh = lowest available frequency

Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.

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Figure 13. Clock Management Block Diagram

	CR7	CR6 CR5 CR4	CR3	CR2	CR1	CR0	RCCR
		Tunable				fCPU		PLL	12-BIT
							8MHz -> 32MHz
		1% RC Oscillator							AT TIMER 2
		OSC,PLLOFF,							RC OSC
	OSCRANGE[2:0]
		Option bits							PLLx4x8
CLKIN		CLKIN					PLL 1MHz -> 8MHz
									fOSC
		CLKIN					PLL 1MHz -> 4MHz
				/2			CLKIN/2
				DIVIDER					CLKIN/2
CLKIN	OSC			OSC	/2				OSC/2
/OSC1
	1-16 MHZ
OSC2					DIVIDER
	or 32kHz
									OSC,PLLOFF,
									OSCRANGE[2:0]
									Option bits
						8-BIT		fLTIMER
				LITE TIMER 2 COUNTER				(1ms timebase @ 8 MHz fOSC)
	fOSC	/32 DIVIDER		fOSC/32
						1			fCPU
				fOSC		0			TO CPU AND
									PERIPHERALS
					MCO SMS		MCCSR
									fCPU	MCO

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7.4 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by four different source types coming from the multioscillator block (1 to 16MHz or 32kHz):

■an external source

■5 crystal or ceramic resonator oscillators

■an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 4. Refer to the electrical characteristics section for more details.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Note: when the Multi-Oscillator is not used, PB4 is selected by default as external clock.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 15.1 on page 123 for more details on the frequency ranges). In this mode of the multi-oscil- lator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

In this mode, the tunable 1%RC oscillator is used as main clock source. The two oscillator pins have to be tied to ground.

Table 4. ST7 Clock Sources

	Hardware Configuration
External Clock	ST7
	OSC1	OSC2
	EXTERNAL
	SOURCE
Resonators	ST7
	OSC1	OSC2
Crystal/Ceramic	CL1	CL2
	LOAD
	CAPACITORS
Internal RC Oscillator	ST7
	OSC1	OSC2

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7.5 RESET SEQUENCE MANAGER (RSM)

7.5.1 Introduction

The reset sequence manager includes three RESET sources as shown in Figure 15:

■External RESET source pulse

■Internal LVD RESET (Low Voltage Detection)

■Internal WATCHDOG RESET

The RESET vector fetch phase duration is 2 clock cycles.

If the PLL is enabled by option byte, it outputs the

clock after an additional delay of tSTARTUP (see Figure 12).

Figure 14. RESET Sequence Phases

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases as shown in Figure 14:

■Active Phase depending on the RESET source

■256 or 4096 CPU clock cycle delay (see table below)

■RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte:

	Clock Source	CPU clock
		cycle delay
	Internal RC Oscillator	256
	External clock (connected to CLKIN pin)	256
	External Crystal/Ceramic Oscillator	4096
	(connected to OSC1/OSC2 pins)

RESET

	Active Phase	INTERNAL RESET	FETCH
		256 or 4096 CLOCK CYCLES	VECTOR

7.5.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A RESET signal originating from an external

source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 16). This de-

tection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

Figure 15. Reset Block Diagram

VDD

RON

Filter

INTERNAL

RESET

RESET

PULSE

WATCHDOG RESET

GENERATOR

LVD RESET

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RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

7.5.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency.

A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin.

7.5.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■Power-On RESET

■Voltage Drop RESET

The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or VDD<VIT- (falling edge) as shown in Figure 16.

The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.

7.5.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 16.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.

Figure 16. RESET Sequences

VDD

VIT+(LVD)

VIT-(LVD)

	LVD
	RESET
RUN	RUN
	ACTIVE PHASE

EXTERNAL	WATCHDOG
RESET	RESET
RUN	RUN
ACTIVE	ACTIVE
PHASE	PHASE

th(RSTL)in							tw(RSTL)out

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

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7.6 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

7.6.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is

below a VIT-(LVD) reference value. This means that it secures the power-up as well as the power-down

keeping the ST7 in reset.

The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value for poweron in order to avoid a parasitic reset when the

MCU starts running and sinks current on the supply (hysteresis).

The voltage threshold can be configured by option byte to be low, medium or high.

Provided the minimum VDD value (guaranteed for

the oscillator frequency) is above VIT-(LVD), the MCU can only be in two modes:

–under full software control

–in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

The LVD Reset circuitry generates a reset when VDD is below:

–VIT+(LVD)when VDD is rising

–VIT-(LVD) when VDD is falling

The LVD function is illustrated in Figure 17.

Notes:

The LVD allows the device to be used without any external RESET circuitry.

The LVD is an optional function which can be selected by option byte.

Figure 17. Low Voltage Detector vs Reset

VDD

Vhys

VIT+(LVD)

VIT-(LVD)

RESET

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Figure 18. Reset and Supply Management Block Diagram

		WATCHDOG			STATUS FLAG
		TIMER (WDG)
			SYSTEM INTEGRITY MANAGEMENT
	RESET SEQUENCE				AVD Interrupt Request
RESET	MANAGER	SICSR
	(RSM)	0	0	0	WDGRF LOCKED LVDRFAVDF AVDIE
					LOW VOLTAGE
VSS					DETECTOR
VDD					(LVD)
					AUXILIARY VOLTAGE
					DETECTOR
					(AVD)

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