SGS Thomson Microelectronics ST63T87B1, ST63T85B1, ST63E87D1, ST6367B1, ST6367B Datasheet

ST6365,ST6375,ST6385 R ST6367,ST6377,ST6387

8-BIT MCUs WITH

ON-SCREEN-DISPLAY FOR TV TUNING

■4.5 to 6V supply operating range

■8MHz Maximum Clock Frequency

■User Program ROM: up to 20140 bytes

■Reserved Test ROM: up to 340 bytes

■Data ROM: user selectable size

■Data RAM: 256 bytes

■Data EEPROM: 384 bytes

■42-Pin Shrink Dual in Line Plastic Package

■Up to 22 software programmable general purpose Inputs/Outputs, including 2 direct LED driving Outputs

■Two Timers each including an 8-bit counter with a 7-bit programmable prescaler

■Digital Watchdog Function

■Serial Peripheral Interface (SPI) supporting S- BUS/ I 2 C BUS and standard serial protocols

■SPI for external frequency synthesis tuning

■14 bit counter for voltage synthesis tuning

■Up to Six 6-Bit PWM D/A Converters

■AFC A/D converter with 0.5V resolution

■Five interrupt vectors (IRIN/NMI, Timer 1 & 2, VSYNC, PWR INT.)

■On-chip clock oscillator

■5 Lines by 15 Characters On-Screen Display Generator with 128 Characters

■All ROM types are supported by pin-to-pin EPROM and OTP versions.

■The development tool of the ST6365, ST6375, ST6385, ST6367, ST6377, ST6387 microcontrollers consists of the ST638X-EMU2 emulation and development system to be connected via a standard RS232 serial line to an MS-DOS Personal Computer.

PSDIP42

(Refer to end of Document for Ordering Information)

DEVICE SUMMARY

	DEVICE	ROM	D/A Converter
		(Bytes)
	ST6365	8K	4
	ST6367	8K	6
	ST6375	14K	4
	ST6377	14K	6
	ST6385	20K	4
	ST6387	20K	6

Rev. 2.2

December 1997

1/84

This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.

Table of Contents

ST6365, ST6375, ST6385, ST6367, ST6377, ST6387 . . . . . . . .			1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			5
1.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
1.2	PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
1.3	MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
	1.3.1	Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	1.3.2	Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	1.3.3	Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	1.3.4 Data RAM/EEPROM/OSD RAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			16
2.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
2.2	CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . .			18
3.1	ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
3.2	RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	3.2.1	RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	1 9
	3.2.2	Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	3.2.3	Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	3.2.4	Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	3.2.5	MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
3.3	HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . . .		21
3.4	INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
	3.4.1	Interrupt Vectors/Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	3.4.2	Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	3.4.3	Interrupt Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	3.4.4	Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	3.4.5	ST638x Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
3.5	POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26

3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.3 Exit from WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.1 Details of I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.2 I/O Pin Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1.3 Input/Output Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1.4 I/O Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.2 Timer Status Control Registers (TSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.3 Timer Counter Registers (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.4 Timer Prescaler Registers (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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Table of Contents

4.3 SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

34

4.3.1 S-BUS/I2C BUS Protocol Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.2 S-BUS/I2C BUS Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.3 Compatibility S-BUS/I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.3.4 STD SPI Protocol (Shift Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.3.5 SPI Data/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.4 14-BIT VOLTAGE SYNTHESIS TUNING PERIPHERAL . . . . . . . . . . . . . . . . . . . . . . . . . . 43

	4.4.1	Output Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
	4.4.2	VS Tuning Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
4.5	6-BIT PWM D/A CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		44
4.6	AFC A/D COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		45
	4.6.1	A/D Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
4.7	DEDICATED LATCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		46
4.8	ON-SCREEN DISPLAY (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		47
	4.8.1	Format Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			57

5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

67

7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3 CUSTOMER EEPROM INITIAL CONTENTS: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.4 OSD TEST CHARACTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.5 ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

ST63E85, T85, ST63E87, T87 . . . . . . . . . . . . . . . . . . . . . . . . . . 71

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

72

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.3 EPROM/OTP DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.4 POWER ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.5 EPROM ERASING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

2.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

81

3.1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.2 CUSTOMER EEPROM INITIAL CONTENTS: FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.3 OSD TEST CHARACTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.4 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.5 ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST6365,67,75,77,85,87 microcontrollers are members of the 8-bit HCMOS ST638x family, a series of devices specially oriented to TV applications. Different ROM size and peripheral configurations are available to give the maximum application and cost flexibility. All ST638x members are based on a building block approach: a common core is surrounded by a combination of on-chip peripherals (macrocells) available from a standard library. These peripherals are designed with the same Core technology providing full compatibility and short design time. Many of these macrocells are specially dedicated to TV applications. The macrocells of the ST638x family are: two Timer peripherals each including an 8-bit counter with a

Table 1. Device Summary

7-bit software programmable prescaler (Timer), a digital hardware activated watchdog function (DHWD), a 14-bit voltage synthesis tuning peripheral, a Serial Peripheral Interface (SPI), up to six 6-bit PWM D/A converters, an AFC A/D converter with 0.5V resolution, an on-screen display (OSD) with 15 characters per line and 128 characters (in two banks each of 64 characters). In addition the following memory resources are available: program ROM (up to 20K), data RAM (256 bytes), EEPROM (384 bytes). Refer to pin configurations figures and to ST638x device summary (Table 1) for the definition of ST638x family members and a summary of differences among the different types.

	Device	ROM	RAM	EEPROM	AFC	VS	D/A	Colour	EPROM Devices
		(Bytes)	(Bytes)	(Bytes)				Pins
	ST6365	8K	256	384	Yes	Yes	4	3	ST63E85
	ST6367	8K	256	384	Yes	Yes	6	3	ST63E87
	ST6375	14K	256	384	Yes	Yes	4	3	ST63E85
	ST6377	14K	256	384	Yes	Yes	6	3	ST63E87
	ST6385	20K	256	384	Yes	Yes	4	3	ST63E85
	ST6387	20K	256	384	Yes	Yes	6	3	ST63E87

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Figure 1. Block Diagram

TEST

IRIN/PC6

PA0 - PA7*

PORT A

TEST

PB0 - PB2, PB4 PB6*

PORT B

INTERRUPT

Inputs

PORT C

PC2, PC4 - PC7*

PC0/SCL

PC1/SDA

DATA ROM

PC3/SEN

USER

Serial Peripheral

USER PROGRAM

SELECTABLE

Interface

MEMORY

DATA RAM

UP TO 20KBytes

256 Bytes

TIMER 1

DATA EEPROM

TIMER 2

384 Bytes

Digital

PC

Watchdog Timer

STACK LEVEL 1

D/A Outputs

DA0 - DA5

STACK LEVEL 2

STACK LEVEL 3

8 BIT CORE

VS Output &

AFC & VS*

STACK LEVEL 4

AFC Outputs

STACK LEVEL 5

On-Screen

R, G, B, BLANK

STACK LEVEL 6

Display

HSYNC, VSYNC

POWER

OSCILLATOR

RESET

SUPPLY

VDD VSS OSCin OSCout	RESET	OSDOSCout OSDOSCin
		*Refer to Pin Description for Additional Information	VR01753

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1.2 PIN DESCRIPTION

VDD and VSS. Power is supplied to the MCU using these two pins. VDD is power and VSS is the ground connection.

OSCin, OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the correct operation of the MCU with various stability/ cost trade-offs. The OSCin pin is the input pin, the OSCout pin is the output pin.

RESET. The active low RESET pin is used to start the microcontroller to the beginning of its program. Additionally the quartz crystal oscillator will be disabled when the RESET pin is low to reduce power consumption during reset phase.

TEST. The TEST pin must be held at VSS for normal operation.

PA0-PA7. These 8 lines are organized as one I/O port (A). Each line may be configured as either an input with or without pull-up resistor or as an output under software control of the data direction register. Pins PA4 to PA7 are configured as opendrain outputs (12V drive). On PA4-PA7 pins the input pull-up option is not available while PA6 and PA7 have additional current driving capability (25mA, VOL:1V). PA0 to PA3 pins are configured as push-pull.

PB0-PB2, PB4-PB6. These 6 lines are organized as one I/O port (B). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register.

PC0-PC7. These 8 lines are organized as one I/O port (C). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register. Pins PC0 to PC3 are configured as open-drain (5V drive) in output mode while PC4 to PC7 are open-drain with 12V drive and the input pull-up options does not exist on these four pins. PC0, PC1 and PC3 lines when in output mode are “ANDed” with the SPI control signals and are all open-drain. PC0 is connected to the SPI clock signal (SCL), PC1 with the SPI data signal (SDA) while PC3 is connected with SPI enable signal (SEN, used in S-BUS protocol). Pin PC4 and PC6 can also be inputs to software programmable edge sensitive latches which can generate interrupts; PC4 can be connected to Power Interrupt while PC6 can be connected to the IRIN/NMI interrupt line.

DA0-DA5. These pins are the six PWM D/A outputs of the 6-bit on-chip D/A converters. These lines have open-drain outputs with 12V drive. The output repetition rate is 31.25KHz (with 8MHz clock).

AFC. This is the input of the on-chip 10 levels comparator that can be used to implement the AFC function. This pin is an high impedance input able to withstand signals with a peak amplitude up to 12V.

OSDOSCin, OSDOSCout. These are the On Screen Display oscillator terminals. An oscillation capacitor and coil network have to be connected to provide the right signal to the OSD.

HSYNC, VSYNC. These are the horizontal and vertical synchronization pins. The active polarity of these pins to the OSD macrocell can be selected by the user as ROM mask option. If the device is specified to have negative logic inputs, then these signals are low the OSD oscillator stops. If the device is specified to have positive logic inputs, then when these signals are high the OSD oscillator stops. VSYNC is also connected to the VSYNC interrupt.

R, G, B, BLANK. Outputs from the OSD. R, G and B are the color outputs while BLANK is the blanking output. All outputs are push-pull. The active polarity of these pins can be selected by the user as ROM mask option.

VS. This is the output pin of the on-chip 14-bit voltage synthesis tuning cell (VS). The tuning signal present at this pin gives an approximate resolution of 40KHz per step over the UHF band. This line is a push-pull output with standard drive.

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Figure 2. ST6365, 75, 85 Pin configuration

Figure 3. ST6367, 77, 87 Pin configuration

VDD

VDD

VS

1

42

DA0

1

42

DA1

2

41

PC0/SCL

DA1

2

41

PC0/SCL

DA2

3

40

PC1/SDA

DA2

3

40

PC1/SDA

DA3

4

39

PC2

DA3

4

39

PC2

DA4

5

38

PC3/SEN

DA4

5

38

PC3/SEN

PB0

6

37

PC4/PWRIN

DA5

6

37

PC4/PWRIN

PB1

7

36

PC5

PB1

7

36

PC5

PB2

8

35

PC6/IRIN

PB2

8

35

PC6/IRIN

AFC

9

34

PC7

AFC

9

34

VS

PB4

10

33

PB4

10

33

RESET

RESET

PB5

11

32

OSCout

PB5

11

32

OSCout

PB6

12

31

OSCin

PB6

12

31

OSCin

30

(1)

30

(1)

PA0

13

TEST/VPP

PA0

13

TEST/VPP

PA1

14

29

OSDOSCin

PA1

14

29

OSDOSCin

PA2

15

28

OSDOSCout

PA2

15

28

OSDOSCout

PA3

16

27

PA3

16

27

VSYNC

VSYNC

PA4

17

26

PA4

17

26

HSYNC

HSYNC

PA5

18

25

BLANK

PA5

18

25

BLANK

PA6 (HD0)

19

24

B

PA6 (HD0)

19

24

B

PA7 (HD1)

20

23

G

PA7 (HD1)

20

23

G

VSS

21

22

R

VSS

21

22

R

(1) This pin is also the VPP input for OTP/EPROM devices

(1) This pin is also the VPP input for OTP/EPROM devices

VR01375

VR01375E

Table 2. Pin Summary

Pin Function

Description

DA0 to DA5

Output, OpenDrain, 12V

AFC

Input, High Impedance, 12V

VS

Output, PushPull

R, G, B, BLANK

Output, PushPull

HSYNC, VSYNC

Input, Pullup, Schmitt Trigger

OSDOSCin

Input, High Impedance

OSDOSCout

Output, PushPull

TEST

Input, PullDown

OSCin

Input, Resistive Bias, Schmitt Trigger to Reset Logic Only

OSCout

Output, PushPull

RESET

Input, Pullup, Schmitt Trigger Input

PA0PA3

I/ O, PushPull, Software Input Pullup, Schmitt Trigger Input

PA4PA5

I/ O, OpenDrain, 12V, No Input Pullup, Schmitt Trigger Input

PA6PA7

I/ O, OpenDrain, 12V, No Input Pullup, Schmitt Trigger Input, High Drive

PB0PB2

I/ O, PushPull, Software Input Pullup, Schmitt Trigger Input

PB4PB6

I/ O, PushPull, Software Input Pullup, Schmitt Trigger Input

PC0PC3

I/ O, OpenDrain, 5V, Software Input Pullup, Schmitt Trigger Input

PC4PC7

I/ O, OpenDrain, 12V, No Input Pullup, Schmitt Trigger Input

VDD, VSS

Power Supply Pins

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

1.3 MEMORY SPACES

The MCU operates in three different memory spaces: Stack Space, Program Space and Data Space.

1.3.1 Stack Space

The stack space consists of six 12 bit registers that are used for stacking subroutine and interrupt return addresses plus the current program counter register.

1.3.2 Program Space

The program space is physically implemented in the ROM and includes all the instructions that are to be executed, as well as the data required for the immediate addressing mode instructions, the reserved test area and the user vectors. It is addressed thanks to the 12-bit Program Counter register (PC register) and the ST6 Core can directly address up to 4K bytes of Program Space. Nevertheless, the Program Space can be extended by the addition of 2Kbyte memory banks as it is shown in Figure 4, in which the 20K bytes memory is described. These banks are addressed by pointing to the 000h-7FFh locations of the Program Space thanks to the Program Counter, and by writing the appropriate code in the Program ROM Page Register (PRPR) located at address CAh in the Data Space. Because interrupts and common subroutines should be available all the time only the lower 2K byte of the 4K program space are bank switched while the upper 2K byte can be

Figure 5. Memory Addressing Diagram

seen as static space. Table 3 gives the different codes that allows the selection of the corresponding banks. Note that, from the memory point of view, the Page 1 and the Static Page represent the same physical memory: it is only a different way of addressing the same location. On the ST6385 and ST6387, a total of 20480 bytes of ROM have been implemented; 20140 bytes are available as User ROM while 340 bytes are reserved for testing.

Figure 4. 20K-Byte Program Space Addressing

Program counter space

0000h

4FFFh

0FFFh

Page 1

Static

Page

0800h

07FFh

Page 0	Page 1	...	Page 9
	Static Page

0000h

STACK SPACE

PROGRAM SPACE

DATA SPACE

PROGRAM COUNTER

STACK LEVEL 1

STACK LEVEL 2

STACK LEVEL 3

STACK LEVEL 4

STACK LEVEL 5

STACK LEVEL 6

0000h	000h

			RAM / EEPROM
	ROM		BANKING AREA
	0-63	03Fh
		040h
			DATA ROM
	07FFh		WINDOW
		07Fh
	0800h
		080h	X REGISTER
		081h	Y REGISTER
		082h	V REGISTER
	ROM	083h	W REGISTER
		084h
		0C0h	RAM
	0FF0h		DATA ROM
			WINDOW SELECT
	INTERRUPT &		DATA RAM
			BANK SELECT
	RESET VECTORS
	0FFFh	0FFh	ACCUMULATOR

vr01568

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

MEMORY SPACES (Cont’d)

Program ROM Page Register (PRPR)

Address: CAh - Write only Reset Value: XXh

7			0
-	-	-	-	PRPR3	PRPR2	PRPR1	PRPR0

D7-D4. These bits are not used but have to be written to “0”.

PRPR3-PRPR0. These are the program ROM banking bits and the value loaded selects the corresponding page to be addressed in the lower part of 4K program address space as specified in Table 3. This register is undefined on reset.

Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used.

Note. Only the lower part of address space has been bankswitched because interrupt vectors and common subroutines should be available all the time. The reason of this structure is due to the fact that it is not possible to jump from a dynamic page to another, unless jumping back to the static page, changing contents of PRPR and then jumping to a different dynamic page.

Care is required when handling the PRPR as it is write only. For this reason, it is not allowed to change the PRPR contents while executing interrupts drivers, as the driver cannot save and than

Table 4. Program Memory Map

restore its previous content. Anyway, this operation may be necessary if the sum of common routines and interrupt drivers will take more than 2K bytes; in this case it could be necessary to divide the interrupt driver in a (minor) part in the static page (start and end), and in the second (major) part in one dynamic page. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location. Each time the program writes the PRPR register, the image register should also be written. The image register must be written first, so if an interrupt occurs between the two instructions the PRPR is not affected.

Table 3. Program Memory Page Register coding

	PRPR3	PRPR2	PRPR1	PRPR0	PC11	Memory Page
	X	X	X	X	1	Static Page
						(Page 1)
	0	0	0	0	0	Page 0
	0	0	0	1	0	Page 1 (Static
						Page)
	0	0	1	0	0	Page 2
	0	0	1	1	0	Page 3
	0	1	0	0	0	Page 4
	0	1	0	1	0	Page 5
	0	1	1	0	0	Page 6
	0	1	1	1	0	Page 7
	1	0	0	0	0	Page 8
	1	0	0	1	0	Page 9

	Program Memory Page	Device Address	Description
	PAGE 0	0000h-007Fh	Reserved
		0080h-07FFh	User ROM
		0800h-0F9Fh	User ROM
		0FA0h-0FEFh	Reserved
	PAGE 1	0FF0h-0FF7h	Interrupt Vectors
	“STATIC”	0FF8h-0FFBh	Reserved
		0FFCh-0FFDh	NMI Vector
		0FFEh-0FFFh	Reset Vector
	PAGE 2	0000h-000Fh	Reserved
		0010h-07FFh	User ROM
	PAGE 3	0000h-000Fh	Reserved
		0010h-07FFh	User ROM (End of 8K ST6365, 67)
	PAGE 4	0000h-000Fh	Reserved
		0010h-07FFh	User ROM
	PAGE 5	0000h-000Fh	Reserved
		0010h-07FFh	User ROM
	PAGE 6	0000h-000Fh	Reserved
		0010h-07FFh	User ROM (End of 14K ST6375, 77)
	PAGE 7	0000h-000Fh	Reserved
		0010h-07FFh	User ROM
	PAGE 8	0000h-000Fh	Reserved
		0010h-07FFh	User ROM
	PAGE 9	0000h-000Fh	Reserved
		0010h-07FFh	User ROM (End of 20K ST6385, 87)

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

MEMORY SPACES (Cont’d)

1.3.3 Data Space

The ST6 Core instruction set operates on a specific space, referred to as the Data Space, which contains all the data necessary for the program.

Figure 6. Data Space

	DATA RAM/EEPROM/OSD	000h
	BANK AREA	03Fh
	DATA ROM	040h
	WINDOW AREA	07Fh
	X REGISTER	080h
	Y REGISTER	081h
	V REGISTER	082h
	W REGISTER	083h
	DATA RAM	084h
		0BFh
	PORT A DATA REGISTER	0C0h
	PORT B DATA REGISTER	0C1h
	PORT C DATA REGISTER	0C2h
	RESERVED	0C3h
	PORT A DIRECTION REGISTER	0C4h
	PORT B DIRECTION REGISTER	0C5h
	PORT C DIRECTION REGISTER	0C6h
	RESERVED	0C7h
	INTERRUPT OPTION REGISTER	0C8h
	DATA ROM WINDOW REGISTER	0C9h
	PROGRAM ROM PAGE REGISTER	0CAh
	RESERVED	0CBh
	SPI DATA REGISTER	0CCh
	RESERVED	0CDh
		0D1h
	TIMER 1 PRESCALER REGISTER	0D2h
	TIMER 1 COUNTER REGISTER	0D3h
	TIMER 1 STATUS/CONTROL REGISTER	0D4h
	RESERVED	0D5h
		0D7h
	WATCHDOG REGISTER	0D8h

The Data Space allows the addressing of RAM (256 bytes), EEPROM (384 bytes), ST6 Core and peripheral registers, as well as read-only data such as constants and look-up tables.

	RESERVED	0D9h
	TIMER 2 PRESCALER REGISTER	0DAh
	TIMER 2 COUNTER REGISTER	0DBh
	TIMER 2 STATUS/CONTROL REGISTER	0DCh
	RESERVED	0DDh
		0DFh
	DA 0 DATA/CONTROL REGISTER	0E0h
	DA 1 DATA/CONTROL REGISTER	0E1h
	DA 2 DATA/CONTROL REGISTER	0E2h
	DA 3 DATA/CONTROL REGISTER	0E3h
	AFC, IR & OSD RESULT REGISTER	0E5h
	OUTPUT CONTROL REGISTER 1	0E6h
	DA 4 DATA/CONTROL REGISTER	0E7h
	DA 5 DATA/CONTROL REGISTER	0E8h
	DEDICATED LATCHES CONTROL REGISTER	0E9h
	EEPROM CONTROL REGISTER	0EAh
	SPI CONTROL REGISTER 1	0EBh
	SPI CONTROL REGISTER 2	0ECh
	OSD CHARACTER BANK SELECT REGISTER	0EDh
	VS DATA REGISTER 1	0EEh
	VS DATA REGISTER 2	0EFh
		0F0h
	RESERVED	0F5h
		0FEh
	ACCUMULATOR	0FFh
	OSD CONTROL REGISTERS LOCATED IN
	PAGE 6 OF BANKED DATA RAM
	VERTICAL START ADDRESS REGISTER	010h
	HORIZONTAL START ADDRESS REGISTER	011h
	VERTICAL SPACE REGISTER	012h
	HORIZONTAL SPACE REGISTER	013h
	BACKGROUND COLOUR REGISTER	014h
	GLOBAL ENABLE REGISTER	017h

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

MEMORY SPACES (Cont’d)

Data ROM Addressing. All the read-only data are physically implemented in the ROM in which the Program Space is also implemented. The ROM therefore contains the program to be executed and also the constants and the look-up tables needed for the program. The locations of Data Space in which the different constants and look-up tables are addressed by the ST6 Core can be considered as being a 64-byte window through which it is possible to access to the read-only data stored in the ROM. This window is located from the 40h address to the 7Fh address in the Data space and allows the direct reading of the bytes from the 000h address to the 03Fh address in the ROM. All the bytes of the ROM can be used to store either instructions or read-only data. Indeed, the window can be moved by step of 64 bytes along the ROM in writing the appropriate code in the Write-only Data ROM Window register (DRWR, location C9h). The effective address of the byte to be read as a data in the ROM is obtained by the concatenation of the 6 less significant bits of the address in the Data Space (as less significant bits) and the content of the DRWR (as most significant bits). So when addressing location 40h of data space, and 0 is loaded in the DRWR, the physical addressed location in ROM is 00h.

Note: The data ROM Window can not address window above the 16K byte range.

Figure 7. Data ROM Window Memory Addressing

Data ROM Window Register (DRWR)

Address: C9h - Write only Reset Value: XXh

7							0
DRWR	DRWR	DRWR	DRWR	DRWR	DRWR	DRWR	DRWR
7	6	5	4	3	2	1	0

DRWR7-DRWR0. These are the Data Rom Window bits that correspond to the upper bits of data ROM program space. This register is undefined after reset.

Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used.

Note: Care is required when handling the DRWR as it is write only. For this reason, it is not allowed to change the DRWR contents while executing interrupts drivers, as the driver cannot save and than restore its previous content. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the DRWR it writes also the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRWR register is not affected.

DATA ROM	13	12	11	10	9	8	7	6	5	4	3	2	1	0	PROGRAM SPACE ADDRESS
															READ
WINDOW REGISTER	7	6	5	4	3	2	1	0
CONTENTS									5	4	3	2	1	0	DATA SPACE ADDRESS
(DWR)
							0	1							40h-7Fh
															IN INSTRUCTION

Example:
DWR=28h	0	0	1	0	1	0	0	0
							0	1	0	1	1	0	0	1	DATA SPACE ADDRESS
															59h

	ROM	0	0	1	0	1	0	0	0	0	1	1	0	0	1
	ADDRESS:A19h

VR01573B

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

MEMORY SPACES (Cont’d)

1.3.4 Data RAM/EEPROM/OSD RAM

Addressing

In all members of the ST638x family 64 bytes of data RAM are directly addressable in the data space from 80h to BFh addresses. The additional 192 bytes of RAM, the 384 bytes of EEPROM, and the OSD RAM can be addressed using the banks of 64 bytes located between addresses 00h and 3Fh. The selection of the bank is done by programming the Data RAM Bank Register (DRBR) located at the E8h address of the Data Space. In this way each bank of RAM, EEPROM or OSD RAM can select 64 bytes at a time. No more than one bank should be set at a time.

Data RAM Bank Register (DRBR)

Address: E8h - Write only

Reset Value: XXh

7							0
DRBR	DRBR	DRBR	DRBR	DRBR	DRBR	DRBR	DRBR
7	6	5	4	3	2	1	0

DRBR7,DRBR1,DRBR0. These bits select the EEPROM pages.

DRBR6, DRBR5. Each of these bits, when set, will select one OSD RAM register page.

DRBR4,DRBR3,DRBR2. Each of these bits, when set, will select oneRAM page.

This register is undefined after reset.

Table 5 summarizes how to set the Data RAM Bank Register in order to select the various banks or pages.

Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used.

Note: Care is required when handling the DRBR as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupts drivers, as the driver cannot save and than restore its previous content. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the DRBR it writes also the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected.

Table 5. Data RAM Bank Register Set-up

DRBR Value		Selection
Hex.	Binary
01h	0000 0001	EEPROM Page 0
02h	0000 0010	EEPROM Page 1
03h	0000 0011	EEPROM Page 2
81h	1000 0001	EEPROM Page 3
82h	1000 0010	EEPROM Page 4
83h	1000 0011	EEPROM Page 5
04h	0000 0100	RAM Page 2
08h	0000 1000	RAM Page 3
10h	0001 0000	RAM Page 4
20h	0010 0000	OSD Page 5
40h	0100 0000	OSD Page 6

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

MEMORY SPACES (Cont’d)

EEPROM Description

The data space of ST638x family from 00h to 3Fh is paged as described in Table 5. 384 bytes of EEPROM located in six pages of 64 bytes (pages 0,1,2,3,4 and 5, see Table 5).

Through the programming of the Data RAM Bank Register (DRBR=E8h) the user can select the bank or page leaving unaffected the way to address the static registers. The way to address the “dynamic” page is to set the DRBR as described in Table 5 (e.g. to select EEPROM page 0, the DRBR has to be loaded with content 01h, see Data RAM/EEPROM/OSD RAM addressing for additional information). Bits 0, 1 and 7 of the DRBR are dedicated to the EEPROM.

The EEPROM pages do not require dedicated instructions to be accessed in reading or writing. The EEPROM is controlled by the EEPROM Control Register (EECR=EAh). Any EEPROM location can be read just like any other data location, also in terms of access time.

To write an EEPROM location takes an average time of 5 ms (10ms max) and during this time the EEPROM is not accessible by the Core. A busy flag can be read by the Core to know the EEPROM status before trying any access. In writing the EEPROM can work in two modes: Byte Mode (BMODE) and Parallel Mode (PMODE). The BMODE is the normal way to use the EEPROM and consists in accessing one byte at a time. The PMODE consists in accessing 8 bytes per time.

EEPROM Control Register (EECR)

Address: EAh - Read only/Write only

Reset Value:

7							0
-	SB	-	-	PS	PE	BS	EN

D7. Not used

Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used.

SB. WRITE ONLY. If this bit is set the EEPROM is disabled (any access will be meaningless) and the

14/84

power consumption of the EEPROM is reduced to the leakage values.

D5, D4. Reserved for testing purposes, they must be set to zero.

PS. WRITE ONLY. Once in Parallel Mode, as soon as the user software sets the PS bit the parallel writing of the 8 adjacent registers will start. PS is internally reset at the end of the programming procedure. Note that less than 8 bytes can be written; after parallel programming the remaining undefined bytes will have no particular content.

PE. WRITE ONLY. This bit must be set by the user program in order to perform parallel programming (more bytes per time). If PE is set and the “parallel start bit” (PS) is low, up to 8 adjacent bytes can be written at the maximum speed, the content being stored in volatile registers. These 8 adjacent bytes can be considered as row, whose A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 are the changing bytes. PE is automatically reset at the end of any parallel programming procedure. PE can be reset by the user software before starting the programming procedure, leaving unchanged the EEPROM registers.

BS. READ ONLY. This bit will be automatically set by the CORE when the user program modifies an EEPROM register. The user program has to test it before any read or write EEPROM operation; any attempt to access the EEPROM while “busy bit” is set will be aborted and the writing procedure in progress completed.

EN. WRITE ONLY. This bit MUST be set to one in order to write any EEPROM register. If the user program will attempt to write the EEPROM when EN= “0” the involved registers will be unaffected and the “busy bit” will not be set.

After RESET the content of EECR register will be 00h.

Notes: When the EEPROM is busy (BS=”1”) the EECR can not be accessed in write mode, it is only possible to read BS status. This implies that as long as the EEPROM is busy it is not possible to change the status of the EEPROM control register. EECR bits 4 and 5 are reserved for test purposes, and must never be set to “1”.

ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

MEMORY SPACES (Cont’d)

Additional Notes on Parallel Mode. If the user wants to perform a parallel programming the first action should be the setting of the PE bit; from this moment, the first time the EEPROM will be addressed in writing, the ROW address will be latched and it will be possible to change it only at the end of the programming procedure or by resetting PE without programming the EEPROM.

After the ROW address latching the Core can “see” just one EEPROM row (the selected one) and any attempt to write or read other rows will produce errors. Do not read the EEPROM while PE is set.

As soon as PE bit is set, the 8 volatile ROW latches are cleared. From this moment the user can load data in the whole ROW or just in a subset. PS setting will modify the EEPROM registers corresponding to the ROW latches accessed after PE.

For example, if the software sets PE and accesses EEPROM in writing at addresses 18h,1Ah,1Bh and then sets PS, these three registers will be modified at the same time; the remaining bytes will have no particular content. Note that PE is internally reset at the end of the programming procedure. This implies that the user must set PE bit between two parallel programming procedures. Anyway the user can set and then reset PE without performing any EEPROM programming. PS is a set only bit and is internally reset at the end of the programming procedure. Note that if the user tries to set PS while PE is not set there will not be any programming procedure and the PS bit will be unaffected. Consequently PS bit can not be set if EN is low. PS can be affected by the user set if, and only if, EN and PE bits are also set to one.

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 8; the controller being externally linked to both the Reset and Oscillator circuits, while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers.

2.2 CPU REGISTERS

The ST6 Family CPU core features six registers and three pairs of flags available to the programmer. These are described in the following paragraphs.

Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be addressed in Data space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data space.

Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in Data space. They are used in the register-indirect addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST6 instruction set can use the indirect registers as any other register of the data space.

Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data space as RAM locations at addresses 82h (V) and 83h (W). They can also be accessed using the direct and bit direct addressing modes. Thus, the ST6 instruction set can use the short direct registers as any other register of the data space.

Program Counter (PC). The program counter is a 12-bit register which contains the address of the next ROM location to be processed by the core. This ROM location may be an opcode, an operand, or the address of an operand. The 12-bit length allows the direct addressing of 4096 bytes in Program space.

Figure 8. ST6 Core Block Diagram

		0,01 TO 8MHz
	RESET	OSCin		OSCout
				INTERRUPTS
		CONTROLLER
						DATA SPACE
		FLAG	CONTROL
	OPCODE		SIGNALS			DATA
		VALUES		ADDRESS/READ LINE
		2				RAM/EEPROM
PROGRAM						DATA
ROM/EPROM				ADDRESS
					256	ROM/EPROM
				DECODER
		A-DATA		B-DATA		DEDICATIONS
						ACCUMULATOR
12	Program Counter
	and	FLAGS
	6 LAYER STACK			ALU
				RESULTS TO DATA SPACE (WRITE LINE)
						VR01811
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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

CPU REGISTERS (Cont’d)

However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register.

The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways:

-JP (Jump) instruction . . . . . PC=Jump address

-CALL instruction . . . . . . . . . PC= Call address

-Relative Branch Instruction . PC= PC +/- offset

- Interrupt . . . . . . . . . . . . . .PC=Interrupt vector

- Reset . . . . . . . . . . . . . . . . . PC= Reset vector

-RET & RETI instructions . . . . PC= Pop (stack)

-Normal instruction . . . . . . . . . . . . .PC= PC + 1

Flags (C, Z). The ST6 CPU includes three pairs of flags (Carry and Zero), each pair being associated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt mode (CNMI, ZNMI).

The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (resp. the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context switching and thus retain their status.

The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction; it also participates in the rotate left instruction.

The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared.

Switching between the three sets of flags is performed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is

automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags.

Stack. The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. The stack will remain in its “deepest” position if more than 6 nested calls or interrupts are executed, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed.

Figure 9. ST6 CPU Programming Mode

l

INDEX

b7

X REG. POINTER

b0

SHORT

REGISTER

b7

Y REG. POINTER

b0

DIRECT

ADDRESSING

b7

V REGISTER

b0

MODE

b7

W REGISTER

b0

b7

ACCUMULATOR

b0

b11

PROGRAM COUNTER

b0

SIX LEVELS

STACK REGISTER

NORMAL FLAGS

C

Z

INTERRUPT FLAGS

C

Z

NMI FLAGS

C

Z

VA000423

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3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 ON-CHIP CLOCK OSCILLATOR

The internal oscillator circuit is designed to require a minimum of external components. A crystal quartz, a ceramic resonator, or an external signal (provided to the OSCin pin) may be used to generate a system clock with various stability/cost tradeoffs. The typical clock frequency is 8MHz. Please note that different frequencies will affect the operation of those peripherals (D/As, SPI) whose reference frequencies are derived from the system clock.

The different clock generator connection schemes are shown in Figure 10 and 11. One machine cycle takes 13 oscillator pulses; 12 clock pulses are needed to increment the PC while and additional 13th pulse is needed to stabilize the internal latches during memory addressing. This means that with a clock frequency of 8MHz the machine cycle is 1.625µSec.

The crystal oscillator start-up time is a function of many variables: crystal parameters (especially RS), oscillator load capacitance (CL), IC parameters, ambient temperature, and supply voltage.It must be observed that the crystal or ceramic leads and circuit connections must be as short as possible. Typical values for CL1 and CL2 are in the range of 15pF to 22pF but these should be chosen based on the crystal manufacturers specification. Typical input capacitance for OSCin and OSCout pins is 5pF.

The oscillator output frequency is internally divided by 13 to produce the machine cycle and by 12 to produce the Timers and the Watchdog clock. A byte cycle is the smallest unit needed to execute any operation (i.e., increment the program counter). An instruction may need two, four, or five byte cycles to be executed (See Table 6).

Table 6. Instruction Timing with 8MHz Clock

	Instruction Type	Cycles	Execution
			Time
	Branch if set/reset	5 Cycles	8.125μs
	Branch & Subroutine Branch	4 Cycles	6.50μs
	Bit Manipulation	4 Cycles	6.50μs
	Load Instruction	4 Cycles	6.50μs
	Arithmetic & Logic	4 Cycles	6.50μs
	Conditional Branch	2 Cycles	3.25μs
	Program Control	2 Cycles	3.25μs

Figure 10. Clock Generator Option 1

CRYSTAL/RESONATOR CLOCK

ST6xxx

OSCin OSCout

CL1

CL2

VA0016B

Figure 11. Clock Generator Option 2

EXTERNAL CLOCK

ST6xxx

OSCin OSCout

NC

VA0015C

Figure 12. OSCin, OSCout Diagram

OSCin, OSCout (QUARTZ PINS)

VDD

OSCin

1M	VDD

In OSCout

VA00462

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3.2 RESETS

The MCU can be reset in three ways:

–by the external Reset input being pulled low;

–by Power-on Reset;

–by the digital Watchdog peripheral timing out.

3.2.1 RESET Input

The RESET pin may be connected to a device of the application board in order to reset the MCU if required. The RESET pin may be pulled low in RUN, WAIT or STOP mode. This input can be used to reset the MCU internal state and ensure a correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal Reset signal is generated by adding a delay to the external signal. Therefore even short pulses on the RESET pin are acceptable, provided VDD has completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the RESET pin is held low.

If RESET activation occurs in RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the Inputs and Outputs are configured as inputs with pull-up resistors if available. When the level on the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

If RESET pin activation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs are configured as inputs with pull-up resistors if available. When the level of the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

3.2.2 Power-on Reset

The function of the POR circuit consists in waking up the MCU at an appropriate stage during the power-on sequence. At the beginning of this sequence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up resistors and no instruction is executed. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence is executed immediately following the internal delay.

The internal delay is generated by an on-chip counter. The internal reset line is released 2048 internal clock cycles after release of the external reset.

The internal POR device is a static mechanism which forces the reset state when VDD is below a threshold voltage in the range 3.4 to 4.2 Volts (see Figure 13). The circuit guarantees that the MCU

will exit or enter the reset state correctly, without spurious effects, ensuring, for example, that EEPROM contents are not corrupted.

Note: This feature is not available on OTP/EPROM Devices.

Figure 13. Power ON/OFF Reset operation

VDD

4.2

Threshold

3.4

t

VDD

POWER

ON/OFF

RESET

t

VR02037

Figure 14. Reset and Interrupt Processing

RESET

NMI MASK SET

INT LATCH CLEARED ( IF PRESENT )

SELECT

NMI MODE FLAGS

PUT FFEH

ON ADDRESS BUS

YES

IS RESET STILL

PRESENT?

NO

LOAD PC

FROM RESET LOCATIONS

FFE/FFF

FETCH INSTRUCTION

VA000427

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RESETS (Cont’d)

3.2.3 Watchdog Reset

The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst other things, resets the watchdog counter.

The MCU restarts just as though the Reset had been generated by the RESET pin, including the built-in stabilisation delay period.

3.2.4 Application Note

No external resistor is required between VDD and the Reset pin, thanks to the built-in pull-up device.

3.2.5 MCU Initialization Sequence

When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (located in program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a Reset, the Interrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode; this prevents the initialisation routine from being interrupted. The initialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal

Figure 16. Reset Circuit

mode and enable interrupts. If no pending interrupt is present at the end of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETI instruction. If, however, a pending interrupt is present, it will be serviced.

Figure 15. Reset and Interrupt Processing

RESET

JP	JP:2 BYTES/4 CYCLES

RESET

VECTOR

INITIALIZATION
ROUTINE	RETI: 1 BYTE/2 CYCLES
	RETI

VA00181

			ST6
	OSCILLATOR		INTERNAL
	SIGNAL		RESET
			COUNTER
RESET	1k	TO ST6	RESET
(ACTIVE LOW)	VDD
	300k
			WATCHDOG RESET
			POWER ON/OFF RESET
			VA0200E

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3.3 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION

The hardware activated digital watchdog function consists of a down counter that is automatically initialized after reset so that this function does not need to be activated by the user program. As the watchdog function is always activated this down counter can not be used as a timer. The watchdog is using one data space register (HWDR location D8h). The watchdog register is set to FEh on reset and immediately starts to count down, requiring no software start. Similarly the hardware activated watchdog can not be stopped or delayed by software.

The watchdog time can be programmed using the 6 MSBs in the watchdog register, this gives the

possibility to generate a reset in a time between 3072 to 196608 oscillator cycles in 64 possible steps. (With a clock frequency of 8MHz this means from 384ms to 24.576ms). The reset is prevented if the register is reloaded with the desired value before bits 2-7 decrement from all zeros to all ones.

The presence of the hardware watchdog deactivates the STOP instruction and a WAIT instruction is automatically executed instead of a STOP. Bit 1 of the watchdog register (set to one at reset) can be used to generate a software reset if cleared to zero). Figure 17 shows the watchdog block diagram while Figure 18 shows its working principle.

Figure 17. Hardware Activated Watchdog Block Diagram

RESET

	Q		-27	-2 8	-12
	RSFF
S	R	DB1.7	LOAD SET	SET
					OSCILLATOR
		8			CLOCK
		DB0
		WRITE
			RESET
		DATA BUS
					VA00010

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HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION (Cont’d)

Hardware Activated Watchdog Register (HWDR)

Address: D8h - Read/Write Reset Value: 0FEh

7							0
T1	T2	T3	T4	T5	T6	SR	C

T1-T6. These are the watchdog counter bits. It should be noted that D7 (T1) is the LSB of the counter and D2 (T6) is the MSB of the counter, these bits are in the opposite order to normal.

SR. This bit is set to one during the reset phase and will generate a software reset if cleared to zero.

C. This is the watchdog activation bit that is hardware set. The watchdog function is always activated independently of changes of value of this bit.

The register reset value is FEh (Bit 1-7 set to one, Bit 0 cleared).

Figure 18. Hardware Activated Watchdog

Working Principle

D0

BIT7

D1

REGISTER

BIT6

RESET

D2

CONTROL

BIT5

D3

BIT4

D4

WATCHDOG

BIT3

D5

BIT2

D6

BIT1

D7

BIT0

8-BIT

OSC-12

DOWN COUNTER

VA00190

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3.4 INTERRUPT

The ST638x Core can manage 4 different maskable interrupt sources, plus one non-maskable interrupt source (top priority level interrupt). Each source is associated with a particular interrupt vector that contains a Jump instruction to the related interrupt service routine. Each vector is located in the Program Space at a particular address (see Table 7). When a source provides an interrupt request, and the request processing is also enabled by the ST638x Core, then the PC register is loaded with the address of the interrupt vector (i.e. of the Jump instruction). Finally, the PC is loaded with the address of the Jump instruction and the interrupt routine is processed.

The relationship between vector and source and the associated priority is hardware fixed for the different ST638x devices. For some interrupt sources it is also possible to select by software the kind of event that will generate the interrupt.

All interrupts can be disabled by writing to the GEN bit (global interrupt enable) of the interrupt option register (address C8h). After a reset, ST638x is in non maskable interrupt mode, so no interrupts will be accepted and NMI flags will be used, until a RETI instruction is executed. If an interrupt is executed, one special cycle is made by the core, during that the PC is set to the related interrupt vector address. A jump instruction at this address has to redirect program execution to the beginning of the related interrupt routine. The interrupt detecting cycle, also resets the related interrupt flag (not available to the user), so that another interrupt can be stored for this current vector, while its driver is under execution.

If additional interrupts arrive from the same source, they will be lost. NMI can interrupt other interrupt routines at any time, while other interrupts cannot interrupt each other. If more than one interrupt is waiting for service, they are executed according to their priority. The lower the number, the higher the priority. Priority is, therefore, fixed. Interrupts are checked during the last cycle of an instruction (RETI included). Level sensitive interrupts have to be valid during this period.

3.4.1 Interrupt Vectors/Sources

The ST638x Core includes 5 different interrupt vectors in order to branch to 5 different interrupt routines. The interrupt vectors are located in the fixed (or static) page of the Program Space.

The interrupt vector associated with the nonmaskable interrupt source is named interrupt vector #0. It is located at the (FFCh,FFDh) addresses in the Program Space. This vector is associated with the PC6/IRIN pin.

The interrupt vectors located at addresses (FF6h, FF7h), (FF4h, FF5h), (FF2h, FF3h), (FF0h, FF1h) are named interrupt vectors #1, #2, #3 and #4 respectively. These vectors are associated with TIMER 2 (#1), VSYNC (#2), TIMER 1 (#3) and PC4(PWRIN) (#4).

Table 7. Interrupt Vectors/Sources

Relationships

	Interrupt Source		Associated	Vector
			Vector	Address
	PC6/IRIN Pin	1	Interrupt	0FFCh-0FFDh
			Vector # 0 (NMI)
	Timer 2		Interrupt	0FF6h-0FF7h
			Vector # 1
	Vsync		Interrupt	0FF4h-0FF5h
			Vector #2
	Timer 1		Interrupt	0FF2h-0FF3h
			Vector #3
	PC4/PWRIN		Interrupt	0FF0h-0FF1h
			Vector #4

Note 1. This pin is associated with the NMI Interrupt Vector

3.4.2 Interrupt Priority

The non-maskable interrupt request has the highest priority and can interrupt any other interrupt routines at any time, nevertheless the other interrupts cannot interrupt each other. If more than one interrupt request is pending, they are processed by the ST638x Core according to their priority level: vector #1 has the higher priority while vector #4 the lower. The priority of each interrupt source is hardware fixed.

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INTERRUPTS (Cont’d)

3.4.3 Interrupt Option Register

Interrupt Option Register (IOR)

Address: (C8h) - Write only

Reset Value: X000XXXXb

7							0
-	EL1	ES2	GEN	-	-	-	-

The Interrupt Option Register (IOR register, location C8h) is used to enable/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register can be addressed in the Data Space as RAM location at the C8h address, nevertheless it is a write-only register that can not be accessed with single-bit operations. The operating modes of the external interrupt inputs associated to interrupt vectors #1 and #2 are selected through bits 5 and 6 of the IOR register.

Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used.

D7. Not used.

EL1. This is the Edge/Level selection bit of interrupt #1. When set to one, the interrupt is generated on low level of the related signal; when cleared to zero, the interrupt is generated on falling edge. The bit is cleared to zero after reset.

ES2. This is the edge selection bit on interrupt #2. This bit is used on the ST638x devices with onchip OSD generator for VSYNC detection. When this bit is se to one, the interrupt #2 is positive edge sensitive, when cleared to zero the negative edge sensitive interrupt is selected.

GEN. This is the global enable bit. When set to one all interrupts are globally enabled; when this bit is cleared to zero all interrupts are disabled (excluding NMI).

D3 - D0. These bits are not used.

3.4.4 Interrupt Procedure

The interrupt procedure is very similar to a call procedure; the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event the user does not know about the context and the time at which it occurred. As a result the user should save all the data space registers which will be used inside the interrupt routines. There are separate sets of processor flags for normal, interrupt and non-maskable interrupt modes which are automatically switched and so these do not need to be saved.

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The following list summarizes the interrupt procedure (refer also to Figure 19*)

–Interrupt detection

–The flags C and Z of the main routine are exchanged with the flags C and Z of the interrupt routine (resp. the NMI flags)

–The value of the PC is stored in the first level of the stack - The normal interrupt lines are inhibited (NMI still active)

–The edge flip-flop is reset

–The related interrupt vector is loaded in the PC.

–User selected registers are saved inside the interrupt service routine (normally on a software stack)

–The source of the interrupt is found by polling (if more than one source is associated to the same vector)

–Interrupt servicing

–Return from interrupt (RETI)

–Automatically the ST638x core switches back to the normal flags (resp the interrupt flags) and pops the previous PC value from the stack

Figure 19. Interrupt Processing Flow-Chart

		INSTRUCTION
		FETCH
		INSTRUCTION
		EXECUTE
		INSTRUCTION
				LOAD PC FROM
		WAS	NO	INTERRUPT VECTOR
				(FFC/FFD)
		THE INSTRUCTION
		A RETI ?
		YES
	YES		IS THE CORE	SET
		?	ALREADY IN	INTERRUPT MASK
			NORMAL MODE?
		NO
		CLEAR		PUSH THE
		INTERRUPT MASK		PC INTO THE STACK
		SELECT
		PROGRAM FLAGS		SELECT
				INTERNAL MODE FLAG
		“POP”
		THE STACKED PC
	NO	?	CHECK IF THERE IS
			AN INTERRUPT REQUEST
			AND INTERRUPT MASK
		YES
				VA000014

ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

INTERRUPTS (Cont’d)

The interrupt routine begins usually by the identification of the device that has generated the interrupt request. The user should save the registers which are used inside the interrupt routine (that holds relevant data) into a software stack. After the RETI instruction execution, the Core carries out the previous actions and the main routine can continue.

3.4.5 ST638x Interrupt Details

IR Interrupt (#0). The IRIN/PC6 Interrupt is con- nected to the first interrupt #0 (NMI, 0FFCh). If the IRINT interrupt is disabled at the Latch circuitry, then it will be high. The #0 interrupt input detects a high to low level. Note that once #0 has been latched, then the only way to remove the latched #0 signal is to service the interrupt. #0 can interrupt the other interrupts. A simple latch is provided from the PC6(IRIN) pin in order to generate the IRINT signal. This latch can be triggered by either the positive or negative edge of IRINT signal. IRINT is inverted with respect to the latch. The latch can be read by software and reset by software.

TIMER 2 Interrupt (#1). The TIMER 2 Interrupt is connected to the interrupt #1 (0FF6h). The TIMER 2 interrupt generates a low level (which is latched in the timer). Only the low level selection for #1 can be used. Bit 6 of the interrupt option register C8h has to be set.

VSYNC Interrupt (#2). The VSYNC Interrupt is connected to the interrupt #2. When disabled the VSYNC INT signal is low. The VSYNC INT signal is inverted with respect to the signal applied to the VSYNC pin. Bit 5 of the interrupt option register C8h is used to select the negative edge (ES2=0) or the positive edge (ES2=1); the edge will depend on the application. Note that once an edge has been latched, then the only way to remove the

latched signal is to service the interrupt. Care must be taken not to generate spurious interrupts. This interrupt may be used to synchronize the VSYNC signal in order to change characters in the OSD only when the screen is on vertical blanking (if desired). This method may also be used to blink characters.

TIMER 1 Interrupt (#3). The TIMER 1 Interrupt is connected to the fourth interrupt #3 (0FF2h) which detects a low level (latched in the timer).

PWR Interrupt (#4). The PWR Interrupt is connected to the fifth interrupt #4 (0FF0h). If the PWRINT is disabled at the PWR circuitry, then it will be high. The #4 interrupt input detects a low level. A simple latch is provided from the PC4 (PWRIN)pin in order to generate the PWRINT signal. This latch can be triggered by either the positive or negative edge of the PWRIN signal. PWRINT is inverted with respect to the latch. The latch can be reset by software.

Notes: Global disable does not reset edge sensitive interrupt flags. These edge sensitive interrupts become pending again when global disabling is released. Moreover, edge sensitive interrupts are stored in the related flags also when interrupts are globally disabled, unless each edge sensitive interrupt is also individually disabled before the interrupting event happens. Global disable is done by clearing the GEN bit of Interrupt option register, while any individual disable is done in the control register of the peripheral. The on-chip Timer peripherals have an interrupt request flag bit (TMZ), this bit is set to one when the device wants to generate an interrupt request and a mask bit (ETI) that must be set to one to allow the transfer of the flag bit to the Core.

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3.5 POWER SAVING MODES

STOP and WAIT modes have been implemented in the ST638x in order to reduce the current consumption of the device during idle periods. These two modes are described in the following paragraphs. Since the hardware activated digital watchdog function is present, the STOP instruction is de-activated and any attempt to execute it will cause the automatic execution of a WAIT instruction.

3.5.1 WAIT Mode

The configuration of the MCU in the WAIT mode occurs as soon as the WAIT instruction is executed. The microcontroller can also be considered as being in a “software frozen” state where the Core stops processing the instructions of the routine, the contents of the RAM locations and peripheral registers are saved as long as the power supply voltage is higher than the RAM retention voltage but where the peripherals are still working. The WAIT mode is used when the user wants to reduce the consumption of the MCU when it is in idle, while not losing count of time or monitoring of external events. The oscillator is not stopped in order to provide clock signal to the peripherals. The timers counting may be enabled (writing the PSI bit in TSCR1 register) and the timer interrupt may be also enabled before entering the WAIT mode; this allows the WAIT mode to be left when timer interrupt occurs. If the exit from the WAIT mode is performed with a general RESET (either from the activation of the external pin or by watchdog reset) the MCU will enter a normal reset procedure as described in the RESET chapter. If an interrupt is generated during WAIT mode the MCU behaviour depends on the state of the MCU Core before the initialization of the WAIT sequence, but also of the kind of the interrupt request that is generated. This case will be described in the following paragraphs. In any case, the MCU Core does not generate any delay after the occurrence of the interrupt because the oscillator clock is still available.

3.5.2 STOP Mode

Since the hardware activated watchdog is present on the ST638x, the STOP instruction has been deactivated. Any attempt to execute a STOP instruction will cause a WAIT instruction to be executed instead.

3.5.3 Exit from WAIT Mode

The following paragraphs describe the output procedure of the MCU Core from WAIT mode when an interrupt occurs. It must be noted that the restart sequence depends on the original state of the MCU (normal, interrupt or non-maskable interrupt

mode) before the start of the WAIT sequence, but also of the type of the interrupt request that is generated. In all cases the GEN bit of IOR has to be set to 1 in order to restart from WAIT mode. Contrary to the operation of NMI in the run mode, the NMI is masked in WAIT mode if GEN=0.

Normal Mode. If the MCU Core was in the main routine when the WAIT instruction has been executed, the Core exits from WAIT mode as soon as an interrupt occurs; the corresponding interrupt routine is executed, and at the end of the interrupt service routine, the instruction that follows the WAIT instruction is executed if no other interrupts are pending.

Non-maskable Interrupt Mode. If the WAIT instruction has been executed during the execution of the non-maskable interrupt routine, the MCU Core outputs from WAIT mode as soon as any interrupt occurs: the instruction that follows the WAIT instruction is executed and the MCU Core is still in the non-maskable interrupt mode even if another interrupt has been generated.

Normal Interrupt Mode. If the MCU Core was in the interrupt mode before the initialization of the WAIT sequence, it outputs from the wait mode as soon as any interrupt occurs. Nevertheless, two cases have to be considered:

–If the interrupt is a normal interrupt, the interrupt routine in which the WAIT was entered will be completed with the execution of the instruction that follows the WAIT and the MCU Core is still in the interrupt mode. At the end of this routine pending interrupts will be serviced in accordance to their priority.

–If the interrupt is a non-maskable interrupt, the non-maskable routine is processed at first. Then, the routine in which the WAIT was entered will be completed with the execution of the instruction that follows the WAIT and the MCU Core is still in the normal interrupt mode.

Notes:

If all the interrupt sources are disabled, the restart of the MCU can only be done by a Reset activation. The Wait instruction is not executed if an enabled interrupt request is pending. In ST638x devices, the hardware activated digital watchdog function is present. As the watchdog is always activated, the STOP instruction is de-activated and any attempt to execute the STOP instruction will cause an execution of a WAIT instruction.

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