SGS Thomson Microelectronics ST72C124J2, ST72C334N4, ST72C334N2, ST72C334J4, ST72C334J2 Datasheet

ST72334J/N,

ST72314J/N, ST72124J

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES

			PRELIMINARY DATA
■	Memories
	± 8K or 16K Program memory (ROM or single
	voltage FLASH) with read-out protection and
	in-situ programming (remote ISP)
	± 256 bytes EEPROM Data memory (with read-
	out protection option in ROM devices)
	± 384 or 512 bytes RAM
■	Clock, Reset and Supply Management	PSDIP56	PSDIP42
	± Enhanced reset system

±Enhanced low voltage supply supervisor with 3 programmable levels

±Clock sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System

±4 Power Saving Modes: Halt, Active-Halt, Wait and Slow

±Beep and clock-out capabilities

■Interrupt Management

±10 interrupt vectors plus TRAP and RESET

±15 external interrupt lines (4 vectors)

■44 or 32 I/O Ports

±44 or 32 multifunctional bidirectional I/O lines:

±21 or 19 alternate function lines

±12 or 8 high sink outputs

■4 Timers

±Configurable watchdog timer

±Realtime base

±Two 16-bit timers with: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes

■2 Communications Interfaces

±SPI synchronous serial interface

±SCI asynchronous serial interface

Device Summary

TQFP64	TQFP44
14 x 14	10 x 10

■1 Analog Peripheral

±8-bit ADC with 8 input channels (6 only on ST72334Jx, not available on ST72124J2)

■Instruction Set

±8-bit data manipulation

±63 basic instructions

±17 main addressing modes

±8 x 8 unsigned multiply instruction

±True bit manipulation

■Development Tools

±Full hardware/software development package

Features ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4

Program memory - bytes	8K	8K	16K	8K	16K	8K	16K	8K	16K
RAM (stack) - bytes	384 (256)	384 (256)	512 (256)	384 (256)	512 (256)	384 (256)	512 (256)	384 (256)	512 (256)
EEPROM - bytes	-	-	-	-	-	256	256	256	256
Peripherals				Watchdog, Two 16-bit Timers, SPI, SCI
	-				ADC
Operating Supply					3.0V to 5.5 V
CPU Frequency				Up to 8 MHz (with up to 16 MHz oscillator)
Operating Temperature			-40°C to +85°C (-40°C to +105/125°C optional)
Packages	TQFP44 / SDIP42			TQFP64 / SDIP56		TQFP44 / SDIP42		TQFP64 / SDIP56
									Rev. 2.1
May 2000									1/148

This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.

Table of Contents

1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5 MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 17
6.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 17
6.2	MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 17
6.3	MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 18
6.4	POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 19
6.5	ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 19
6.6	REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 20
6.7	READ-OUT PROTECTION OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 20
7 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 21
7.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 21
7.2	MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 21
7.3	CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 21
8 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 24
8.1	LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 25
8.2	RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 26
8.3	MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 28
8.4	CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 29
8.5	SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION . . . . . . . . . . . . . . . . .	. . . . 30
9 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 31
9.1	NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 31
9.2	EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 31
9.3	PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 31
10 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 33
10.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 33
10.2	SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 33
10.3	WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 34
10.4	ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 35
11 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 37
11.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 37
11.2	FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 37
		148
11.3	I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 40
11.4	LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 41

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	Table of Contents
11.5	INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
12 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		44
12.1	I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
12.2	I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
12.3	REGISTERS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
13 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		47
13.1	WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
13.2	MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . .	50
13.3	16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	52
13.4	SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
13.5	SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	83
13.6	8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	95
14 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		99

14.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 14.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

15 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

15.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 15.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 15.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 15.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 15.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 15.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 15.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 15.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 15.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 15.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 15.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 132 15.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

16 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

137

16.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 16.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 16.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 16.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

17 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 143

17.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 17.2 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

18 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

147

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ST72334J/N, ST72314J/N, ST72124J

1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION

New Features available on the ST72C334

■8 or 16K FLASH/ROM with In-Situ Programming and Read-out protection

■New ADC with a better accuracy and conversion time

■New configurable Clock, Reset and Supply system

■New power saving mode with real time base: Active Halt

■Beep capability on PF1

■New interrupt source: Clock security system (CSS) or Main clock controller (MCC)

ST72C334 I/O Configuration and Pinout

■Same pinout as ST72E331

■PA6 and PA7 are true open drain I/O ports without pull-up (same as ST72E331)

■PA3, PB3, PB4 and PF2 have no pull-up configuration (all I/Os present on TQFP44)

■PA5:4, PC3:2, PE7:4 and PF7:6 have high sink capabilities (20mA on N-buffer, 2mA on P-buffer and pull-up). On the ST72E331, all these pads (except PA5:4) were 2mA push-pull pads without high sink capabilities. PA4 and PA5 were 20mA true open drains.

New Memory Locations in ST72C334

■20h: MISCR register becomes MISCR1 register (naming change)

■29h: new control/status register for the MCC module

■2Bh: new control/status register for the Clock, Reset and Supply control. This register replaces the WDGSR register keeping the WDOGF flag compatibility.

■40h: new MISCR2 register

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2 INTRODUCTION

The ST72334J/N, ST72314J/N and ST72124J devices are members of the ST7 microcontroller family. They can be grouped as follows:

± ST72334J/N devices are designed for mid-range applications with Data EEPROM, ADC, SPI and SCI interface capabilities.

±ST72314J/N devices target the same range of applications but without Data EEPROM.

±ST72124J devices are for applications that do not need Data EEPROM and the ADC peripheral.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set.

The ST72C334J/N, ST72C314J/N and ST72C124J versions feature single-voltage

Figure 1. General Block Diagram

ST72334J/N, ST72314J/N, ST72124J

FLASH memory with byte-by-byte In-Situ Programming (ISP) capability.

Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

For easy reference, all parametric data are located in Section 15 on page 105.

RESET

ISPSEL

VDD

VSS

OSC1

OSC2

PF7,6,4,2:0 (6-BIT)

PE7:0 (6-BIT for N versions)

(2-BIT for J versions)

8-BIT CORE

ALU

CONTROL

LVD

MULTI OSC

+

CLOCK FILTER

MCC/RTC

PORT F

TIMER A

BEEP

PORT E

SCI

WATCHDOG

BUS DATA AND ADDRESS

PROGRAM

MEMORY (8K or 16K Bytes)

RAM

(384 or 512 Bytes)

EEPROM

(256 Bytes)

	PORT A	PA7:0
		(8-BIT for N versions)
		(5-BIT for J versions)
	PORT B	PB7:0
		(8-BIT for N versions)
		(5-BIT for J versions)
	PORT C
	TIMER B	PC7:0
		(8-BIT)
	SPI
	PORT D
		PD7:0
	8-BIT ADC	(8-BIT for N versions)
		(6-BIT for J versions)
		VDDA
		VSSA

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ST72334J/N, ST72314J/N, ST72124J

3 PIN DESCRIPTION

Figure 2. 64-Pin TQFP Package Pinout (N versions)

(HS) PE4

(HS) PE5

(HS) PE6

(HS) PE7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

AIN0 / PD0 AIN1 / PD1

AIN2 / PD2

AIN3 / PD3

NC

NC PE1/ RDI PE0/ TDO

V

OSC1 OSC2

V

NC

NC

RESET

ISPSEL PA7(HS)

PA6(HS)

PA5(HS)

PA4(HS)

2

2

DD

SS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VSS_1

1

48

2

47

VDD_1

	3		46
	4		45
	5		ei0
			44
	6	ei2	43
	7		42
	8		41
	9		40
	10	ei3	39
	11		38
	12		37
	13		36
	14		35
	15	ei1	34
	16		33

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

AIN4 / PD4

AIN5 / PD5

AIN6 / PD6

AIN7 / PD7

DDA

SSA

DD_3

SS_3

MCO / PF0

BEEP / PF1

PF2

NC

OCMP1 A / PF4

NC

ICAP1 A / (HS) PF6

EXTCLK A / (HS) PF7

V

V

V

V

(HS) eix

PA3

PA2

PA1

PA0

PC7 / SS

PC6 / SCK / ISPCLK

PC5 / MOSI

PC4 / MISO / ISPDATA

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B

PC0 / OCMP2_B

VSS_0

VDD_0

20mA high sink capability associated external interrupt vector

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ST72334J/N, ST72314J/N, ST72124J

PIN DESCRIPTION (Cont'd)

Figure 3. 56-Pin SDIP Package Pinout (N versions)

PB4	1			56	PB3
PB5	2	ei3	ei2	55	PB2
PB6	3			54	PB1
PB7	4			53	PB0
AIN0 / PD0	5			52	PE7 (HS)
AIN1 / PD1	6			51	PE6 (HS)
AIN2 / PD2	7			50	PE5 (HS)
AIN3 / PD3	8			49	PE4 (HS)
AIN4 / PD4	9			48	PE1 / RDI
AIN5 / PD5	10			47	PE0 / TDO
AIN6 / PD6	11			46	VDD_2
AIN7 / PD7	12			45	OSC1
VDDA	13			44	OSC2
VSSA	14			43	VSS_2
MCO / PF0	15			42	RESET
BEEP / PF1	16	ei1		41	ISPSEL
PF2	17			40	PA7 (HS)
OCMP1_A / PF4	18			39	PA6 (HS)I
ICAP1_A / (HS) PF6	19			38	PA5 (HS)
EXTCLK_A / (HS) PF7	20			37	PA4 (HS)
VDD_0	21			36	VSS_1
VSS_0	22			35	VDD_1
OCMP2_B / PC0	23			34	PA3
OCMP1_B / PC1	24		ei0	33	PA2
ICAP2_B / (HS) PC2	25			32	PA1
ICAP1_B / (HS) PC3	26			31	PA0
ISPDATA/ MISO / PC4	27			30	PC7 / SS
MOSI / PC5	28			29	PC6 / SCK / ISPCLK
					(HS)	20mA high sink capability
					eix	associated external interrupt vector

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ST72334J/N, ST72314J/N, ST72124J

PIN DESCRIPTION (Cont'd)

Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts (J versions)

	PE0/ TDO	V	OSC1	OSC2	V	RESET	ISPSEL PA7(HS) PA6(HS) PA5(HS)	PA4(HS)
		2			2
		DD			SS
PE1 / RDI	44 43 42 41 40 39 38 37 36 35 34
	1							33
PB0	2							32
PB1	3	ei2					ei0	31
PB2	4							30
PB3	5							29
PB4	6	ei3						28
AIN0 / PD0	7							27
AIN1 / PD1	8							26
AIN2 / PD2	9							25
AIN3 / PD3	10				ei1			24
AIN4 / PD4	11							23
	12 13 14 15 16 17 18 19 20 21 22

VSS_1

VDD_1

PA3

PC7 / SS

PC6 / SCK / ISPCLK PC5 / MOSI

PC4 / MISO / ISPDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B

PC0 / OCMP2_B

/ PD5	DDA	SSA	/ PF0	/ PF1	PF2	/ PF4
	V	V
AIN5			MCO	BEEP		OCMP1 A
PB4		1		EI3
AIN0 / PD0		2				ei2
AIN1 / PD1		3
AIN2 / PD2		4
AIN3 / PD3		5
AIN4 / PD4		6
AIN5 / PD5		7
VDDA		8
VSSA		9
MCO / PF0		10
BEEP / PF1		11		ei1
PF2		12
OCMP1_A / PF4		13
ICAP1_A / (HS) PF6		14
EXTCLK_A / (HS) PF7		15
OCMP2_B / PC0		16
OCMP1_B / PC1		17
ICAP2_B/ (HS) PC2		18
ICAP1_B / (HS) PC3		19				ei0
ISPDATA / MISO / PC4		20
MOSI / PC5		21

PF6	PF7	DD 0	SS 0
(HS)	(HS)	V	V
ICAP1 A /	EXTCLK A /
	42		PB3
	41		PB2
	40		PB1
	39		PB0
	38		PE1 / RDI
	37		PE0 / TDO
	36		VDD_2
	35		OSC1
	34		OSC2
	33		VSS_2
	32		RESET
	31		ISPSEL
	30		PA7 (HS)
	29		PA6 (HS)
	28		PA5 (HS)
	27		PA4 (HS)
	26		VSS_1
	25		VDD_1
	24		PA3
	23		PC7 / SS
	22		PC6 / SCK / ISPCLK
			(HS)	20mA high sink capability
			eix	associated external interrupt vector

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PIN DESCRIPTION (Cont'd)

For external pin connection guidelines, refer to Section 15 ºELECTRICAL CHARACTERISTICSº on page 105.

Legend / Abbreviations for Table 1:

Type:		I = input, O = output, S = supply
Input level:		A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD,
		CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level:		HS = 20mA high sink (on N-buffer only)
Port and control configuration:
±	Input:	float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
±	Output:	OD = open drain 2), PP = push-pull

Refer to Section 11 ºI/O PORTSº on page 37 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.

Table 1. Device Pin Description

TQFP64	Pin n°		SDIP42		Type	Level
	SDIP56	QFP44		Pin Name		Input	Output
1	49			PE4 (HS)	I/O CT		HS
2	50			PE5 (HS)	I/O CT		HS
3	51			PE6 (HS)	I/O CT		HS
4	52			PE7 (HS)	I/O CT		HS
5	53	2	39	PB0	I/O	CT
6	54	3	40	PB1	I/O	CT
7	55	4	41	PB2	I/O	CT
8	56	5	42	PB3	I/O	CT
9	1	6	1	PB4	I/O	CT
10	2			PB5	I/O	CT
11	3			PB6	I/O	CT
12	4			PB7	I/O	CT
13	5	7	2	PD0/AIN0	I/O	CT
14	6	8	3	PD1/AIN1	I/O	CT
15	7	9	4	PD2/AIN2	I/O	CT
16	8	10	5	PD3/AIN3	I/O	CT
17	9	11	6	PD4/AIN4	I/O	CT
18	10	12	7	PD5/AIN5	I/O	CT
19	11			PD6/AIN6	I/O	CT
20	12			PD7/AIN7	I/O	CT
21	13	13	8	VDDA	S
22	14	14	9	VSSA	S
23				VDD_3	S

float X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

	Port				Main
Input			Output		function	Alternate function
wpu					(after
	int	ana	OD	PP
					reset)
X			X	X	Port E4
X			X	X	Port E5
X			X	X	Port E6
X			X	X	Port E7
ei2			X	X	Port B0
ei2			X	X	Port B1
ei2			X	X	Port B2
	ei2		X	X	Port B3
	ei3		X	X	Port B4
ei3			X	X	Port B5
ei3			X	X	Port B6
ei3			X	X	Port B7
X		X	X	X	Port D0	ADC Analog Input 0
X		X	X	X	Port D1	ADC Analog Input 1
X		X	X	X	Port D2	ADC Analog Input 2
X		X	X	X	Port D3	ADC Analog Input 3
X		X	X	X	Port D4	ADC Analog Input 4
X		X	X	X	Port D5	ADC Analog Input 5
X		X	X	X	Port D6	ADC Analog Input 6
X		X	X	X	Port D7	ADC Analog Input 7
					Analog Power Supply Voltage
					Analog Ground Voltage
					Digital Main Supply Voltage

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ST72334J/N, ST72314J/N, ST72124J

Pin n°

TQFP64 SDIP56 QFP44 SDIP42 24

25 15 15 10

26 16 16 11

27 17 17 12

28

29 18 18 13

30

31 19 19 14

32 20 20 15

33 21 21

34 22 22

35 23 23 16

36 24 24 17

37 25 25 18

38 26 26 19

39 27 27 20

40 28 28 21

41 29 29 22

42 30 30 23

4331

4432

4533

4634 31 24

4735 32 25

4836 33 26

4937 34 27

5038 35 28

5139 36 29

5240 37 30

	Type	Level
Pin Name		Input	Output
VSS_3	S
PF0/MCO	I/O	CT
PF1/BEEP	I/O	CT
PF2	I/O	CT
NC
PF4/OCMP1_A	I/O	CT
NC
PF6 (HS)/ICAP1_A	I/O	CT	HS
PF7 (HS)/EXTCLK_A I/O		CT	HS
VDD_0	S
VSS_0	S
PC0/OCMP2_B	I/O	CT
PC1/OCMP1_B	I/O	CT
PC2 (HS)/ICAP2_B	I/O	CT	HS
PC3 (HS)/ICAP1_B	I/O	CT	HS
PC4/MISO	I/O	CT
PC5/MOSI	I/O	CT
PC6/SCK	I/O	CT
PC7/SS	I/O	CT
PA0	I/O	CT
PA1	I/O	CT
PA2	I/O	CT
PA3	I/O	CT
VDD_1	S
VSS_1	S
PA4 (HS)	I/O	CT	HS
PA5 (HS)	I/O	CT	HS
PA6 (HS)	I/O	CT	HS
PA7 (HS)	I/O	CT	HS

		Port
	Input
float	wpu	int	ana
X	ei1
X	ei1
X		ei1
X	X
X	X
X	X
X	X
X	X
X	X
X	X
X	X
X	X
X	X
X	X
X	ei0
X	ei0
X	ei0
X		ei0
X	X
X	X
X
X

53 41 38 31	ISPSEL	I
54 42 39 32	RESET	I/O	C	X

55NC

56NC

57 43 40 33	VSS_3	S
58 44 41 34	OSC2 3)	O

		Main
Output		function	Alternate function
		(after
OD	PP
		reset)
		Digital Ground Voltage
X	X	Port F0	Main clock output (fOSC/2)
X	X	Port F1	Beep signal output
X	X	Port F2
Not Connected
X	X	Port F4	Timer A Output Compare 1
Not Connected
X	X	Port F6	Timer A Input Capture 1
X	X	Port F7	Timer A External Clock Source
		Digital Main Supply Voltage
		Digital Ground Voltage
X	X	Port C0	Timer B Output Compare 2
X	X	Port C1	Timer B Output Compare 1
X	X	Port C2	Timer B Input Capture 2
X	X	Port C3	Timer B Input Capture 1
X	X	Port C4	SPI Master In / Slave Out Data
X	X	Port C5	SPI Master Out / Slave In Data
X	X	Port C6	SPI Serial Clock
X	X	Port C7	SPI Slave Select (active low)
X	X	Port A0
X	X	Port A1
X	X	Port A2
X	X	Port A3
		Digital Main Supply Voltage
		Digital Ground Voltage
X	X	Port A4
X	X	Port A5
T		Port A6

TPort A7

Must be tied low in user mode. In programming mode when available, this pin acts as In-Situ Programming mode selection.

X

Top priority non maskable interrupt (active low)

Not Connected

Digital Ground Voltage

Resonator oscillator inverter output or capacitor input for RC oscillator

10/148

ST72334J/N, ST72314J/N, ST72124J

Pin n°
TQFP64 SDIP56 QFP44 SDIP42	Pin Name
59 45 42 35	OSC1 3)
60 46 43 36	VDD_3
61 47 44 37	PE0/TDO
62 48 1 38	PE1/RDI

63NC

64NC

	Level
Type	Input	Output

I

S

I/O CT I/O CT

		Port
	Input
float	wpu	int	ana

X X

X X

		Main
Output		function	Alternate function
		(after
OD	PP
		reset)

External clock input or Resonator oscillator inverter input or resistor input for RC oscillator

Digital Main Supply Voltage

X	X	Port E0	SCI Transmit Data Out
X	X	Port E1	SCI Receive Data In

Not Connected

Notes:

1. In the interrupt input column, ªeiº defines the associated external interrupt vector. If the weak pull-up

x

column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2. In the open drain output column, ªTº defines a true open drain I/O (P-Buffer and protection diode to V

DD

are not implemented). See Section 11 ºI/O PORTSº on page 37 and Section 15.8 ºI/O PORT PIN CHARACTERISTICSº on page 125 for more details.

3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see Section 3 ºPIN DESCRIPTIONº on page 6 and Section 15.5 ºCLOCK AND TIMING CHARACTERISTICSº on page 113 for more details.

11/148

ST72334J/N, ST72314J/N, ST72124J

4 REGISTER & MEMORY MAP

As shown in the Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, 384 or 512 bytes of RAM, up to 256 bytes of data EEPROM and 4 or 8 Kbytes of user program memory. The RAM

Figure 5. Memory Map

0000h

HW Registers

(see Table 2)

007Fh

0080h

384 Bytes RAM

01FFh

512 Bytes RAM

027Fh

0200h / 0280h

Reserved

0BFFh

0C00h

256 Bytes Data EEPROM

0CFFh

0D00h

Reserved

BFFFh

C000h

16K Bytes

E000h 8K Bytes Program

Program Memory

FFDFh Memory

FFE0h

Interrupt & Reset Vectors

(see Table 6 on page 32)

FFFFh

space includes up to 256 bytes for the stack from 0100h to 01FFh.

The highest address bytes contain the user reset and interrupt vectors.

IMPORTANT: Memory locations marked as ªReservedº must never be accessed. Accessing a reseved area can have unpredicable effects on the device.

	0080h	Short Addressing RAM
		Zero page
	00FFh	(128 Bytes)
		Stack or
	0100h
		16-bit Addressing RAM
	01FFh	(256 Bytes)
	0080h	Short Addressing RAM
	00FFh	Zero page
		(128 Bytes)
	0100h	Stack or
		16-bit Addressing RAM
	01FFh	(256 Bytes)
	0200h	16-bit Addressing
	027Fh	RAM

C000h

16 KBytes

E000h

8 KBytes

FFFFh

12/148

ST72334J/N, ST72314J/N, ST72124J

REGISTER & MEMORY MAP (Cont'd)

Table 2. Hardware Register Map

	Address	Block	Register	Register Name	Reset	Remarks
			Label		Status
	0000h		PADR	Port A Data Register	00h1)	R/W
	0001h	Port A	PADDR	Port A Data Direction Register	00h	R/W
	0002h		PAOR	Port A Option Register	00h	R/W 2)
	0003h			Reserved Area (1 Byte)
	0004h		PCDR	Port C Data Register	00h1)	R/W
	0005h	Port C	PCDDR	Port C Data Direction Register	00h	R/W
	0006h		PCOR	Port C Option Register	00h	R/W
	0007h			Reserved Area (1 Byte)
	0008h		PBDR	Port B Data Register	00h1)	R/W
	0009h	Port B	PBDDR	Port B Data Direction Register	00h	R/W
	000Ah		PBOR	Port B Option Register	00h	R/W 2)
	000Bh			Reserved Area (1 Byte)
	000Ch		PEDR	Port E Data Register	00h1)	R/W
	000Dh	Port E	PEDDR	Port E Data Direction Register	00h	R/W
	000Eh		PEOR	Port E Option Register	00h	R/W 2)
	000Fh			Reserved Area (1 Byte)
	0010h		PDDR	Port D Data Register	00h1)	R/W
	0011h	Port D	PDDDR	Port D Data Direction Register	00h	R/W
	0012h		PDOR	Port D Option Register	00h	R/W 2)
	0013h			Reserved Area (1 Byte)
	0014h		PFDR	Port F Data Register	00h1)	R/W
	0015h	Port F	PFDDR	Port F Data Direction Register	00h	R/W
	0016h		PFOR	Port F Option Register	00h	R/W
	0017h
	to			Reserved Area (9 Bytes)
	001Fh
	0020h		MISCR1	Miscellaneous Register 1	00h	R/W
	0021h		SPIDR	SPI Data I/O Register	xxh	R/W
	0022h	SPI	SPICR	SPI Control Register	0xh	R/W
	0023h		SPISR	SPI Status Register	00h	Read Only
	0024h
	to			Reserved Area (5 Bytes)
	0028h
	0029h	MCC	MCCSR	Main Clock Control / Status Register	01h	R/W

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ST72334J/N, ST72314J/N, ST72124J

	Address	Block	Register	Register Name	Reset	Remarks
			Label		Status
	002Ah	WATCHDOG	WDGCR	Watchdog Control Register	7Fh	R/W
	002Bh		CRSR	Clock, Reset, Supply Control / Status Register	000x 000x	R/W
	002Ch	Data-EEPROM	EECSR	Data-EEPROM Control/Status Register	00h	R/W
	002Dh			Reserved Area (4 Bytes)
	0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

TIMER A

TIMER B

SCI

TACR2	Timer A Control Register 2	00h	R/W
TACR1	Timer A Control Register 1	00h	R/W
TASR	Timer A Status Register	xxh	Read Only
TAIC1HR	Timer A Input Capture 1 High Register	xxh	Read Only
TAIC1LR	Timer A Input Capture 1 Low Register	xxh	Read Only
TAOC1HR	Timer A Output Compare 1 High Register	80h	R/W
TAOC1LR	Timer A Output Compare 1 Low Register	00h	R/W
TACHR	Timer A Counter High Register	FFh	Read Only
TACLR	Timer A Counter Low Register	FCh	Read Only
TAACHR	Timer A Alternate Counter High Register	FFh	Read Only
TAACLR	Timer A Alternate Counter Low Register	FCh	Read Only
TAIC2HR	Timer A Input Capture 2 High Register	xxh	Read Only 3)
TAIC2LR	Timer A Input Capture 2 Low Register	xxh	Read Only 3)
TAOC2HR	Timer A Output Compare 2 High Register	80h	R/W 3)
TAOC2LR	Timer A Output Compare 2 Low Register	00h	R/W 3)
MISCR2	Miscellaneous Register 2	00h	R/W
TBCR2	Timer B Control Register 2	00h	R/W
TBCR1	Timer B Control Register 1	00h	R/W
TBSR	Timer B Status Register	xxh	Read Only
TBIC1HR	Timer B Input Capture 1 High Register	xxh	Read Only
TBIC1LR	Timer B Input Capture 1 Low Register	xxh	Read Only
TBOC1HR	Timer B Output Compare 1 High Register	80h	R/W
TBOC1LR	Timer B Output Compare 1 Low Register	00h	R/W
TBCHR	Timer B Counter High Register	FFh	Read Only
TBCLR	Timer B Counter Low Register	FCh	Read Only
TBACHR	Timer B Alternate Counter High Register	FFh	Read Only
TBACLR	Timer B Alternate Counter Low Register	FCh	Read Only
TBIC2HR	Timer B Input Capture 2 High Register	xxh	Read Only
TBIC2LR	Timer B Input Capture 2 Low Register	xxh	Read Only
TBOC2HR	Timer B Output Compare 2 High Register	80h	R/W
TBOC2LR	Timer B Output Compare 2 Low Register	00h	R/W
SCISR	SCI Status Register	C0h	Read Only
SCIDR	SCI Data Register	xxh	R/W
SCIBRR	SCI Baud Rate Register	00xx xxxx	R/W
SCICR1	SCI Control Register 1	xxh	R/W
SCICR2	SCI Control Register 2	00h	R/W
SCIERPR	SCI Extended Receive Prescaler Register	00h	R/W
	Reserved area	---
SCIETPR	SCI Extended Transmit Prescaler Register	00h	R/W

14/148

ST72334J/N, ST72314J/N, ST72124J

	Address	Block	Register	Register Name	Reset	Remarks
			Label		Status
	0058h			Reserved Area (24 Bytes)
	006Fh
	0070h	ADC	ADCDR	Data Register	xxh	Read Only
	0071h		ADCCSR	Control/Status Register	00h	R/W
	0072h
	to			Reserved Area (14 Bytes)
	007Fh

Legend: x=undefined, R/W=read/write

Notes:

1.The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

2.The bits corresponding to unavailable pins are forced to 1 by hardware, affecting accordingly the reset status value. These bits must always keep their reset value.

3.External pin not available.

15/148

ST72334J/N, ST72314J/N, ST72124J

5 FLASH PROGRAM MEMORY

5.1 INTRODUCTION

FLASH devices have a single voltage non-volatile FLASH memory that may be programmed in-situ (or plugged in a programming tool) on a byte-by- byte basis.

5.2 MAIN FEATURES

■Remote In-Situ Programming (ISP) mode

■Up to 16 bytes programmed in the same cycle

■MTP memory (Multiple Time Programmable)

■Read-out memory protection against piracy

5.3 STRUCTURAL ORGANISATION

The FLASH program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants.

The FLASH program memory is mapped in the upper part of the ST7 addressing space and includes the reset and interrupt user vector area .

5.4 IN-SITU PROGRAMMING (ISP) MODE

The FLASH program memory can be programmed using Remote ISP mode. This ISP mode allows the contents of the ST7 program memory to be updated using a standard ST7 programming tools after the device is mounted on the application board. This feature can be implemented with a minimum number of added components and board area impact.

An example Remote ISP hardware interface to the standard ST7 programming tool is described below. For more details on ISP programming, refer to the ST7 Programming Specification.

Remote ISP Overview

The Remote ISP mode is initiated by a specific sequence on the dedicated ISPSEL pin.

The Remote ISP is performed in three steps:

±Selection of the RAM execution mode

±Download of Remote ISP code in RAM

±Execution of Remote ISP code in RAM to program the user program into the FLASH

Remote ISP hardware configuration

In Remote ISP mode, the ST7 has to be supplied with power (VDD and VSS) and a clock signal (oscillator and application crystal circuit for example).

This mode needs five signals (plus the VDD signal if necessary) to be connected to the programming tool. This signals are:

±RESET: device reset

±VSS: device ground power supply

±ISPCLK: ISP output serial clock pin

±ISPDATA: ISP input serial data pin

±ISPSEL: Remote ISP mode selection. This pin

must be connected to VSS on the application board through a pull-down resistor.

If any of these pins are used for other purposes on the application, a serial resistor has to be implemented to avoid a conflict if the other device forces the signal level.

Figure 6 shows a typical hardware interface to a standard ST7 programming tool. For more details on the pin locations, refer to the device pinout description.

Figure 6. Typical Remote ISP Interface

			HE10 CONNECTOR TYPE
XTAL			TO PROGRAMMING TOOL
CL0		CL1	1
OSC2	OSC1	DD	ISPSEL
		V

10KΩ

	VSS
	RESET
ST7	ISPCLK

ISPDATA

47KΩ

APPLICATION

5.5 MEMORY READ-OUT PROTECTION

The read-out protection is enabled through an option bit.

For FLASH devices, when this option is selected, the program and data stored in the FLASH memory are protected against read-out piracy (including a re-write protection). When this protection option is removed the entire FLASH program memory is first automatically erased. However, the E2PROM data memory (when available) can be protected only with ROM devices.

16/148

6 DATA EEPROM

6.1 INTRODUCTION

The Electrically Erasable Programmable Read Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter.

Figure 7. EEPROM Block Diagram

ST72334J/N, ST72314J/N, ST72124J

6.2 MAIN FEATURES

■Up to 16 Bytes programmed in the same cycle

■EEPROM mono-voltage (charge pump)

■Chained erase and programming cycles

■Internal control of the global programming cycle duration

■End of programming cycle interrupt flag

■WAIT mode management

FALLING

EEPROM INTERRUPT EDGE

DETECTOR

					HIGH VOLTAGE
						PUMP
EECSR	RESERVED			EEPROM
	0 0	0 0	IE	LAT	PGM
0
	ADDRESS		4		EEPROM
				ROW
	DECODER				MEMORY MATRIX
				DECODER
					(1 ROW = 16 x 8 BITS)
					128	128
				4	DATA	16 x 8 BITS
					MULTIPLEXER	DATA LATCHES
				4
	ADDRESS BUS				DATA BUS

17/148

ST72334J/N, ST72314J/N, ST72124J

DATA EEPROM (Cont'd)

6.3 MEMORY ACCESS

The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 8 describes these different memory access modes.

Read Operation (LAT=0)

The EEPROM can be read as a normal ROM location when the LAT bit of the EECSR register is cleared. In a read cycle, the byte to be accessed is put on the data bus in less than 1 CPU clock cycle. This means that reading data from EEPROM takes the same time as reading data from EPROM, but this memory cannot be used to execute machine code.

Write Operation (LAT=1)

To access the write mode, the LAT bit has to be set by software (the PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 16 data latches according to its address.

Figure 8. Data EEPROM Programming Flowchart

When PGM bit is set by the software, all the previous bytes written in the data latches (up to 16) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four Least Significant Bits of the address can change.

At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously, and an interrupt is generated if the IE bit is set. The Data EEPROM interrupt request is cleared by hardware when the Data EEPROM interrupt vector is fetched.

Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of LAT bit.

It is not possible to read the latched data. This note is ilustrated by the Figure 9.

	READ MODE		WRITE MODE
	LAT=0		LAT=1
	PGM=0		PGM=0
	READ BYTES	WRITE UP TO 16 BYTES
		IN EEPROM AREA
	IN EEPROM AREA
		(with the same 12 MSB of the address)
		START PROGRAMMING CYCLE
			LAT=1
		PGM=1 (set by software)
	INTERRUPT GENERATION
	IF IE=1	0	1
			LAT

CLEARED BY HARDWARE

18/148

ST72334J/N, ST72314J/N, ST72124J

DATA EEPROM (Cont'd)

6.4 POWER SAVING MODES Wait mode

The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller. The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode.

Halt mode

The DATA EEPROM immediatly enters HALT mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted.

6.5 ACCESS ERROR HANDLING

If a read access occurs while LAT=1, then the data bus will not be driven.

If a write access occurs while LAT=0, then the data on the bus will not be latched.

If a programming cycle is interrupted (by software/ RESET action), the memory data will not be guaranteed.

Figure 9. Data EEPROM Programming Cycle

READ OPERATION NOT POSSIBLE		READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE	WRITE CYCLE

WRITE OF

DATA LATCHES

tPROG

LAT

PGM

EEPROM INTERRUPT

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DATA EEPROM (Cont'd)

6.6 REGISTER DESCRIPTION CONTROL/STATUS REGISTER (CSR)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

Bit 1 = LAT Latch Access Transfer

This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if PGM bit is cleared.

0:Read mode

1:Write mode

0

0

0

0

0

IE LAT PGM

Bit 7:3 = Reserved, forced by hardware to 0.

Bit 2 = IE Interrupt enable

This bit is set and cleared by software. It enables the Data EEPROM interrupt capability when the PGM bit is cleared by hardware. The interrupt request is automatically cleared when the software enters the interrupt routine.

0:Interrupt disabled

1:Interrupt enabled

Bit 0 = PGM Programming control and status

This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is clearedby hardware and an interrupt is generated if the ITE bit is set.

0:Programming finished or not yet started

1:Programming cycle is in progress

Note: if the PGM bit is cleared during the programming cycle, the memory data is not guaranteed

Table 3. DATA EEPROM Register Map and Reset Values

	Address	Register	7	6	5	4	3	2	1	0
	(Hex.)	Label
	002Ch	EECSR						IE	RWM	PGM
		Reset Value	0	0	0	0	0	0	0	0

6.7 READ-OUT PROTECTION OPTION

The Data EEPROM can be optionally read-out protected in ST72334 ROM devices (see option

list on page 145). ST72C334 Flash devices do not have this protection option.

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7 CENTRAL PROCESSING UNIT

7.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

7.2 MAIN FEATURES

■63 basic instructions

■Fast 8-bit by 8-bit multiply

■17 main addressing modes

■Two 8-bit index registers

■16-bit stack pointer

■Low power modes

■Maskable hardware interrupts

■Non-maskable software interrupt

7.3 CPU REGISTERS

The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions.

Figure 10. CPU Registers

			7							0
			RESET VALUE = XXh
			7							0
			RESET VALUE = XXh
			7							0
			RESET VALUE = XXh
15	PCH	8	7			PCL				0
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
			7							0
			1	1	1	H	I	N	Z	C
	RESET VALUE = 1			1	1	X	1	X	X	X
15		8	7							0

RESET VALUE = STACK HIGHER ADDRESS

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

ACCUMULATOR

XINDEX REGISTER

YINDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

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ST72334J/N, ST72314J/N, ST72124J

CPU REGISTERS (Cont'd)

CONDITION CODE REGISTER (CC)

Read/Write

Reset Value: 111x1xxx

7							0
1	1	1	H	I	N	Z	C

The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.

0:No half carry has occurred.

1:A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 3 = I Interrupt mask.

This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.

0:Interrupts are enabled.

1:Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware when you enter it and reset by the IRET instruction at the end of the interrupt routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.

0:The result of the last operation is positive or null.

1:The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0:The result of the last operation is different from zero.

1:The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0:No overflow or underflow has occurred.

1:An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the ªbit test and branchº, shift and rotate instructions.

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ST72334J/N, ST72314J/N, ST72124J

CENTRAL PROCESSING UNIT (Cont'd)

Stack Pointer (SP)

Read/Write

Reset Value: 01 FFh

15							8
0	0	0	0	0	0	0	1
7							0
SP7	SP6	SP5	SP4	SP3	SP2	SP1	SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11).

Since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

Figure 11. Stack Manipulation Example

CALL	Interrupt	PUSH Y
Subroutine	Event
@ 0100h

			SP
		SP	Y
		CC	CC
		A	A
		X	X
	SP	PCH	PCH
		PCL	PCL
	PCH	PCH	PCH
	@ 01FFh PCL	PCL	PCL

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11.

±When an interrupt is received, the SP is decremented and the context is pushed on the stack.

±On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

POP Y	IRET	RET
		or RSP

SP

	CC
	A
	X
	PCH	SP
	PCL
	PCH	PCH
	PCL	SP
		PCL

Stack Higher Address = 01FFh Stack Lower Address = 0100h

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8 SUPPLY, RESET AND CLOCK MANAGEMENT

The ST72334J/N, ST72314J/N and ST72124J microcontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 12.

See Section 15 ºELECTRICAL CHARACTERISTICSº on page 105 for more details.

Main Features

■Supply Manager with main supply low voltage detection (LVD)

■Reset Sequence Manager (RSM)

■Multi-Oscillator (MO)

±4 Crystal/Ceramic resonator oscillators

±1 External RC oscillator

±1 Internal RC oscillator

■Clock Security System (CSS)

±Clock Filter

±Backup Safe Oscillator

Figure 12. Clock, Reset and Supply Block Diagram

CLOCK SECURITY SYSTE M (CSS)

OSC2	MULTI-	SAFE	fOSC	TO
	CLOCK			MAIN CLOCK
	OSCILLATOR
OSC1	FILTER	OSC		CONTROLLER
	(MO)

RESET SEQUENCE

RESET MANAGER FROM

(RSM)

WATCH DOG

PERIP HERAL

VDD	LOW VOLTAGE			LVD	CSS	WDG
	DETECTO R
VSS	(LVD)	CRSR 0	0	0 RF 0	IE	D RF

CSS INTER RUPT

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8.1 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.

The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when VDD is below:

±VIT+ when VDD is rising

±VIT- when VDD is falling

The LVD function is illustrated in the Figure 13.

Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes:

±under full software control

±in static safe reset

Figure 13. Low Voltage Detector vs Reset

VDD

VIT+

VIT-

ST72334J/N, ST72314J/N, ST72124J

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

Notes:

1.The LVD allows the device to be used without any external RESET circuitry.

2.Three different reference levels are selectable through the option byte according to the application requirement.

LVD application note

Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register.

This bit is set by hardware when a LVD reset is generated and cleared by software (writing zero).

Vhyst

RESET

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8.2 RESET SEQUENCE MANAGER (RSM)

8.2.1 Introduction

The reset sequence manager includes three RESET sources as shown in Figure 15:

■External RESET source pulse

■Internal LVD RESET (Low Voltage Detection)

■Internal WATCHDOG RESET

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases as shown in Figure 14:

■Delay depending on the RESET source

■4096 CPU clock cycle delay

■RESET vector fetch

Figure 15. Reset Block Diagram

VDD	fCPU

RON

RESET

The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state.

The RESET vector fetch phase duration is 2 clock cycles.

Figure 14. RESET Sequence Phases

RESET

	DELAY	INTERNAL RESET	FETCH
		4096 CLOCK CYCLES	VECTOR

INTERNAL

RESET

COUNTER

WATCHDOG RESET

LVD RESET

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RESET SEQUENCE MANAGER (Cont'd)

8.2.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details.

A RESET signal originating from an external

source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchro-

nous and therefore the MCU can enter reset state even in HALT mode.

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

Two RESET sequences can be associated with this RESET source: short or long external reset pulse (see Figure 16).

Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.

Figure 16. RESET Sequences

VDD

VIT+

VIT-

8.2.3 Internal Low Voltage Detection RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■Power-On RESET

■Voltage Drop RESET

The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or VDD<VIT- (falling edge) as shown in Figure 16.

The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.

8.2.4 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 16.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.

	LVD	SHORT EXT.	LONG EXT.		WATCHDOG
	RESET	RESET	RESET		RESET
RUN	RUN	RUN		RUN	RUN
	DELAY	DELAY	DELAY		DELAY
	tw(RSTL)out
	th(RSTL)in	th(RSTL)in			tw(RSTL)out

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (4096 TCP U)

FETCH VECTOR

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8.3 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by four different source types coming from the multioscillator block:

■an external source

■4 crystal or ceramic resonator oscillators

■an external RC oscillator

■an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configuration are shown in Table 4. Refer to the electrical characteristics section for more details.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption. In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

External RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an external resistor and an external capacitor. The frequency of the external RC oscillator (in the range of some MHz.) is fixed by the resistor and the capacitor values. Consequently in this MO mode, the accuracy of the clock is directly linked to the accuracy of the discrete components.

Internal RC Oscillator

The internal RC oscillator mode is based on the same principle as the external RC oscillator including the resistance and the capacitance of the device. This mode is the most cost effective one with the drawback of a lower frequency accuracy. Its frequency is in the range of several MHz.

In this mode, the two oscillator pins have to be tied to ground.

Table 4. ST7 Clock Sources

		Hardware Configur ation
	ClockExternal	ST7
		OSC1	OSC2
		EXTERNAL
	Resonators	SOURCE
		ST7
	Crystal/Ceramic	OSC1	OSC2
		CL1	CL2
		LOAD
		CAPACITORS
	OscillatorRC	ST7
		OSC1	OSC2
	External	REX	CEX
	OscillatorRCInternal	ST7
		OSC1	OSC2

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8.4 CLOCK SECURITY SYSTEM (CSS)

The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a clock filter control and an Internal safe oscillator. The CSS can be enabled or disabled by option byte.

8.4.1 Clock Filter Control

The clock filter is based on a clock frequency limitation function.

This filter function is able to detect and filter high frequency spikes on the ST7 main clock.

ST72334J/N, ST72314J/N, ST72124J

Limitation detection

The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the CRSR register. An interrupt can be generated if the CSSIE bit has been previously set.

These two bits are described in the CRSR register description.

8.4.3 Low Power Modes

Mode	Description

WAIT

No effect on CSS. CSS interrupt cause the device to exit from Wait mode.

If the oscillator is not working properly (e.g. working at a harmonic frequency of the resonator), the current active oscillator clock can be totally filtered, and then no clock signal is available for the ST7 from this oscillator anymore. If the original clock source recovers, the filtering is stopped automatically and the oscillator supplies the ST7 clock.

8.4.2 Safe Oscillator Control

The safe oscillator of the CSS block is a low frequency back-up clock source (see Figure 17).

If the clock signal disappears (due to a broken or disconnected resonator...) during a safe oscillator period, the safe oscillator delivers a low frequency clock signal which allows the ST7 to perform some rescue operations.

Automatically, the ST7 clock source switches back from the safe oscillator if the original clock source recovers.

The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until HALT mode is exited. The previous CSS

HALT

configuration resumes when the MCU is woken up by an interrupt with ªexit from HALT modeº capability or from the counter reset value when the MCU is woken up by a RESET.

8.4.4 Interrupts

The CSS interrupt event generates an interrupt if the corresponding Enable Control Bit (CSSIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

	Event	Enable	Exit	Exit
Interrupt Event		Control	from	from
	Flag	Bit	Wait	Halt
CSS event detection
(safe oscillator acti-	CSSD	CSSIE	Yes	No
vated as main clock)

Figure 17. Clock Filter Function and Safe Oscillator Function

CLOCK FILTER	FUNCTION
SAFE OSCILLATOR	FUNCTION

fOSC/2

fCPU

fOSC/2

fSFOSC

fCPU

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8.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION

Read/Write

Reset Value: 000x 000x (xxh)

	7							0
	0	0	0	LVD	0	CSS	CSS	WDG
				RF		IE	D	RF

Bit 7:5 = Reserved, always read as 0.

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last RESET was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by option byte, the LVDRF bit value is undefined.

Bit 3 = Reserved, always read as 0.

Bit 2 = CSSIE Clock security syst. interrupt enable

This bit enables the interrupt when a disturbance is detected by the clock security system (CSSD bit set). It is set and cleared by software.

0:Clock security system interrupt disabled

1:Clock security system interrupt enabled

Refer to Table 6, ªInterrupt Mapping,º on page 32 for more details on the CSS interrupt vector. When the CSS is disabled by option byte, the CSSIE bit has no effect.

Bit 1 = CSSD Clock security system detection

This bit indicates that the safe oscillator of the clock security system block has been selected by hardware due to a disturbance on the main clock

signal (fOSC). It is set by hardware and cleared by reading the CRSR register when the original oscil-

lator recovers.

0:Safe oscillator is not active

1:Safe oscillator has been activated

When the CSS is disabled by option byte, the CSSD bit value is forced to 0.

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last RESET was generated by the watchdog peripheral. It is set by hardware (Watchdog RESET) and cleared by software (writing zero) or an LVD RESET (to ensure a stable cleared state of the WDGRF flag when the CPU starts).

Combined with the LVDRF flag information, the flag description is given by the following table.

RESET Sources	LVDRF	WDGRF
External RESET pin	0	0
Watchdog	0	1
LVD	1	X

Application notes

The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure.

In this case, a watchdog reset can be detected by software while an external reset can not.

Table 5. Clock, Reset and Supply Register Map and Reset Values

	Address	Register	7	6	5	4	3	2	1	0
	(Hex.)	Label
	002Bh	CRSR				LVDRF		CFIE	CSSD	WDGRF
		Reset Value	0	0	0	x	0	0	0	x

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