SGS Thomson Microelectronics ST72F264G2M6, ST72F264G2B6, ST72264G2M6, ST72264G2B6, ST72264G2 Datasheet

ST72260G, ST72262G,

ST72264G

8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES

■Memories

–4 K or 8 Kbytes Program memory: ROM or Single voltage extended Flash (XFlash) with read-out protection write protection and InCircuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55°C.

–256 bytes RAM

■Clock, Reset and Supply Management

–Enhanced reset system

–Enhanced low voltage supply supervisor (LVD) with 3 programmable levels and auxiliary voltage detector (AVD) with interrupt capability for implementing safe power-down procedures

–Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock

–PLL for 2x frequency multiplication

–Clock-out capability

–4 Power Saving Modes: Halt, Active Halt,Wait and Slow

■Interrupt Management

–Nested interrupt controller

–10 interrupt vectors plus TRAP and RESET

–22 external interrupt lines (on 2 vectors)

■22 I/O Ports

–22 multifunctional bidirectional I/O lines

–20 alternate function lines

–8 high sink outputs

■4 Timers

–Main Clock Controller with Real time base and Clock-out capabilities

–Configurable watchdog timer

Device Summary

SDIP32

LFBGA 6x6mm

SO28

–Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes

■3 Communications Interfaces

–SPI synchronous serial interface

–I2C multimaster interface

–SCI asynchronous serial interface (LIN compatible)

■1 Analog peripheral

–10-bit ADC with 6 input channels

■Instruction Set

–8-bit data manipulation

–63 basic instructions

–17 main addressing modes

–8 x 8 unsigned multiply instruction

■Development Tools

–Full hardware/software development package

Features	ST72260G1	ST72262G1	ST72262G2	ST72264G1		ST72264G2
Program memory - bytes	4K	4K	8K	4K		8K
RAM (stack) - bytes			256	(128)
	Watchdog timer,	Watchdog timer, RTC			Watchdog timer, RTC
	RTC,
Peripherals		Two 16-bit timers,				Two 16-bit timers,
	Two16-bit timers,
		SPI, ADC			SPI, SCI, I2C, ADC
	SPI
Operating Supply			2.4 V to 5.5 V
CPU Frequency		Up to 8 MHz (with oscillator up to 16 MHz) PLL 4/8 Mhz
Operating Temperature			-40° C to +85° C				0° C to +70° C
Packages			SO28 / SDIP32				LFBGA
							Rev. 1.7
August 2003					1/171

1

Table of Contents

ST72260G, ST72262G,

ST72264G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
5.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
5.2	MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
5.3	CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

33

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.5 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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9.8	I/O PORT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 43
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		45
10.1	I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
10.2	I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
10.3	MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		48
11.1	WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
11.2	MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC) . . . . . . . . . . . . .	53
11.3	16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
11.4	SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	74
11.5	SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	85
11.6	I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	99
11.7	10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	112
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		116
12.1	CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	116
12.2	INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	119
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		122

13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 149 13.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		154
14.1	PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	154
14.2	THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	155
14.3	SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . .	156
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . .		157

15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 159 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

165

ERRATA SHEET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

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17 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		166
18 REFERENCE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		166
19 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		166
19.1	EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	166
19.2	I/O PORT B AND C CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	166
19.3	16-BIT TIMER PWM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	167
19.4	SPI MULTIMASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	167
19.5	MINIMUM OPERATING VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	167
19.6	CSS FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	167
19.7	INTERNAL AND EXTERNAL RC OSCILLATOR WITH LVD . . . . . . . . . . . . . . . . . . . .	167
19.8	EXTERNAL CLOCK WITH PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	167
19.9	HALT MODE POWER CONSUMPTION WITH ADC ON . . . . . . . . . . . . . . . . . . . . . . .	168
19.10 ACTIVE HALT WAKE-UP BY EXTERNAL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . .		168
19.11 A/D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . .		168
19.12 NEGATIVE INJECTION IMPACT ON ADC ACCURACY . . . . . . . . . . . . . . . . . . . . . . .		168
19.13	ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	168
19.14 FUNCTIONAL EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		169
20 DEVICE MARKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		169
21 ERRATA SHEET REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		170

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet

Please note that an errata sheet can be found at the end of this document on page 166.

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1 INTRODUCTION

The ST72260G, ST72262G and ST72264G devices are members of the ST7 microcontroller family. They can be grouped as follows :

–ST72264G devices are designed for mid-range applications with ADC, I2C and SCI interface capabilities.

–ST72262G devices target the same range of applications but without I2C interface or SCI.

–ST72260G devices are for applications that do not need ADC, I2C peripherals or SCI.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set.

The ST72F260G, ST72F262G, and ST72F264G versions feature single-voltage FLASH memory

with byte-by-byte In-Circuit Programming (ICP) capabilities.

Under software control, all devices can be placed in WAIT, SLOW, Active-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

For easy reference, all parametric data is located in Section 13 on page 122.

Figure 1. General Block Diagram

		Internal
OSC1	MULTI OSC	CLOCK		I2C*
OSC2	+
	CLOCK FILTER			SCI*
	MCC/RTC				PA7:0
				PORT A	(8 bits)
	LVD
VDD	POWER			ICD
VSS	SUPPLY		ADDRESS
				SPI
RESET	CONTROL			PORT B	PB7:0
					(8 bits)
			AND
	8-BIT CORE
			BUS DATA
	ALU			16-BIT TIMER A
	PROGRAM			PORT C
					PC5:0
	MEMORY
					(6 bits)
	(4 or 8K Bytes)
				10-BIT ADC*

RAM								16-BIT TIMER B
(256 Bytes)
								WATCHDOG

*Not available on some devices, see device summary on page 1.

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2 PIN DESCRIPTION

Figure 2. 28-Pin SO Package Pinout

		RESET								1					28			VDD
			OSC1							2					27			VSS
			OSC2							3					26			ICCSEL
																		PA0 (HS)/ICCCLK
	SS/PB7									4					25
SCK/PB6										5					24			PA1 (HS)/ICCDATA
MISO/PB5										6					23			PA2 (HS)
MOSI/PB4										7			ei1	ei0	22			PA3 (HS)
OCMP2_A/PB3										8					21			PA4 (HS)/SCLI3
ICAP2_A/PB2										9					20			PA5(HS)/RDI3
OCMP1_A/PB1										10					19			PA6 (HS)/SDAI3
ICAP1_A/PB0										11					18			PA7 (HS)/TDO3
AIN5/EXTCLK_A/PC5										12					17			PC0/ICAP1_B/AIN02
AIN42/OCMP2_B/PC4										13			ei0 or ei11		16			PC1/OCMP1_B/AIN12
AIN32/ICAP2_B/PC3										14					15			PC2/MCO/AIN22
1 Configurable by option byte																		(HS)	20mA high sink capability
2 Alternate function not available on ST72260																		eiX	associated external interrupt vector
3 Alternate function not available on ST72260 and ST72262
Figure 3. 32-Pin SDIP Package Pinout
																		VDD
			RESET									1			32
			OSC1									2			31			VSS
			OSC2									3			30			ICCSEL
																		PA0 (HS)/ICCCLK
			SS/PB7									4			29
SCK/PB6												5	ei1	ei0	28			PA1 (HS)/ICCDATA
MISO/PB5												6			27			PA2 (HS)
MOSI/PB4												7			26			PA3 (HS)
					NC							8			25			NC
					NC							9			24			NC
OCMP2_A/PB3												10			23			PA4 (HS)/SCLI3
ICAP2_A/PB2												11	ei1	ei0	22			PA5 (HS)/RDI3
OCMP1_A/PB1												12			21			PA6 (HSI/SDAI3
ICAP1_A/PB0												13			20			PA7 (HS)/TDO3
AIN52/EXTCLK_A/PC5												14			19			PC0/ICAP1_B/AIN02
AIN42/OCMP2_B/PC4												15	ei0 or ei11		18			PC1/OCMP1_B/AIN12
																		PC2/MCO/AIN22
AIN32/ICAP2_B/PC3												16			17
1 Configurable by option byte																		(HS)	20mA high sink capability
2 Alternate function not available on ST72260
3 Alternate function not available on ST72260 and ST72262																		eiX	associated external interrupt vector

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Figure 4. TFBGA Package Pinout (view through package)

1

2

3

4

5

6

A

B

C

D

E

F

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PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to Section 13 "ELECTRICAL CHARACTERISTICS" on page 122.

Legend / Abbreviations for Table 1:

Type:		I = input, O = output, S = supply
Input level:		A = Dedicated analog input
In/Output level:		CT= CMOS 0.3 VDD/0.7 VDD with input trigger
Output level:		HS = 20 mA high sink (on N-buffer only)
Port and control configuration:
–	Input:	float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
–	Output:	OD = open drain 2), PP = push-pull

Refer to Section 9 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.

Table 1. Device Pin Description

Pin n°

Level

Port / Control

Main

SDIP32

SO28

BGA

Type

Input

Output

float

wpu

int

ana

OD

PP

Function

Pin Name

Input

Output

Alternate Function

(after

reset)

Top priority non maskable interrupt (ac-

1

1

A3

RESET

I/O

CT

X

X

tive low)

OSC1 3)

External clock input or Resonator oscilla-

2

2

C4

I

tor inverter input or resistor input for RC

oscillator

3

3

B3

OSC2 3)

O

Resonator oscillator inverter output or ca-

pacitor input for RC oscillator

4

4

A2

I/O

CT

X

ei1

X

X

Port B7

SPI Slave Select (active low)

PB7/SS

5

5

A1

PB6/SCK

I/O

CT

X

ei1

X

X

Port B6

SPI Serial Clock

6

6

B1

PB5/MISO

I/O

CT

X

ei1

X

X

Port B5

SPI Master In/ Slave Out Data

7

7

B2

PB4/MOSI

I/O

CT

X

ei1

X

X

Port B4

SPI Master Out / Slave In Data

8

C1

NC

9

C2

NC

Not Connected

D1

NC

10

8

C3

PB3/OCMP2_A

I/O

CT

X

ei1

X

X

Port B3

Timer A Output Compare 2

11

9

D2

PB2/ICAP2_A

I/O

CT

X

ei1

X

X

Port B2

Timer A Input Capture 2

12

10

E1

PB1 /OCMP1_A

I/O

CT

X

ei1

X

X

Port B1

Timer A Output Compare 1

13

11

F1

PB0 /ICAP1_A

I/O

CT

X

ei1

X

X

Port B0

Timer A Input Capture 1

14

12

F2

PC5/EXTCLK_A/AIN5

I/O

CT

X

ei0/ei1

X

X

X

Port C5

Timer A Input Clock or ADC

Analog Input 5

15

13

E2

PC4/OCMP2_B/AIN4

I/O

CT

X

ei0/ei1

X

X

X

Port C4

Timer B Output Compare 2 or

ADC Analog Input 4

16

14

F3

PC3/ ICAP2_B/AIN3

I/O

CT

X

ei0/ei1

X

X

X

Port C3

Timer B Input Capture 2 or

ADC Analog Input 3

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ST72260G, ST72262G, ST72264G

Pin n°

Level

Port / Control

Main

SDIP32

SO28

BGA

Type

Input

Output

float

wpu

int

ana

OD

PP

Function

Pin Name

Input

Output

Alternate Function

(after

reset)

17

15

E3

PC2/MCO/AIN2

I/O

CT

X

ei0/ei1

X

X

X

Port C2

Main clock output (fCPU) or

ADC Analog Input 2

18

16

F4

PC1/OCMP1_B/AIN1

I/O

CT

X

ei0/ei1

X

X

X

Port C1

Timer B Output Compare 1 or

ADC Analog Input 1

19

17

D3

PC0/ICAP1_B/AIN0

I/O

CT

X

ei0/ei1

X

X

X

Port C0

Timer B Input Capture 1 or

ADC Analog Input 0

20

18

E4

PA7/TDO

I/O

CT

HS

X

ei0

X

X

Port A7

SCI output

21

19

F5

PA6/SDAI

I/O

CT

HS

X

ei0

T

Port A6

I2C DATA

22

20

F6

PA5 /RDI

I/O

CT

HS

X

ei0

X

X

Port A5

SCI input

23

21

E6

PA4/SCLI

I/O

CT

HS

X

ei0

T

Port A4

I2C CLOCK

24

E5

NC

25

D6

NC

Not Connected

D5

NC

26

22

C6

PA3

I/O

CT

HS

X

ei0

X

X

Port A3

27

23

D4

PA2

I/O

CT

HS

X

ei0

X

X

Port A2

C5

NC

Not Connected

B6

NC

28

24

A6

PA1/ICCDATA

I/O

CT

HS

X

ei0

X

X

Port A1

In Circuit Communication Data

29

25

A5

PA0/ICCCLK

I/O

CT

HS

X

ei0

X

X

Port A0

In Circuit Communication

Clock

30

26

B5

ICCSEL

I

CT

X

ICC mode pin, must be tied low

31

27

A4

VSS

S

Ground

32

28

B4

VDD

S

Main power supply

Notes:

1.In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is a pull-up interrupt input, otherwise the configuration is a floating interrupt input. Port C is mapped to ei0 or ei1 by option byte.

2.In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 9 "I/O PORTS" on page 38 for more details.

3.OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see Section 2 "PIN DESCRIPTION" on page 6 and Section 6.2 "MULTI-OSCILLA- TOR (MO)" on page 21 for more details.

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ST72260G, ST72262G, ST72264G

3 REGISTER & MEMORY MAP

As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register location, 256 bytes of RAM and up to 8 Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh.

The highest address bytes contain the user reset and interrupt vectors.

The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7 ad-

dressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).

The size of Flash Sector 0 and other device options are configurable by Option byte (refer to Section 15.1 on page 157).

IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the device.

Figure 5. Memory Map

0000h

HW Registers

(see Table 2)

0080h

007Fh

Short Addressing RAM

0080h

Zero page

RAM

00FFh

(128 Bytes)

(256 Bytes)

0100h

Stack or

017Fh

16-bit Addressing RAM

(128 Bytes)

0180h

017Fh

Reserved

8K FLASH

PROGRAM MEMORY

DFFFh

E000h

4 Kbytes

E000h

Program Memory

EFFFh

SECTOR 1

F000h

4 Kbytes

(4K, 8 KBytes)

FFDFh

FFFFh

SECTOR 0

FFE0h

Interrupt & Reset Vectors

FFFFh

(see Table 5 on page 32)

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ST72260G, ST72262G, ST72264G

Table 2. Hardware Register Map

	Address	Block	Register	Register Name	Reset	Remarks
			Label		Status
	0000h		PCDR	Port C Data Register	xx000000h1)	R/W 2)
	0001h	Port C	PCDDR	Port C Data Direction Register	00h	R/W 2)
	0002h		PCOR	Port C Option Register	00h	R/W 2)
	0003h			Reserved (1 Byte)
	0004h		PBDR	Port B Data Register	00h 1)	R/W
	0005h	Port B	PBDDR	Port B Data Direction Register	00h	R/W
	0006h		PBOR	Port B Option Register	00h	R/W.
	0007h			Reserved (1 Byte)
	0008h		PADR	Port A Data Register	00h 1)	R/W
	0009h	Port A	PADDR	Port A Data Direction Register	00h	R/W
	000Ah		PAOR	Port A Option Register	00h	R/W
	000Bh
	to			Reserved (17 Bytes)
	001Bh
	001Ch		ISPR0	Interrupt software priority register0	FFh	R/W
	001Dh	ITC	ISPR1	Interrupt software priority register1	FFh	R/W
	001Eh		ISPR2	Interrupt software priority register2	FFh	R/W
	001Fh		ISPR3	Interrupt software priority register3	FFh	R/W
	0020h		MISCR1	Miscellanous register 1	00h	R/W
	0021h		SPIDR	SPI Data I/O Register	xxh	R/W
	0022h	SPI	SPICR	SPI Control Register	0xh	R/W
	0023h		SPICSR	SPI Status Register	00h	R/W
	0024h	WATCHDOG	WDGCR	Watchdog Control Register	7Fh	R/W
	0025h		SICSR	System Integrity Control / Status Register	000x 000x	R/W
	0026h	MCC	MCCSR	Main Clock Control / Status Register	00h	R/W
	0027h			Reserved (1 Byte)
	0028h		I2CCR	I2C Control Register	00h	R/W
	0029h		I2CSR1	I2C Status Register 1	00h	Read Only
	002Ah		I2CSR2	I2C Status Register 2	00h	Read Only
	002Bh	I2C	I2CCCR	I2C Clock Control Register	00h	R/W
	002Ch		I2COAR1	I2C Own Address Register 1	00h	R/W
	002Dh		I2COAR2	I2C Own Address Register2	40h	R/W
	002Eh		I2CDR	I2C Data Register	00h	R/W
	002Fh			Reserved (2 Bytes)
	0030h

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ST72260G, ST72262G, ST72264G

	Address	Block	Register	Register Name	Reset	Remarks
			Label		Status
	0031h		TACR2	Timer A Control Register 2	00h	R/W
	0032h		TACR1	Timer A Control Register 1	00h	R/W
	0033h		TASCSR	Timer A Control/Status Register	xxh	R/W
	0034h		TAIC1HR	Timer A Input Capture 1 High Register	xxh	Read Only
	0035h		TAIC1LR	Timer A Input Capture 1 Low Register	xxh	Read Only
	0036h		TAOC1HR	Timer A Output Compare 1 High Register	80h	R/W
	0037h		TAOC1LR	Timer A Output Compare 1 Low Register	00h	R/W
	0038h	TIMER A	TACHR	Timer A Counter High Register	FFh	Read Only
	0039h		TACLR	Timer A Counter Low Register	FCh	Read Only
	003Ah		TAACHR	Timer A Alternate Counter High Register	FFh	Read Only
	003Bh		TAACLR	Timer A Alternate Counter Low Register	FCh	Read Only
	003Ch		TAIC2HR	Timer A Input Capture 2 High Register	xxh	Read Only
	003Dh		TAIC2LR	Timer A Input Capture 2 Low Register	xxh	Read Only
	003Eh		TAOC2HR	Timer A Output Compare 2 High Register	80h	R/W
	003Fh		TAOC2LR	Timer A Output Compare 2 Low Register	00h	R/W
	0040h		MISCR2	Miscellanous register 2	00h	R/W
	0041h		TBCR2	Timer B Control Register 2	00h	R/W
	0042h		TBCR1	Timer B Control Register 1	00h	R/W
	0043h		TBSCSR	Timer B Control/Status Register	xxh	R/W
	0044h		TBIC1HR	Timer B Input Capture 1 High Register	xxh	Read Only
	0045h		TBIC1LR	Timer B Input Capture 1 Low Register	xxh	Read Only
	0046h		TBOC1HR	Timer B Output Compare 1 High Register	80h	R/W
	0047h		TBOC1LR	Timer B Output Compare 1 Low Register	00h	R/W
	0048h	TIMER B	TBCHR	Timer B Counter High Register	FFh	Read Only
	0049h		TBCLR	Timer B Counter Low Register	FCh	Read Only
	004Ah		TBACHR	Timer B Alternate Counter High Register	FFh	Read Only
	004Bh		TBACLR	Timer B Alternate Counter Low Register	FCh	Read Only
	004Ch		TBIC2HR	Timer B Input Capture 2 High Register	xxh	Read Only
	004Dh		TBIC2LR	Timer B Input Capture 2 Low Register	xxh	Read Only
	004Eh		TBOC2HR	Timer B Output Compare 2 High Register	80h	R/W
	004Fh		TBOC2LR	Timer B Output Compare 2 Low Register	00h	R/W
	0050h		SCISR	SCI Status Register	C0h	Read Only
	0051h		SCIDR	SCI Data Register	xxh	R/W
	0052h		SCIBRR	SCI Baud Rate Register	00h	R/W
	0053h	SCI	SCICR1	SCI Control Register1	x000 0000h	R/W
	0054h		SCICR2	SCI Control Register2	00h	R/W
	0055h		SCIERPR	SCI Extended Receive Prescaler Register	00h	R/W
	0056h		SCIETPR	SCI Extended Transmit Prescaler Register	00h	R/W
	0057h
	to			Reserved (24 Bytes)
	006Eh
	006Fh		ADCDRL	Data Register Low3)	00h	Read Only
	0070h	ADC	ADCDRH	Data Register High3)	00h	Read Only
	0071h		ADCCSR	Control/Status Register	00h	R/W
	0072h	FLASH	FCSR	Flash Control Register	00h	R/W
	0073h
	to			Reserved (13 Bytes)
	007Fh

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ST72260G, ST72262G, ST72264G

Legend: x=Undefined, R/W=Read/Write

Notes:

1.The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

2.The bits associated with unavailable pins must always keep their reset value.

3.For compatibility with the ST72C254, the ADCDRL and ADCDRH data registers are located with the LSB on the lower address (6Fh) and the MSB on the higher address (70h). As this scheme is not little Endian, the ADC data registers cannot be treated by C programs as an integer, but have to be treated as two char registers.

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ST72260G, ST72262G, ST72264G

4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming.

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■ICP (In-Circuit Programming)

■IAP (In-Application Programming)

■ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM

■Sector 0 size configurable by option byte

■Read-out and write protection against piracy

4.3 PROGRAMMING MODES

The ST7 can be programmed in three different ways:

–Insertion in a programming tool. In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased.

–In-Circuit Programming. In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board.

–In-Application Programming. In this mode, sector 1 can be programmed or erased without removing the device from the application

14/171

board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

–Download ICP Driver code in RAM from the ICCDATA pin

–Execute ICP Driver code in RAM to program the FLASH memory

Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.)

IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

ST72260G, ST72262G, ST72264G

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC interface

ICP needs a minimum of 4 and up to 7 pins to be connected to the programming tool. These pins are:

–RESET: device reset

–VSS: device power supply ground

–ICCCLK: ICC output serial clock pin

–ICCDATA: ICC input serial data pin

–ICCSEL: ICC selection (not required on devices without ICCSEL pin)

–OSC1: main clock input for external source (not required on devices without OSC1/OSC2 pins)

–VDD: application board power supply (optional, see Note 3)

Notes:

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming

Figure 6. Typical ICC Interface

Tool documentation for recommended resistor values.

2.During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3.The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4.Pin 9 has to be connected to the OSC1 pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with mul- ti-oscillator capability need to have OSC2 grounded in this case.

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

OPTIONAL

(See Note 3)

APPLICATION CL2

POWER SUPPLY

VDD		OSC2

OSC1

ICC CONNECTOR

HE10 CONNECTOR TYPE

OPTIONAL

APPLICATION BOARD

(See Note 4)

9

7

5

3

1

10

8

6

4

2

APPLICATION

RESET SOURCE

10kΩ

See Note 2

CL1

APPLICATION

See Note 1

I/O

ST7

VSS

ICCSEL

RESET

ICCCLK

ICCDATA

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ST72260G, ST72262G, ST72264G

FLASH PROGRAM MEMORY (Cont’d)

4.5 Memory Protection

There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually.

4.5.1 Read out Protection

Read out protection, when selected, makes it impossible to extract the memory content from the microcontroller, thus preventing piracy.

In flash devices, this protection is removed by reprogramming the option. In this case the program memory is automatically erased and the device can be reprogrammed.

Read-out protection selection depends on the device type:

–In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

–In ROM devices it is enabled by mask option specified in the Option List.

4.5.2 Flash Write/Erase Protection

Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content.

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Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable.

Write/erase protection is enabled through the FMP_W bit in the option byte.

4.6 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h)

2nd RASS Key: 1010 1110 (AEh)

7					0
0	0	0	0	0	OPT	LAT	PGM

Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations. For details on XFlash programming, refer to the ST7 Flash Programming Reference Manual.

When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

ST72260G, ST72262G, ST72264G

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■Enable executing 63 basic instructions

■Fast 8-bit by 8-bit multiply

■17 main addressing modes (with indirect addressing mode)

■Two 8-bit index registers

■16-bit stack pointer

■Low power HALT and WAIT modes

■Priority maskable hardware interrupts

■Non-maskable software/hardware interrupts

5.3 CPU REGISTERS

The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

Figure 7. CPU Registers

										7										0
																							ACCUMULATOR
												RESET VALUE = XXh
										7										0
																							X INDEX REGISTER
											RESET VALUE = XXh
										7										0
																							Y INDEX REGISTER
											RESET VALUE = XXh
					PCH			8			7				PCL					0			PROGRAM COUNTER
	15
	RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
										7										0
												1	1	I1	H	I0	N		Z	C			CONDITION CODE REGISTER
				RESET VALUE = 1									1	1	X	1	X		X	X
		15						8												0			STACK POINTER
											7
RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

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ST72260G, ST72262G, ST72264G

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write

Reset Value: 111x1xxx

7							0
1	1	I1	H	I0	N	Z	C

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.

0:No half carry has occurred.

1:A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the result 7th bit.

0:The result of the last operation is positive or null.

1:The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

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Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0:The result of the last operation is different from zero.

1:The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0:No overflow or underflow has occurred.

1:An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt

The combination of the I1 and I0 bits gives the current interrupt software priority.

Interrupt Software Priority		I1	I0
Level 0	(main)	1	0
Level 1		0	1
Level 2		0	0
Level 3	(= interrupt disable)	1	1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

ST72260G, ST72262G, ST72264G

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write

Reset Value: 01 7Fh

15							8
0	0	0	0	0	0	0	1
7							0
SP7	SP6	SP5	SP4	SP3	SP2	SP1	SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8).

Since the stack is 128 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8

–When an interrupt is received, the SP is decremented and the context is pushed on the stack.

–On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

Figure 8. Stack Manipulation Example

		CALL	Interrupt	PUSH Y	POP Y	IRET	RET
	Subroutine		Event				or RSP
	@ 0100h
			SP
			SP	Y	SP
			CC	CC	CC
			A	A	A
			X	X	X
	SP		PCH	PCH	PCH	SP
			PCL	PCL	PCL
		PCH	PCH	PCH	PCH	PCH	SP
	@ 017Fh	PCL	PCL	PCL	PCL	PCL
		Stack Higher Address = 017Fh
		Stack Lower Address = 0100h
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6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 10.

For more details, refer to dedicated parametric section.

Main Features

■Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator)

■Reset Sequence Manager (RSM)

■Multi-Oscillator Clock Management (MO)

–4 Crystal/Ceramic resonator oscillators

–1 Internal RC oscillator

■System Integrity Management (SI)

–Main supply Low Voltage Detector (LVD)

–Auxiliary Voltage Detector (AVD) with interrupt capability for monitoring the main supply

–Clock Security System (CSS) with Clock Filter and Backup Safe Oscillator (enabled by option byte)

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the 2 to 4 MHz range, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2.

Caution: The PLL is not recommended for applications where timing accuracy is required. See “PLL Characteristics” on page 134.

Figure 9. PLL Block Diagram

fOSC			PLL x 2		0			fOSC2
			/ 2		1

PLL OPTION BIT

Figure 10. Clock, Reset and Supply Block Diagram

SYSTEM INTEGRITY MANAGEMENT

CLOCK SECURITY SYSTEM

(CSS)

OSC2

MULTI-

fOSC

PLL

fOSC2

CLOCK

SAFE

fOSC2

MAIN CLOCK

fCPU

CONTROLLER

OSCILLATOR

(option)

OSC1

FILTER

OSC

WITH REALTIME

(MO)

CLOCK (MCC/RTC)

RESET SEQUENCE

AVD Interrupt Request

WATCHDOG

RESET

MANAGER

SICSR

TIMER (WDG)

(RSM)

0

AVD AVD LVD

0

CSS CSS WDG

IE

F

RF

IE

D

RF

CSS Interrupt Request

LOW VOLTAGE

VSS

DETECTOR

VDD

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

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6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by four different source types coming from the multioscillator block:

■an external source

■5 crystal or ceramic resonator oscillators

■an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 3. Refer to the electrical characteristics section for more details.

Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effects Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 5 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 15.1 on page 157 for more details on the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing.

In this mode, the two oscillator pins have to be tied to ground.

Table 3. ST7 Clock Sources

	Hardware Configuration
External Clock	ST7
	OSC1	OSC2
	EXTERNAL
	SOURCE
Resonators	ST7
	OSC1	OSC2
Crystal/Ceramic	CL1	CL2
	LOAD
	CAPACITORS
Internal RC Oscillator	ST7
	OSC1	OSC2

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6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

The reset sequence manager includes three RESET sources as shown in Figure 12:

■External RESET source pulse

■Internal LVD RESET (Low Voltage Detection)

■Internal WATCHDOG RESET

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases as shown in Figure 11:

■Active Phase depending on the RESET source

■4096 CPU clock cycle delay (selected by option byte)

■RESET vector fetch

The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application.

Figure 12. Reset Block Diagram

The RESET vector fetch phase duration is 2 clock cycles.

Figure 11. RESET Sequence Phases

RESET

	Active Phase	INTERNAL RESET	FETCH
		4096 CLOCK CYCLES	VECTOR

6.3.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A RESET signal originating from an external

source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 13). This de-

tection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

		VDD
		RON
	RESET	Filter	INTERNAL
			RESET
		PULSE	WATCHDOG RESET
		GENERATOR	LVD RESET

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RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

6.3.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency.

A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin.

6.3.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■Power-On RESET

■Voltage Drop RESET

The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or VDD<VIT- (falling edge) as shown in Figure 13.

The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 13.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.

Figure 13. RESET Sequences

VDD

VIT+(LVD)

VIT-(LVD)

LVD	EXTERNAL	WATCHDOG
RESET	RESET	RESET

RUN		RUN	RUN	RUN
	ACTIVE PHASE	ACTIVE		ACTIVE
		PHASE		PHASE

th(RSTL)in							tw(RSTL)out

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (4096 TCPU)

VECTOR FETCH

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6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains group the Low voltage Detector (LVD), Auxiliary Voltage Detector (AVD) and Clock Security System (CSS) functions. It is managed by the SICSR register.

6.4.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.

The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when VDD is below:

–VIT+ when VDD is rising

–VIT- when VDD is falling

The voltage threshold can be configured by option byte to be low, medium or high.

Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes:

–under full software control

–in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

Notes:

The LVD allows the device to be used without any external RESET circuitry.

The LVD function is illustrated in Figure 14.

The LVD is an optional function which can be selected by option byte.

Figure 14. Low Voltage Detector vs Reset

VDD

Vhys

VIT+

VIT-

RESET

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on

an analog comparison between a VIT- and VIT+ reference value and the VDD main supply. The VIT-

reference value for falling voltage is lower than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis).

The output of the AVD comparator is directly readable by the application software through a real time status bit (VDF) in the SICSR register. This bit is read only.

Caution: The AVD functions only if the LVD is enabled through the option byte.

6.4.2.1 Monitoring the VDD Main Supply

The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see Section 15.1 on page 157).

If the AVD interrupt is enabled, an interrupt is gen-

erated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles).

Figure 15. Using the AVD to Monitor VDD

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 15.

The interrupt on the rising edge is used to inform the application that the VDD warning state is over.

If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached.

If trv is greater than 256 or 4096 cycles then:

– If the AVD interrupt is enabled before the

VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE

bit is set, and the second when the threshold is reached.

–If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD interrupt will occur.

VDD	Early Warning Interrupt

(Power has dropped, MCU not not yet in reset)

Vhyst

VIT+(AVD)

VIT-(AVD)

VIT+(LVD)

VIT-(LVD)

trv VOLTAGE RISE TIME

AVDF bit

0

1

RESET VALUE

1

0

AVD INTERRUPT

REQUEST

IF AVDIE bit = 1

INTERRUPT PROCESS

INTERRUPT PROCESS

LVD RESET

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.3 Clock Security System (CSS)

The Clock Security System (CSS) protects the ST7 against breakdowns, spikes and overfrequencies occurring on the main clock source (fOSC). It is based on a clock filter and a clock detection control with an internal safe oscillator (fSFOSC).

6.4.3.1 Clock Filter Control

The PLL has an integrated glitch filtering capability making it possible to protect the internal clock from overfrequencies created by individual spikes. This feature is available only when the PLL is enabled. If glitches occur on fOSC (for example, due to loose connection or noise), the CSS filters these automatically, so the internal CPU frequency (fCPU) continues deliver a glitch-free signal (see Figure 16).

6.4.3.2 Clock detection Control

If the clock signal disappears (due to a broken or disconnected resonator...), the safe oscillator de-

livers a low frequency clock signal (fSFOSC) which allows the ST7 to perform some rescue opera-

tions.

Automatically, the ST7 clock source switches back

from the safe oscillator (fSFOSC) if the main clock source (fOSC) recovers.

When the internal clock (fCPU) is driven by the safe

oscillator (fSFOSC), the application software is notified by hardware setting the CSSD bit in the SIC-

SR register. An interrupt can be generated if the

CSSIE bit has been previously set.

These two bits are described in the SICSR register description.

6.4.4 Low Power Modes

Mode	Description

WAIT

No effect on SI. CSS and AVD interrupts cause the device to exit from Wait mode.

The SICSR register is frozen.

The CSS (including the safe oscillator) is disabled until HALT mode is exited. The

HALT

previous CSS configuration resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

6.4.4.1 Interrupts

The CSS or AVD interrupt events generate an interrupt if the corresponding Enable Control Bit (CSSIE or AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

	Event	Enable	Exit	Exit
Interrupt Event		Control	from	from
	Flag	Bit	Wait	Halt
CSS event detection
(safe oscillator acti-	CSSD	CSSIE	Yes	No
vated as main clock)
AVD event	AVDF	AVDIE	Yes	No

Figure 16. Clock Filter Function

	Clock Filter Function
	PLL ON	fOSC2
		fCPU
	Clock Detection Function
		fOSC2
		fSFOSC
		fCPU

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.5 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read/Write

Reset Value: 000x 000x (00h)

	7							0
	0	AVD	AVD	LVD	0	CSS	CSS	WDG
		IE	F	RF		IE	D	RF

Bit 7 = Reserved, always read as 0.

Bit 6 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine.

0:AVD interrupt disabled

1:AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value.

0:VDD over VIT+(AVD) threshold

1:VDD under VIT-(AVD) threshold

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.

bit set). It is set and cleared by software.

0:Clock security system interrupt disabled

1:Clock security system interrupt enabled

When the CSS is disabled by OPTION BYTE, the CSSIE bit has no effect.

Bit 1 = CSSD Clock security system detection

This bit indicates that the safe oscillator of the Clock Security System block has been selected by hardware due to a disturbance on the main clock

signal (fOSC). It is set by hardware and cleared by reading the SICSR register when the original oscil-

lator recovers.

0:Safe oscillator is not active

1:Safe oscillator has been activated

When the CSS is disabled by OPTION BYTE, the CSSD bit value is forced to 0.

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).

Combined with the LVDRF flag information, the flag description is given by the following table.

RESET Sources			LVDRF	WDGRF
External	RESET	pin	0	0
Watchdog			0	1
LVD			1	X

Application Notes

Bit 3 = Reserved, must be kept cleared.

Bit 2 = CSSIE Clock security syst. interrupt enable

This bit enables the interrupt when a disturbance is detected by the Clock Security System (CSSD

The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.

	Address	Register	7	6	5	4	3	2	1	0
	(Hex.)	Label
	0025h	SICSR		AVDIE	AVDF	LVDRF		CSSIE	CSSD	WDGRF
		Reset Value	0	0	0	x	0	0	0	x

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7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management provides the following features:

■Hardware interrupts

■Software interrupt (TRAP)

■Nested or concurrent interrupt management with flexible interrupt priority and level management:

–Up to 4 software programmable nesting levels

–Up to 16 interrupt vectors fixed by hardware

–2 non-maskable events: RESET and TRAP This interrupt management is based on:

–Bit 5 and bit 3 of the CPU CC register (I1:0),

–Interrupt software priority registers (ISPRx),

–Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 4). The processing flow is shown in Figure 17

When an interrupt request has to be serviced:

–Normal processing is suspended at the end of the current instruction execution.

–The PC, X, A and CC registers are saved onto the stack.

–I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector.

–The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to “Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.

Table 4. Interrupt Software Priority Levels

Interrupt software priority		Level		I1	I0
Level 0	(main)	Low		1	0
Level 1				0	1
Level 2		High		0	0
Level 3	(= interrupt disable)			1	1

Figure 17. Interrupt Processing Flowchart

RESET	PENDING	Y
	INTERRUPT
	N	Interrupt has the same or a
		lower software priority
		than current one	I1:0
	FETCH NEXT	THE INTERRUPT
	INSTRUCTION	STAYS PENDING
	Y	Interrupt hashighera	softwarepriority than currentone
	“IRET”
	N
RESTORE PC, X, A, CC	EXECUTE
FROM STACK	INSTRUCTION	STACK PC, X, A, CC
		LOAD I1:0 FROM INTERRUPT SW REG.
		LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont’d)

Servicing Pending Interrupts

As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process:

–the highest software priority interrupt is serviced,

–if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first.

Figure 18 describes this decision process.

Figure 18. Priority Decision Process

	PENDING
	INTERRUPTS
Same	SOFTWARE	Different
	PRIORITY
	HIGHEST SOFTWARE
	PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.

Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt.

Note 2: RESET and TRAP are non-maskable and they can be considered as having the highest software priority in the decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET and TRAP) and the maskable type (external or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 17). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit HALT mode.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart on Figure 17 as a TLI.

■ RESET

The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority.

See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.

■ External Interrupts

External interrupts allow the processor to exit from HALT low power mode.

External interrupt sensitivity is software selectable through the Miscellaneous registers (MISCRx). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.

If several input pins of a group connected to the same interrupt vector request an interrupt simultaneously, the interrupt vector will be serviced. Software can read the pin levels to identify which pin(s) are the source of the interrupt.

If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the “Interrupt Mapping” table.

A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register.

The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register.

Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.

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INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 18.

Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced.

Figure 19. Concurrent Interrupt Management

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 19 and Figure 20 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 20. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt.

Warning: A stack overflow may occur without notifying the software of the failure.

Note: TLI (Top Level Interrupt) is not available in this product.

HARDWARE PRIORITY

	IT2		IT1		IT4		IT3		TLI		IT0		SOFTWARE			I1								I0
													PRIORITY
													LEVEL											BYTES
												IT0			3			1				1
											TLI				3			1				1
							IT1					IT1			3			1				1		= 10
												IT3			3			1				1		STACK
			IT2												3			1				1		USED
RIM															3			1				1
												IT4
MAIN													MAIN		3/0
11 / 10													10

Figure 20. Nested Interrupt Management

HARDWARE PRIORITY

IT2

IT1

IT4

IT3

TLI

IT0

SOFTWARE

I1

I0

PRIORITY

LEVEL

		TLI		3	1		1
		IT0		3	1		1
	IT1		IT1	2	0		0
	IT2		IT2	1	0		1
RIM		IT3		3	1		1
				3	1		1
	IT4	IT4
MAIN			MAIN	3/0
11 / 10			10

USED STACK = 20 BYTES

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