SGS Thomson Microelectronics ST72T633L1M1, ST72T633K1B1, ST72T632L2M1, ST72T631L4M1, ST72T631K4B1 Datasheet

ST7263

LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C

PRELIMINARY DATA

■Up to 16Kbytes program memory

■Data RAM: up to 512 bytes with 64 bytes stack

■Run, Wait and Halt CPU modes

■RAM retention mode

■USB (Universal Serial Bus) Interface with DMA for low speed applications compliant with USB 1.5 Mbs specification (version 1.1) and USB HID specifications (version 1.0)

■Integrated 3.3V voltage regulator and transceivers

■Suspend and Resume operations

■3 endpoints with programmable in/out configuration

■19 programmable I/O lines with:

±8 high current I/Os (10mA at 1.3V)

±2 very high current pure Open Drain I/Os (25mA at 1.5V)

±8 lines individually programmable as interrupt inputs

■Low Voltage Reset (optional)

■Programmable Watchdog for system reliability

■16-bit Timer with:

±2 Input Captures

±2 Output Compares

±PWM Generation capabilities

±External Clock input

■Asynchronous Serial Communications Interface (8K and 16K program memory versions only)

■I2C Multi Master Interface up to 400 KHz (16K program memory version only)

■8-bit A/D Converter (ADC) with 8 channels

Table 1. Device Summary

PSDIP32

CSDIP32W

SO34 (Shrink)

■Fully static operation

■63 basic instructions

■17 main addressing modes

■8x8 unsigned multiply instruction

■True bit manipulation

■Versatile Development Tools (under Windows) including assembler, linker, C-compiler, archiver, source level debugger, software library, hardware emulator, programming boards and gang programmers

	Features	ST72631	ST72632	ST72633
	ROM - OTP (bytes)	16K	8K	4K
	RAM (stack) - bytes	512 (64)	256 (64)
	Peripherals	Watchdog, 16-bit timer, SCI, I2C, ADC, Watchdog, 16-bit timer,		Watchdog, 16-bit timer,
		USB	SCI, ADC, USB	ADC, USB
	Operating Supply		4.0V to 5.5V
	CPU frequency	8 Mhz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)
	Operating temperature		0°C to +70°C
	Packages		SO34/SDIP32
	EPROM device		ST72E631 1 (CSDIP32W)
	Note 1: EPROM version for development only			Rev. 1.5
	January 2000			1/107

This is preliminary information on a new product. Details are subject to change without notice.

Table of Contents

ST7263 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 EPROM/OTP PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
2.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
2.2	MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
2.3	CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
3 CLOCKS AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.1 Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.2 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.3 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			20
4.1	INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
	4.1.1	Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
4.2	POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
	4.2.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	4.2.2	HALT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	4.2.3	WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
5 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			25
5.1	I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
	5.1.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	5.1.2	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	5.1.3	I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	5.1.4	Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	5.1.5	Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
	5.1.6	Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	5.1.7	Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
5.2	MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32
5.3	WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		33

5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107. . . . 34

5.3.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2/107

Table of Contents

5.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

36

5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.6 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.6.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.5 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.7 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	87
6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	87

6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3/107

ST7263

7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

7.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

7.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.3 POWER CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

95

7.4 I/O PORT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.5 LOW VOLTAGE RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

7.6 CONTROL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

7.7 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 98

7.7.1 USB - Universal Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.7.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.8 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

8 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

8.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.2 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . 105 8.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4/107

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST7263 Microcontrollers form a sub family of the ST7 dedicated to USB applications. The devices are based on an industry-standard 8-bit core and feature an enhanced instruction set. They operate at a 24MHz or 12 MHz oscillator frequency. Under software control, the ST7263 MCUs may be placed in either Wait or Halt modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8-bit data management, the ST7263 MCUs feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. The devices include an ST7 Core, up to 16K program memory, up to 512 bytes RAM, 19 I/O lines and the following on-chip peripherals:

±USB low speed interface with 3 endpoints with programmable in/out configuration using the DMA architecture with embedded 3.3V voltage regulator and transceivers (no external components are needed).

±8-bit Analog-to-Digital converter (ADC) with 8 multiplexed analog inputs

Figure 1. General Block Diagram

		Internal
		CLOCK
	OSCIN	OSC/3
	OSCOUT	OSCILLATOR
		OSC/4 or OSC/2
		(for USB)
	VDD	POWER
	VSS	SUPPLY
		WATCH DOG	ADDRESS
	RESET	CONTROL
		8-BIT CORE	DATA AND
		ALU
		LVD
		USB DMA	BUS
	VPP/TEST	PROGRAM
		MEMORY
	VDDA	(4K/8K/16K Bytes)
	VSSA	RAM
		(256/512 Bytes)

* not on all products (refer to Table 1: Device Summary)

ST7263

± industry standard asynchronous SCI serial interface (not on all products - see device summary below)

±digital Watchdog

±16-bit Timer featuring an External clock input, 2 Input Captures, 2 Output Compares with Pulse Generator capabilities

±fast I2C Multi Master interface (not on all products - see device summary)

±Low voltage reset ensuring proper power-on or power-off of the device

All ST7263 MCUs are available in ROM and OTP versions.

The ST72E631 is the EPROM version of the ST7263 in CSDIP32 windowed packages.

A specific mode is available to allow programming of the EPROM user memory array. This is set by a specific voltage source applied to the VPP/TEST pin.

I2C*

	PORT A	PA[7:0]
		(8 bits)
	16-BIT TIMER
	PORT B	PB[7:0]
	ADC	(8 bits)
	PORT C
	SCI*	PC[2:0]
	(UART)	(3 bits)
	USB SIE	USBDP
		USBDM
		USBVCC

5/107

ST7263

1.2 PIN DESCRIPTION

Figure 2. 34-Pin SO Package Pinout

	VDD	1	34	VDDA
	OSCOUT	2	33	USBVCC
				USBDM
	OSCIN	3	32
	VSS	4	31	USBDP
	PC2/USBOE	5	30	VSSA
	PC1/TDO	6	29	PA0/MCO
	PC0/RDI	7	28	PA1(25mA)/SDA
	RESET	8	27	NC
	NC	9	26	NC
	AIN7/IT8/PB7(10mA)	10	25	NC
	AIN6/IT7/PB6(10mA)	11	24	PA2(25mA)/SCL
	VPP/TEST	12	23	PA3/EXTCLK
	AIN5/IT6/PB5(10mA)	13	22	PA4/ICAP1/IT1
	AIN4/IT5/PB4(10mA)	14	21	PA5/ICAP2/IT2
	AIN3/PB3(10mA)	15	20	PA6/OCMP1/IT3
	AIN2/PB2(10mA)	16	19	PA7/OCMP2/IT4
	AIN1/PB1(10mA)	17	18	PB0(10mA)/AIN0
	* VPP on EPROM/OTP versions only
	Figure 3. 32-Pin SDIP Package Pinout
	VDD	1	32	VDDA
	OSCOUT	2	31	USBVCC
	OSCIN	3	30	USBDM
	VSS	4	29	USBDP
	PC2/USBOE	5	28	VSSA
	PC1/TDO	6	27	PA0/MCO
	PC0/RDI	7	26	PA1(25mA)/SDA
	RESET	8	25	NC
	AIN7/IT8/PB7(10mA)	9	24	NC
	AIN6/IT7/PB6(10mA)	10	23	PA2(25mA)/SCL
	VPP/TEST*	11	22	PA3/EXTCLK
	AIN5/IT6/PB5(10mA)	12	21	PA4/ICAP1/IT1
	AIN4/IT5/PB4(10mA)	13	20	PA5/ICAP2/IT2
	AIN3/PB3(10mA)	14	19	PA6/COMP1/IT3
	AIN2/PB2(10mA)	15	18	PA7/COMP2/IT4
	AIN1/PB1/(10mA)	16	17	PB0(10mA)/AIN0

* VPP on EPROM/OTP versions only

6/107

ST7263

PIN DESCRIPTION (Cont'd)

RESET (see Note 1): Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog has triggered or VDD is low. It can be used to reset external peripherals.

OSCIN/OSCOUT: Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator.

VPP/TEST: EPROM programming input. This pin must be held low during normal operating modes.

VDD/VSS (see Note 2): Main power supply and Ground voltages.

VDDA/VSSA (see Note 2): Power Supply and Ground for analog peripherals.

Table 2. Device Pin Description

Alternate Functions: Several pins of the I/O ports assume software programmable alternate functions as shown in the pin description.

Note 1: Adding two 100nF decoupling capacitors on Reset pin (respectively connected to VDD and VSS) will significantly improve product electromagnetic susceptibility performances.

Note 2: To enhance reliability of operation, it is recommended to connect VDDA and VDD together on the application board. The same recommendations apply to VSSA and VSS.

Pin n°
SDIP32	SO34	Pin Name
1	1	VDD
2	2	OSCOUT
3	3	OSCIN
4	4	VSS
5	5	PC2/USBOE
6	6	PC1/TDO
7	7	PC0/RDI
8	8	RESET

--9 NC

9	10	PB7/AIN7/IT8
10	11	PB6/AIN6/IT7
11	12	VPP/TEST
12	13	PB5/AIN5/IT6
13	14	PB4/AIN4/IT5
14	15	PB3/AIN3
15	16	PB2/AIN2
16	17	PB1/AIN1
17	18	PB0/AIN0
18	19	PA7/OCMP2/IT4
19	20	PA6/OCMP1/IT3

	Level
Type	Input	Output	float
S
O
I
S
I/O		CT
I/O		CT
I/O		CT
I/O
--
I/O	CT 10mA		X
I/O	CT 10mA		X
S
I/O	CT 10mA		X
I/O	CT 10mA		X
I/O	CT 10mA		X
I/O	CT 10mA		X
I/O	CT 10mA		X
I/O	CT 10mA		X
I/O		CT
I/O		CT

Port / Control					Main
Input			Output
					Function	Alternate Function
wpu	int	ana	OD	PP	(after reset)
					Power supply voltage (4V - 5.5V)
					Oscillator output
					Oscillator input
					Digital ground
X				X	Port C2	USB Output Enable
X				X	Port C1	SCI transmit data output *)
X				X	Port C0	SCI Receive Data Input *)
X			X		Reset
					Not connected
	X	X		X	Port B7	ADC analog input 7
	X	X		X	Port B6	ADC analog input 6
					Supply for EPROM and test input
	X	X		X	Port B5	ADC analog input 5
	X	X		X	Port B4	ADC analog input 4
		X		X	Port B3	ADC analog input 3
		X		X	Port B2	ADC analog input 2
		X		X	Port B1	ADC analog input 1
		X		X	Port B0	ADC Analog Input 0
X	X			X	Port A7	Timer Output Compare 2
X	X			X	Port A6	Timer Output Compare 1

7/107

ST7263

Pin n°
SDIP32	SO34	Pin Name
20	21	PA5/ICAP2/IT2
21	22	PA4/ICAP1/IT1
22	23	PA3/EXTCLK
23	24	PA2/SCL
--	25	NC
24	26	NC
25	27	NC
26	28	PA1/SDA
27	29	PA0/MCO
28	30	VSSA
29	31	USBDP
30	32	USBDM
31	33	USBVCC
32	34	VDDA

	Level
Type	Input	Output	float
I/O		CT
I/O		CT
I/O		CT
I/O	CT 25mA		X
--
--
--
I/O	CT 25mA		X
I/O		CT
S
I/O

I/O

O

S

Port / Control					Main
Input			Output
					Function	Alternate Function
wpu	int	ana	OD	PP	(after reset)
X	X			X	Port A5	Timer Input Capture 2
X	X			X	Port A4	Timer Input Capture 1
X				X	Port A3	Timer External Clock
			X		Port A2	I2C serial clock *)
					Not connected
					Not connected
					Not connected
			X		Port A1	I2C serial data *)
	X			X	Port A0	Main Clock Output

Analog ground

USB bidirectional data (data +)

USB bidirectional data (data -)

USB power supply

Analog supply voltage

*: if the peripheral is present on the device (see Table 1 Device Summary)

Legend / Abbreviations of Figure 2 and Table 2:

Type:	I = input, O = output, S = supply
In/Output level:	CT = CMOS 0.3VDD/0.7VDD with input trigger
Output level:	10mA = 10mA high sink (on N-buffer only)

		25mA = 25mA very high sink (on N-buffer only)
Port and control configuration:
±	Input:	float = floating, wpu = weak pull-up, int = interrupt, ana = analog
±	Output:	OD = open drain, PP = push-pull

Refer to ªI/O PORTSº on page 25 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is kept as long as the device is under reset state.

8/107

ST7263

1.3 EXTERNAL CONNECTIONS

The following figure shows the recommended external connections for the device.

The VPP pin is only used for programming OTP and EPROM devices and must be tied to ground in user mode.

The 10 nF and 0.1 μF decoupling capacitors on the power supply lines are a suggested EMC performance/cost tradeoff.

Figure 4. Recommended External Connections

The external reset network is intended to protect the device against parasitic resets, especially in noisy environments.

Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up.

VPP

	VDD	+
	10nF		0.1μF

Optional if Low Voltage
Detector (LVD) is used	VDD
	4.7K
	0.1μF
EXTERNAL RESET CIRCUIT
	0.1μF
	See
	Clocks
	Section

Or configure unused I/O ports by software as input with pull-up

10K

VDD

VDD

VSS

RESET

OSCIN

OSCOUT

Unused I/O

9/107

ST7263

1.4 REGISTER & MEMORY MAP

As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 192 bytes of register location, up to 512 bytes of RAM and up to 16K bytes of user program memory. The RAM space includes up to 64 bytes for the stack from 0100h to 013Fh.

The highest address bytes contain the user reset and interrupt vectors.

IMPORTANT: Memory locations noted ªReservedº must never be accessed. Accessing a reserved area can have unpredictable effects on the device

Figure 5. Memory Map

	0000h	HW Registers
		(see Table 4	0040h
	003Fh		Short Addressing
			RAM (192 Bytes)
	0040h
		256 Bytes RAM*	00FFh
			0100h
	023Fh	512 Bytes RAM*	Stack (64 Bytes)
			013Fh
	0240h
		Reserved
			0040h
	BFFFh		Short Addressing
			RAM (192 Bytes)
	C000h
		Program Memory*	00FFh
			0100h
		16K Bytes	Stack (64 Bytes)
			013Fh
	E000h		0140h
		8K Bytes	16-bit Addressing RAM
	F000h
		4K Bytes	(256 Bytes)
			023Fh

FFEFh

FFF0h

Interrupt & Reset Vectors (see Table 3 on page 10)

FFFFh

*Program memory and RAM sizes are product dependent (see Table 1 Device Summary)

Table 3. Interrupt Vector Map

Vector Address	Description	Masked by	Remarks	Exit from Halt Mode
FFF0-FFF1h	USB Interrupt Vector	I- bit	Internal Interrupt	No
FFF2-FFF3h	SCI Interrupt Vector*	I- bit	Internal Interrupt	No
FFF4-FFF5h	I2C Interrupt Vector*	I- bit	Internal Interrupt	No
FFF6-FFF7h	TIMER Interrupt Vector	I- bit	Internal Interrupt	No
FFF8-FFF9h	IT1 to IT8 Interrupt Vector	I- bit	External Interrupts	Yes
FFFA-FFFB h	USB End Suspend Mode Interrupt Vector	I- bit	Internal Interrupt	Yes
FFFC-FFFDh	TRAP (software) Interrupt Vector	none	CPU Interrupt	No
FFFE-F FFFh	RESET Vector	none		Yes

* If the peripheral is present on the device (see Table 1 Device Summary)

10/107

ST7263

Table 4. Hardware Register Memory Map

Address

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h

0024h

Block

ADC

WDG

TIM

SCI 1)

Register Label	Register name	Reset Status	Remarks
PADR	Port A Data Register	00h	R/W
PADDR	Port A Data Direction Register	00h	R/W
PBDR	Port B Data Register	00h	R/W
PBDDR	Port B Data Direction Register	00h	R/W
PCDR	Port C Data Register	1111 x000b	R/W
PCDDR	Port C Data Direction Register	1111 x000b	R/W
	Reserved (2 Bytes)
ITIFRE	Interrupt Register	00h	R/W
MISCR	Miscellaneous Register	F0h	R/W
DR	ADC Data Register	00h	Read only
CSR	ADC control Status register	00h	R/W
CR	Watchdog Control Register	7Fh	R/W
	Reserved (4 Bytes)
CR2	Timer Control Register 2	00h	R/W
CR1	Timer Control Register 1	00h	R/W
SR	Timer Status Register	00h	Read only
IC1HR	Timer Input Capture High Register 1	xxh	Read only
IC1LR	Timer Input Capture Low Register 1	xxh	Read only
OC1HR	Timer Output Compare High Register 1	80h	R/W
OC1LR	Timer Output Compare Low Register 1	00h	R/W
CHR	Timer Counter High Register	FFh	Read only
CLR	Timer Counter Low Register	FCh	R/W
ACHR	Timer Alternate Counter High Register	FFh	Read only
ACLR	Timer Alternate Counter Low Register	FCh	R/W
IC2HR	Timer Input Capture High Register 2	xxh	Read only
IC2LR	Timer Input Capture Low Register 2	xxh	Read only
OC2HR	Timer Output Compare High Register 2	80h	R/W
OC2LR	Timer Output Compare Low Register 2	00h	R/W
SR	SCI Status Register	C0h	Read only
DR	SCI Data Register	xxh	R/W
BRR	SCI Baud Rate Register	00xx xxxxb	R/W
CR1	SCI Control Register 1	xxh	R/W
CR2	SCI Control Register 2	00h	R/W

11/107

ST7263

Address	Block	Register Label	Register name	Reset Status	Remarks
0025h		PIDR	USB PID Register	xxh	Read only
0026h		DMAR	USB DMA address Register	xxh	R/W
0027h		IDR	USB Interrupt/DMA Register	xxh	R/W
0028h		ISTR	USB Interrupt Status Register	00h	R/W
0029h		IMR	USB Interrupt Mask Register	00h	R/W
002Ah		CTLR	USB Control Register	xxxx 0110b	R/W
002Bh	USB	DADDR	USB Device Address Register	00h	R/W
002Ch		EP0RA	USB Endpoint 0 Register A	0000 xxxxb	R/W
002Dh		EP0RB	USB Endpoint 0 Register B	80h	R/W
002Eh		EP1RA	USB Endpoint 1 Register A	0000 xxxxb	R/W
002Fh		EP1RB	USB Endpoint 1 Register B	0000 xxxxb	R/W
0030h		EP2RA	USB Endpoint 2 Register A	0000 xxxxb	R/W
0031h		EP2RB	USB Endpoint 2 Register B	0000 xxxxb	R/W
0032h			Reserved (7 Bytes)
0038h
0039h		DR	I2C Data Register	00h	R/W
003Ah	I2C1)		Reserved	-
003Bh		OAR	I2C (7 Bits) Slave Address Register	00h	R/W
003Ch		CCR	I2C Clock Control Register	00h	R/W
003Dh		SR2	I2C 2nd Status Register	00h	Read only
003Eh		SR1	I2C 1st Status Register	00h	Read only
003Fh		CR	I2C Control Register	00h	R/W

Note 1. If the peripheral is present on the device (see Table 1 Device Summary)

12/107

1.5 EPROM/OTP PROGRAM MEMORY

The program memory of the ST72T63 may be programmed using the EPROM programming boards available from STMicroelectronics (see Table 26).

1.5.1 EPROM ERASURE

ST72Exxx EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current.

It is recommended that the ST72Exxx devices be kept out of direct sunlight, since the UV content of sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent lighting may also cause erasure.

ST7263

An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting conditions. Covering the window also reduces IDD in power-saving modes due to photo-diode leakage currents.

An Ultraviolet source of wave length 2537 Å yielding a total integrated dosage of 15 Watt-sec/cm2 is required to erase the ST72Exxx. The device will be erased in 15 to 30 minutes if such a UV lamp with a 12mW/cm2 power rating is placed 1 inch from the device window without any interposed filters.

13/107

ST7263

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

2.2 MAIN FEATURES

■63 basic instructions

■Fast 8-bit by 8-bit multiply

■17 main addressing modes

■Two 8-bit index registers

■16-bit stack pointer

■Low power modes

■Maskable hardware interrupts

■Non-maskable software interrupt

2.3 CPU REGISTERS

The 6 CPU registers shown in Figure 6 are not present in the memory mapping and are accessed by specific instructions.

Figure 6. CPU Registers

			7							0
			RESET VALUE = XXh
			7							0
			RESET VALUE = XXh
			7							0
			RESET VALUE = XXh
15	PCH	8	7			PCL				0
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
			7							0
			1	1	1	H	I	N	Z	C
	RESET VALUE = 1			1	1	X	1	X	X	X
15		8	7							0

RESET VALUE = STACK HIGHER ADDRESS

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

ACCUMULATOR

XINDEX REGISTER

YINDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

14/107

CPU REGISTERS (Cont'd)

CONDITION CODE REGISTER (CC)

Read/Write

Reset Value: 111x1xxx

7							0
1	1	1	H	I	N	Z	C

The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.

0:No half carry has occurred.

1:A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 3 = I Interrupt mask.

This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.

0:Interrupts are enabled.

1:Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware when you en-

ST7263

ter it and reset by the IRET instruction at the end of the interrupt routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.

0:The result of the last operation is positive or null.

1:The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0:The result of the last operation is different from zero.

1:The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0:No overflow or underflow has occurred.

1:An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the ªbit test and branchº, shift and rotate instructions.

15/107

ST7263

CPU REGISTERS (Cont'd)

Stack Pointer (SP)

Read/Write

Reset Value: 01 3Fh

15							8
0	0	0	0	0	0	0	1
7							0
0	0	SP5	SP4	SP3	SP2	SP1	SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 7).

Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (SP5 to SP0 bits are set) which is the stack higher address.

Figure 7. Stack Manipulation Example

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 7.

±When an interrupt is received, the SP is decremented and the context is pushed on the stack.

±On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

CALL	Interrupt	PUSH Y	POP Y	IRET	RET
Subroutine	Event				or RSP
@ 0100h

			SP
		SP	Y	SP
		CC	CC	CC
		A	A	A
		X	X	X
	SP	PCH	PCH	PCH	SP
		PCL	PCL	PCL
	PCH	PCH	PCH	PCH	PCH
	@ 013Fh PCL	PCL	PCL	PCL	SP
					PCL

Stack Higher Address = 013Fh

Stack Lower Address = 0100h

16/107

3 CLOCKS AND RESET

3.1 CLOCK SYSTEM

3.1.1 General Description

The MCU accepts either a Crystal or Ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (fOSC), which is divided by 3 (and by 2 or 4 for USB, depending on the external clock used).

By setting the CLKDIV bit in the Miscellaneous Register, a 12 MHz external clock can be used giving an internal frequency of 4 MHz while maintaining a 6 MHz for USB (refer to Figure 10).

The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%.

The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or ceramic resonator in the frequency range specified for fosc. The circuit shown in Figure 9 is recommended when using a crystal, and Table 5 Recommended Values for 24 MHz Crystal Resonator lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time.

Table 5. Recommended Values for 24 MHz Crystal Resonator

RSMAX	20 Ω	25 Ω	70 Ω
COSCIN	56pF	47pF	22pF
COSCOUT	56pF	47pF	22pF
RP	1-10 MΩ	1-10 MΩ	1-10 MΩ

Note: RSMAX is the equivalent serial resistor of the crystal (see crystal specification).

3.1.2 External Clock

An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 8. The tOXOV specifications does not apply when using an external clock input. The equivalent specification of the external clock

source should be used instead of tOXOV (see Section 6.5 CONTROL TIMING).

ST7263

Figure 8. External Clock Source Connections

OSCIN OSCOUT

NC

EXTERNAL

CLOCK

Figure 9. Crystal/Ceramic Resonator

OSCIN OSCOUT

RP

COSCIN

COSCOUT

Figure 10. Clock block diagram

			8 or 4 MHz
			CPU and
		%3	peripherals)
		CLKDIV
		1	6 MHz (USB)
			%2
24 or			%2
		0
12 MHz	%2
Crystal

17/107

ST7263

3.2 RESET

The Reset procedure is used to provide an orderly software start-up or to exit low power modes.

Three reset modes are provided: a low voltage reset, a watchdog reset and an external reset at the RESET pin.

A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point.

An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes active.

3.2.1 Low Voltage Reset

Low voltage reset circuitry generates a reset when VDD is:

■below VTRH when VDD is rising,

■below VTRL when VDD is falling.

During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

The Low Voltage Detector can be disabled by setting the LVD bit of the Miscellaneous Register.

3.2.2 Watchdog Reset

When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset other devices as when low voltage reset (Figure 11).

3.2.3 External Reset

The external reset is an active low input signal applied to the RESET pin of the MCU.

As shown in Figure 14, the RESET signal must stay low for a minimum of one and a half CPU clock cycles.

An internal Schmitt trigger at the RESET pin is provided to improve noise immunity.

Table 6. List of sections affected by RESET, WAIT and HALT (Refer to 3.5 for Wait and Halt Modes)

Section	RESET	WAIT	HALT
CPU clock running at 8 MHz	X
Timer Prescaler reset to zero	X
Timer Counter set to FFFCh	X
All Timer enable bit set to 0 (disable)	X
Data Direction Registers set to 0 (as Inputs)	X
Set Stack Pointer to 013Fh	X
Force Internal Address Bus to restart vector FFFEh,FFFFh	X
Set Interrupt Mask Bit (I-Bit, CCR) to 1 (Interrupt Disable)	X
Set Interrupt Mask Bit (I-Bit, CCR) to 0 (Interrupt Enable)		X	X
Reset HALT latch	X
Reset WAIT latch	X
Disable Oscillator (for 4096 cycles)	X		X
Set Timer Clock to 0	X		X
Watchdog counter reset	X
Watchdog register reset	X
Port data registers reset	X
Other on-chip peripherals: registers reset	X

18/107

		ST7263
	Figure 11. Low Voltage Reset functional Diagram	Figure 12. Low Voltage Reset Signal Output
	RESET	VTRH
	LOW VOLTAGE	VTRL
	VDD
	RESET
	INTERNAL	VDD
	RESET
	FROM
	WATCHDOG	RESET
	RESET
		Note: Typical hysteresis (VTRH-VTRL) of 250 mV is
		expected

Figure 13. Temporization timing diagram after an internal Reset

VTRH

VDD

temporization (4096 CPU clock cycles)

Addresses	$FFFE

Figure 14. Reset Timing Diagram

tDDR

VDD

OSCIN

tOXOV

fCPU
PC	FFFE	FFFF
RESET	4096 CPU
	CLOCK
	CYCLES
WATCHDOG RESET	DELAY

Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VTRH, VTRL and VTRM

19/107

ST7263

4 INTERRUPTS AND POWER SAVING MODES

4.1 INTERRUPTS

The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in Table 7 Interrupt Mapping and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 15.

The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).

When an interrupt has to be serviced:

±Normal processing is suspended at the end of the current instruction execution.

±The PC, X, A and CC registers are saved onto the stack.

±The I bit of the CC register is set to prevent additional interrupts.

±The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to Table 7 Interrupt Mapping for vector addresses).

The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume.

Priority management

By default, a servicing interrupt can not be interrupted because the I bit is set by hardware entering in interrupt routine.

In the case several interrupts are simultaneously pending, a hardware priority defines which one will be serviced first (see Table 7 Interrupt Mapping).

Non maskable software interrupts

This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 15.

Interrupts and Low power mode

All interrupts allow the processor to leave the Wait low power mode. Only external and specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to the ªExit from HALTª column in Table 7 Interrupt Mapping).

External interrupts

The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising edge occurs on this pin. Conversely, pins ITl/PAn and ITm/ PBn (l=3,4; m= 7,8; n=6,7) can generate an interrupt when a falling edge occurs on this pin.

Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE register and if the I bit of the CCR is reset.

Peripheral interrupts

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both.

±The I bit of the CC register is cleared.

±The corresponding enable bit is set in the control register.

If any of these two conditions is false, the interrupt is latched and thus remains pending.

Clearing an interrupt request is done by:

±writing ª0º to the corresponding bit in the status register or

±an access to the status register while the flag is set followed by a read or write of an associated

register.

Notes:

1. The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.

2.All interrupts allow the processor to leave the Wait low power mode.

3.Exit from Halt mode may only be triggered by an External Interrupt on one of the ITi ports (PA4-PA7

and PB4-PB7), an end suspend mode Interrupt coming from USB peripheral, or a reset.

20/107

ST7263

INTERRUPTS (Cont'd)

Figure 15. Interrupt Processing Flowchart

FROM RESET

	N
	BIT I SET
	Y	N
		INTERRUPT
	FETCH NEXT INSTR UCTION	Y
	N
	IRET	STACK PC, X, A, CC
	Y	SET I BIT
		LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

Table 7. Interrupt Mapping

		Source		Register	Priority	Exit	Vector
	N°		Description			from	Address
		Block		Label	Order
						HALT
		RESET	Reset	N/A	Highest	yes	FFFEh-FFFFh
		TRAP	Software Interrupt		Priority	no	FFFCh-FFFDh
		USB	End Suspend Mode	ISTR		yes	FFFAh-FFFBh
	1	ITi	External Interrupts	ITRFRE			FFF8h-FFF9h
	2	TIMER	Timer Peripheral Interrupts	TIMSR			FFF6h-FFF7h
	3	I2C	I2C Peripheral Interrupts	I2CSR1			FFF4h-FFF5h
				I2CSR2
						no
	4	SCI	SCI Peripheral Interrupts	SCISR			FFF2h-FFF3h
					Lowest
	5	USB	USB Peripheral Interrupts	ISTR	Priority		FFF0h-FFF1h

21/107

ST7263

INTERRUPTS (Cont'd)

4.1.1 Interrupt Register

INTERRUPTS REGISTER (ITRFRE)

Address: 0008h Ð Read/Write

Reset Value: 0000 0000 (00h)

7							0
IT8E	IT7E	IT6E	IT5E	IT4E	IT3E	IT2E	IT1E

Bit 7:0 = ITiE (i=1 to 8). Interrupt Enable Control Bits.

If an ITiE bit is set, the corresponding interrupt is generated when

± a rising edge occurs on the pin PA4/IT1 or PA5/ IT2 or PB4/IT5 or PB5/IT6

or

± a falling edge occurs on the pin PA6/IT3 or PA7/ IT4 or PB6/IT7 or PB7/IT8

No interrupt is generated elsewhere.

Note: Analog input must be disabled for interrupts coming from port B.

22/107

4.2 POWER SAVING MODES

4.2.1 Introduction

To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7.

After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 (fCPU).

From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

ST7263

Figure 16. HALT Mode Flow Chart

HALT INSTRUCTION

OSCILLATOR	OFF
PERIPH. CLOCK	OFF
CPU CLOCK	OFF
I-BIT	CLEARED

4.2.2 HALT mode

The HALT mode is the MCU lowest power consumption mode. The HALT mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals.

When entering HALT mode, the I bit in the Condition Code Register is cleared. Thus, any of the external interrupts (ITi or USB end suspend mode), are allowed and if an interrupt occurs, the CPU clock becomes active.

The MCU can exit HALT mode on reception of either an external interrupt on ITi, an end suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles.

After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up.

N

RESET
N
EXTERNAL	Y
INTERRUPT*
Y
OSCILLATOR		ON
PERIPH. CLOCK		ON
CPU CLOCK		ON
I-BIT		SET

4096 CPU CLOCK

CYCLES DELAY

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.

23/107

ST7263

POWER SAVING MODES (Cont'd)

4.2.3 WAIT mode

WAIT mode places the MCU in a low power consumption mode by stopping the CPU.

This power saving mode is selected by calling the ªWFIº ST7 software instruction.

All peripherals remain active. During WAIT mode, the I bit of the CC register is forced to 0, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine.

The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up.

Refer to Figure 17.

Figure 17. WAIT Mode Flow Chart

WFI INSTRUCTION

OSCILLATOR	ON
PERIPH. CLOCK	ON
CPU CLOCK	OFF
I-BIT	CLEARED

N

RESET

N

INTERRUPT	Y
Y	OSCILLATOR	ON
	PERIPH. CLOCK	ON
	CPU CLOCK	ON
	I-BIT	SET

IF RESET

4096 CPU CLOCK CYCLES DELAY

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.

24/107

5 ON-CHIP PERIPHERALS

5.1 I/O PORTS

5.1.1 Introduction

The I/O ports offer different functional modes:

±transfer of data through digital inputs and outputs and for specific pins:

±analog signal input (ADC)

±alternate signal input/output for the on-chip peripherals.

±external interrupt generation

An I/O port is composed of up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

5.1.2 Functional description

Each port is associated to 2 main registers:

±Data Register (DR)

±Data Direction Register (DDR)

Each I/O pin may be programmed using the corresponding register bits in DDR register: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.

Table 8. I/O Pin Functions

DDR	MODE
0	Input
1	Output

Input Modes

The input configuration is selected by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Note 1: All the inputs are triggered by a Schmitt trigger.

Note 2: When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output.

Interrupt function

When an I/O is configured in Input with Interrupt, an event on this I/O can generate an external In-

ST7263

terrupt request to the CPU. The interrupt sensitivity is given independently according to the description mentioned in the ITRFRE interrupt register.

Each pin can independently generate an Interrupt request.

Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as interrupt source, this is logically ORed. For this reason if one of the interrupt pins is tied low, it masks the other ones.

Output Mode

The pin is configured in output mode by setting the corresponding DDR register bit (see Table 7).

In this mode, writing ª0º or ª1º to the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value.

Note: In this mode, the interrupt function is disabled.

Digital Alternate Function

When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).

When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin's state is also digitally readable by addressing the DR register.

Notes:

1.Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input.

2.When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input

(DDR = 0).

Warning: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

25/107

ST7263

I/O PORTS (Cont'd)

Analog Alternate Function

When the pin is used as an ADC input the I/O must be configured as input, floating. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to

have clocking pins located close to a selected analog pin.

Warning: The analog input voltage level must be within the limits stated in the Absolute Maximum Ratings.

5.1.3 I/O Port Implementation

The hardware implementation on each I/O port depends on the settings in the DDR register and specific feature of the I/O port such as ADC Input or true open drain.

26/107

ST7263

I/O PORTS (Cont'd)

5.1.4 Port A

Table 9. Port A0, A3, A4, A5, A6, A7 Description

	PORT A		I / O
		Input*	Output
	PA0	with pull-up	push-pull
	PA3	with pull-up	push-pull
	PA4	with pull-up	push-pull
	PA5	with pull-up	push-pull
	PA6	with pull-up	push-pull
	PA7	with pull-up	push-pull
	*Reset State

Alternate Function

	Signal	Condition
	MCO (Main Clock Output)	MCO = 1 (MISCR)
	Timer EXTCLK	CC1 =1
		CC0 = 1 (Timer CR2)
	Timer ICAP1
	IT1 Schmitt triggered input	IT1E = 1 (ITIFRE)
	Timer ICAP2
	IT2 Schmitt triggered input	IT2E = 1 (ITIFRE)
	Timer OCMP1	OC1E = 1
	IT3 Schmitt triggered input	IT3E = 1 (ITIFRE)
	Timer OCMP2	OC2E = 1
	IT4 Schmitt triggered input	IT4E = 1 (ITIFRE)

Figure 18. PA0, PA3, PA4, PA5, PA6, PA7 Configuration

ALTERNATE 1

OUTPUT

0

	DR
DATA	LATCH
BUS	DDR
	LATCH
	DDR SEL

DR SEL	1
ALTERNATE INPUT	0

ALTERNATE ENABLE

VDD

P-BUFFER

VDD

PULL-UP

ALTERNATE ENABLE

PAD

N-BUFFER

DIODES

ALTERNATE ENABLE

VSS

CMOS SCHMITT TRIGGER

27/107

ST7263

I/O PORTS (Cont'd)

Table 10. PA1, PA2 Description

	PORT A		I / O	Alternate Function
		Inpu t*	Output	Signal	Condition
	PA1	without pull-up	Very High Current open drain	SDA (I2C data)	I2C enable
	PA2	without pull-up	Very High Current open drain	SCL (I2C clock)	I2C enable
	*Reset State

Figure 19. PA1, PA2 Configuration

ALTERNATE ENABLE

ALTERNATE 1

OUTPUT

0

DR

LATCH

DDR

LATCH

BUS DATA

DDR SEL
		N-BUFFER
DR SEL	1	ALTERNATE ENABLE
	0	VSS
		CMOS SCHMITT TRIGGER

PAD

28/107

ST7263

I/O PORTS (Cont'd)

5.1.5 Port B

Table 11. Port B Description

	PORT B		I/O	Alternate Function
		Input*	Output	Signal	Condit ion
	PB0	without pull-up	push-pull	Analog input (ADC)	CH[2:0] = 000 (ADCCSR)
	PB1	without pull-up	push-pull	Analog input (ADC)	CH[2:0] = 001 (ADCCSR)
	PB2	without pull-up	push-pull	Analog input (ADC)	CH[2:0]= 010 (ADCCSR)
	PB3	without pull-up	push-pull	Analog input (ADC)	CH[2:0]= 011 (ADCCSR)
	PB4	without pull-up	push-pull	Analog input (ADC)	CH[2:0]= 100 (ADCCSR)
				IT5 Schmitt triggered input	IT4E = 1 (ITIFRE)
	PB5	without pull-up	push-pull	Analog input (ADC)	CH[2:0]= 101 (ADCCSR)
				IT6 Schmitt triggered input	IT5E = 1 (ITIFRE)
	PB6	without pull-up	push-pull	Analog input (ADC)	CH[2:0]= 110 (ADCCSR)
				IT7 Schmitt triggered input	IT6E = 1 (ITIFRE)
	PB7	without pull-up	push-pull	Analog input (ADC)	CH[2:0]= 111 (ADCCSR)
				IT8 Schmitt triggered input	IT7E = 1 (ITIFRE)

*Reset State

Figure 20. Port B Configuration

ANALOG COMMON	BUS DATA
RAIL

	ALTERNATE ENABLE
ALTERNATE 1		VDD
OUTPUT	0
		VDD
DR		P-BUFFER
LATCH
	ALTERNATE ENABLE
DDR		PAD
LATCH
	ANALOG ENABLE
	(ADC)
DDR SEL	ANALOG
	SWITCH	DIODES
		N-BUFFER
DR SEL	1
	ALTERNATE ENABLE
	DIGITAL ENABLE	VSS
	0

ALTERNATE INPUT

29/107

ST7263

I/O PORTS (Cont'd)

5.1.6 Port C

Table 12. Port C Description

PORT C	I / O	Alternate Function
Input*	Output	Signal	Conditio n

PC0	with pull-up	push-pull
PC1	with pull-up	push-pull
PC2	with pull-up	push-pull
*Reset State

RDI (SCI input)
TDO (SCI output)	SCI enable
USBOE (USB output ena-	USBOE =1
ble)	(MISCR)

Figure 21. Port C Configuration

ALTERNATE1

OUTPUT

0

		DR
		LATCH
	DATA	DDR
	BUS	LATCH
		DDR SEL

DR SEL

1

0

ALTERNATE INPUT

ALTERNATE ENABLE

VDD

P-BUFFER

VDD

PULL-UP

ALTERNATE ENABLE

PAD

N-BUFFER

DIODES

ALTERNATE ENABLE

VSS

CMOS SCHMITT TRIGGER

30/107