ST72324
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
■Memories
–8 to 32K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and InCircuit Programming for HDFlash devices
–384 to 1K bytes RAM
–HDFlash endurance: 100 cycles, data retention: 20 years at 55°C
■Clock, Reset And Supply Management
–Enhanced low voltage supervisor (LVD) for main supply with 3 programmable reset thresholds and auxiliary voltage detector (AVD) with interrupt capability
–Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
–PLL for 2x frequency multiplication
–Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
■Interrupt Management
–Nested interrupt controller
–10 interrupt vectors plus TRAP and RESET
–9/6 external interrupt lines (on 4 vectors)
■Up to 32 I/O Ports
–32/24 multifunctional bidirectional I/O lines
–22/17 alternate function lines
–12/10 high sink outputs
■4 Timers
–Main Clock Controller with: Real time base, Beep and Clock-out capabilities
–Configurable watchdog timer
–16-bit Timer A with: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
–16-bit Timer B with: 2 input captures, 2 output compares, PWM and pulse generator modes
Device Summary
TQFP32
7 x 7
TQFP44 10 x 10
SDIP42 |
SDIP32 |
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400 mil |
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600 mil |
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■2 Communication Interfaces
–SPI synchronous serial interface
–SCI asynchronous serial interface (LIN compatible)
■1 Analog Peripheral
–10-bit ADC with up to 12 input pins
■Instruction Set
–8-bit Data Manipulation
–63 Basic Instructions
–17 main Addressing Modes
–8 x 8 Unsigned Multiply Instruction
■Development Tools
–Full hardware/software development package
–In-Circuit Testing capability
Features |
ST72324(J/K)6 |
ST72324(J/K)4 |
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ST72324(J/K)2 |
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Program memory - bytes |
32K |
16K |
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8K |
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RAM (stack) - bytes |
1024 (256) |
512 (256) |
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384 (256) |
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Operating Voltage |
3.8V to 5.5V (low |
voltage Flash version planned with 3.0 to 3.6V range) |
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Temp. Range (ROM) |
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up to -40°C to +125°C |
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Temp. Range (Flash) |
up to -40°C to +125°C |
-40°C to +85 °C |
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Packages |
SDIP42 (JxB), |
TQFP44 10x10 (JxT),SDIP32 (KxB), TQFP32 7x7 (KxT) |
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Rev. 1.9
August 2003 |
1/161 |
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
17 |
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4.2 |
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
17 |
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4.3 |
STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
17 |
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4.3.1 |
Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
17 |
4.4 |
ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
18 |
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4.5 |
ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
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4.6 |
IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
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4.7 |
RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
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4.7.1 |
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
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5.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
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5.2 |
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
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5.3 |
CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
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6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
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6.1 |
PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
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6.2 |
MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
24 |
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6.3 |
RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
25 |
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6.3.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
25 |
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6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
25 |
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6.3.3 |
External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
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6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
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6.3.5 |
Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
6.4 |
SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
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6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
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6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
28 |
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6.4.3 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
29 |
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6.4.4 |
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
29 |
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6.4.5 |
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
30 |
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
31 |
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7.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
31 |
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7.2 |
MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
31 |
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7.3 |
INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
33 |
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7.4 |
CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
33 |
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7.5 |
INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
34 |
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7.6 |
EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
36 |
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7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
36 |
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7.7 |
EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . |
38 |
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8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
40 |
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8.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
40 |
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8.2 |
SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
40 |
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2/161 |
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2
Table of Contents
8.3 |
WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
41 |
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8.4 |
ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
42 |
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8.4.1 |
ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
42 |
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8.4.2 |
HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
43 |
9 I/O PORTS . |
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45 |
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9.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
45 |
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9.2 |
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
45 |
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9.2.1 |
Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
45 |
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9.2.2 |
Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
45 |
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9.2.3 |
Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
45 |
9.3 |
I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
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9.4 |
LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
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9.5 |
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
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9.5.1 |
I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
49 |
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
51 |
10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 54 10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 56
10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.4.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3/161
1
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Table of Contents |
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10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 85 |
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10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
85 |
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10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
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10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
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10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
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10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
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10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
91 |
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10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
96 |
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10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
96 |
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10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
97 |
10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
103 |
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10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
103 |
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10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
103 |
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10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
104 |
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10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
104 |
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10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
104 |
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10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
105 |
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
107 |
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11.1 |
CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
107 |
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11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
108 |
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11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
108 |
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11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
108 |
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11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
108 |
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11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
108 |
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11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
109 |
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11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
109 |
11.2 |
INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
110 |
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
113 |
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12.1 |
PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
113 |
12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
114 |
12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
114 |
12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
115 |
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
115 |
12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.3.2 General Operating Conditions for low voltage Flash devices (planned) . . . . . . . . 116 12.3.3 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 117 12.3.4 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.4.1 RUN and SLOW Modes (Flash devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.4.2 WAIT and SLOW WAIT Modes (Flash devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 120
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Table of Contents |
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12.4.3 RUN and SLOW Modes (ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
121 |
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12.4.4 WAIT and SLOW WAIT Modes (ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . |
121 |
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12.4.5 HALT and ACTIVE-HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
122 |
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12.4.6 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
122 |
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12.4.7 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
123 |
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
124 |
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12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
124 |
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12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
124 |
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12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
125 |
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12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
127 |
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12.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
128 |
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12.5.6 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
128 |
12.6 |
MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
129 |
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12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
129 |
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12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
129 |
12.7 |
EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
130 |
12.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.7.3 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12.7.4 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.10.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 140
12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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12.12.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
143 |
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12.12.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
143 |
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12.12.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
144 |
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
145 |
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13.1 |
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
145 |
13.2 |
THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
147 |
13.3 |
SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
148 |
14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . |
149 |
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14.1 |
FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
149 |
14.2 |
DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . |
151 |
14.2.1 Version-Specific Sales Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
14.3.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
157 |
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15.1 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
15.2 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
15.2.1 External RC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.2.2 CSS Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.2.3 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.2.4 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.2.5 Internal RC Oscillator with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.2.6 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
15.3 FLASH REV “X” AND ALL ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
15.3.1 Read-out protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
158 |
15.3.2 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
158 |
15.3.3 I/O Port A and F Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
158 |
15.3.4 LVD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
158 |
15.4 ALL ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
158 |
15.4.1 AVD not supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
158 |
15.4.2 Internal RC oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
158 |
16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
160 |
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet.
Please also pay special attention to the Section “IMPORTANT NOTES” on page 157
6/161
1
ST72324
1 INTRODUCTION
The ST72324K and ST72324J devices are members of the ST7 microcontroller family. They can be grouped as follows:
–The 32-pin ST72324K devices are designed for mid-range applications
–The 42/44-pin ST72324J devices target the same range of applications requiring more than 24 I/O ports.
All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruc-
Figure 1. Device Block Diagram
tion set and are available with FLASH or ROM program memory.
Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state.
The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
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8-BIT CORE |
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ALU |
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RESET |
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CONTROL |
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VPP |
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VSS |
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LVD |
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VDD |
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OSC1
OSC2
PF7:6,4,2:0 (6 bits on J devices) (5 bits on K devices)
PE1:0 (2 bits)
PD5:0 (6 bits on J devices) (2 bits on K devices)
VAREF
OSC
MCC/RTC/BEEP
PORT F
TIMER A
BEEP
PORT E
SCI
PORT D
10-BIT ADC
VSSA
BUS DATA AND ADDRESS
PROGRAM
MEMORY
(8K - 60K Bytes)
RAM
(384 - 2048 Bytes)
WATCHDOG
PORT A
PORT B
PORT C
TIMER B
SPI
PA7:3
(5 bits on J devices) (4 bits on K devices)
PB4:0
(5 bits on J devices) (3 bits on K devices)
PC7:0 (8 bits)
7/161
3
ST72324
2 PIN DESCRIPTION
Figure 2. 42-Pin SDIP and 44-Pin TQFP Package Pinouts
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PE0/ TDO |
2 |
OSC1 |
OSC2 |
2 |
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RESET |
/ ICCSEL |
PA5(HS) |
PA4(HS) |
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V |
V |
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V (HS)PA7 (HS)PA6 |
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DD |
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SS |
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PP |
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RDI / PE1 |
44 43 42 41 40 39 38 37 36 35 34 |
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1 |
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33 |
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PB0 |
2 |
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32 |
PB1 |
3 |
ei2 |
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ei0 |
31 |
PB2 |
4 |
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30 |
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PB3 |
5 |
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29 |
(HS) PB4 |
6 |
ei3 |
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28 |
AIN0 / PD0 |
7 |
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27 |
AIN1 / PD1 |
8 |
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26 |
AIN2 / PD2 |
9 |
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25 |
AIN3 / PD3 |
10 |
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ei1 |
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24 |
AIN4 / PD4 |
11 |
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23 |
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12 13 14 15 16 17 18 19 20 21 22 |
V
VDD_1
PA3 (HS)
PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12
AIN5 / PD5 |
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AREF |
SSA |
MCO/ AIN8 / PF0 |
BEEP / (HS) PF1 |
(HS) PF2 |
OCMP1A / AIN10 / PF4 |
ICAP1A / (HS) PF6 |
EXTCLKA / (HS) PF7 |
DD 0 |
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SS 0 |
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V |
V |
V |
V |
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(HS) PB4 |
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PB3 |
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ei3 |
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AIN0 / PD0 |
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2 |
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ei2 |
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41 |
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PB2 |
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AIN1 / PD1 |
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3 |
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40 |
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PB1 |
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AIN2 / PD2 |
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4 |
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39 |
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PB0 |
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AIN3 / PD3 |
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5 |
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38 |
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PE1 / RDI |
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AIN4 / PD4 |
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6 |
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37 |
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PE0 / TDO |
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AIN5 / PD5 |
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VDD_2 |
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VAREF |
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8 |
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OSC1 |
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VSSA |
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OSC2 |
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MCO / AIN8 / PF0 |
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10 |
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33 |
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VSS_2 |
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BEEP / (HS) PF1 |
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11 |
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ei1 |
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32 |
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RESET |
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(HS) PF2 |
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12 |
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31 |
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VPP / ICCSEL |
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||||
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AIN10 / OCMP1_A / PF4 |
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13 |
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30 |
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PA7 (HS) |
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ICAP1_A / (HS) PF6 |
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14 |
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29 |
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PA6 (HS) |
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EXTCLK_A / (HS) PF7 |
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15 |
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28 |
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PA5 (HS) |
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AIN12 / OCMP2_B / PC0 |
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16 |
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27 |
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PA4 (HS) |
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AIN13 / OCMP1_B / PC1 |
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17 |
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26 |
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VSS_1 |
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ICAP2_B/ (HS) PC2 |
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18 |
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25 |
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VDD_1 |
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ICAP1_B / (HS) PC3 |
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19 |
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ei0 |
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24 |
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PA3 (HS) |
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ICCDATA / MISO / PC4 |
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PC7 / |
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/ AIN15 |
|||
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20 |
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23 |
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SS |
||||||
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AIN14 / MOSI / PC5 |
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21 |
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22 |
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PC6 / SCK / ICCCLK |
|||||
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(HS) |
20mA high sink capability |
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eix |
associated external interrupt vector |
8/161
ST72324
PIN DESCRIPTION (Cont’d)
Figure 3. 32-Pin SDIP Package Pinout
(HS) PB4 |
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PB3 |
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||||
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1 |
ei3 |
32 |
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AIN0 / PD0 |
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2 |
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ei2 |
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PB0 |
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31 |
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|||||||
AIN1 / PD1 |
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PE1 / RDI |
|||||||
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3 |
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30 |
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VAREF |
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PE0 / TDO |
|||||||
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4 |
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29 |
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|||||||
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|||||||||
VSSA |
|
5 |
|
28 |
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VDD_2 |
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||||
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||||||||
MCO / AIN8 / PF0 |
|
6 |
ei1 |
27 |
|
OSC1 |
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|||||||||
BEEP / (HS) PF1 |
|
7 |
26 |
|
OSC2 |
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||||||||
OCMP1_A / AIN10 / PF4 |
|
8 |
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25 |
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VSS_2 |
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ICAP1_A / (HS) PF6 |
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9 |
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24 |
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RESET |
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||||
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||||||
EXTCLK_A / (HS) PF7 |
|
10 |
|
23 |
|
VPP / ICCSEL |
|||||
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|||||||||
AIN12 / OCMP2_B / PC0 |
|
11 |
|
22 |
|
PA7 (HS) |
|
||||
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||||||||
AIN13 / OCMP1_B / PC1 |
|
12 |
|
21 |
|
PA6 (HS) |
|
||||
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||||||||
ICAP2_B / (HS) PC2 |
|
13 |
|
20 |
|
PA4 (HS) |
|
||||
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||||||||
ICAP1_B / (HS) PC3 |
|
14 |
|
ei0 19 |
|
PA3 (HS) |
|
||||
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||||||||
ICCDATA/ MISO / PC4 |
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PC7 / |
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/ AIN15 |
||
|
15 |
|
18 |
SS |
|||||||
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|||||||||
AIN14 / MOSI / PC5 |
|
16 |
|
17 |
|
PC6 / SCK / ICCCLK |
|||||
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|||||||||
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(HS) |
20mA high sink capability |
|||
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|||||
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|
eix |
associated external interrupt vector |
|||
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|
Figure 4. 32-Pin TQFP 7x7 Package Pinout
|
/ AIN1 |
/ AIN0 |
(HS) |
/ RDI |
/ TDO |
2 |
|
|
|
PD1 |
PD0 |
PB4 |
PB3 PB0 PE1 |
PE0 |
V |
|
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|
DD |
|
|
VAREF |
32 31 30 29 28 27 26 25 |
OSC1 |
||||||
1 |
|
ei3 |
ei2 |
|
24 |
|||
VSSA |
2 |
|
|
23 |
OSC2 |
|||
|
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|
|||||
MCO / AIN8 / PF0 |
3 |
|
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|
22 |
VSS_2 |
|
BEEP / (HS) PF1 |
ei1 |
|
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|
21 |
|
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|
4 |
|
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|
|
RESET |
|||
OCMP1_A / AIN10 / PF4 |
5 |
|
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|
20 |
VPP / ICCSEL |
|
ICAP1_A / (HS) PF6 |
6 |
|
|
|
|
19 |
PA7 (HS) |
|
EXTCLK_A / (HS) PF7 |
7 |
|
|
|
|
18 |
PA6 (HS) |
|
AIN12 / OCMP2_B / PC0 |
8 |
|
|
|
ei0 17 |
PA4 (HS) |
||
|
9 |
10 11 12 13 14 15 16 |
|
|
AIN13 / OCMP1 B / PC1 |
ICAP2 B / (HS) PC2 |
ICAP1 B / (HS) PC3 |
ICCDATA / MISO / PC4 |
AIN14 / MOSI / PC5 |
ICCCLK / SCK / PC6 |
|
AIN15 / SS / PC7 |
(HS) PA3 |
|
||||||||
|
(HS) 20mA high sink capability
eix associated external interrupt vector
9/161
ST72324
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 113.
Legend / Abbreviations for Table 1:
Type: |
I = input, O = output, S = supply |
|
Input level: |
A = Dedicated analog input |
|
In/Output level: C = CMOS 0.3VDD/0.7VDD |
||
Output level: |
CT= CMOS 0.3VDD/0.7VDD with input trigger |
|
HS = 20mA high sink (on N-buffer only) |
||
Port and control configuration: |
||
– |
Input: |
float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog |
– |
Output: |
OD = open drain 2), PP = push-pull |
Refer to “I/O PORTS” on page 45 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.
Table 1. Device Pin Description
|
Pin n° |
|
|
|
Level |
|
|
Port |
|
|
Main |
|
|
|
|||
|
|
|
|
|
Type |
|
|
|
|
|
|
|
|
|
|
|
|
TQFP44 |
SDIP42 |
TQFP32 |
SDIP32 |
Pin Name |
Input |
Output |
float |
wpu |
int |
ana |
OD |
PP |
function |
Alternate Function |
|||
|
|
|
|
|
|
|
|
Input |
|
Output |
(after |
||||||
|
|
|
|
|
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|
|
|
|
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|
|
reset) |
|
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|
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|
|
|
|
|
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|
|
|
|
|
|
6 |
1 |
30 |
1 |
PB4 (HS)5) |
I/O |
CT |
HS |
X |
ei3 |
|
X |
X |
Port B4 |
|
|
|
|
7 |
2 |
31 |
2 |
PD0/AIN0 |
I/O |
CT |
|
X |
X |
|
X |
X |
X |
Port D0 |
ADC Analog Input 0 |
||
8 |
3 |
32 |
3 |
PD1/AIN1 |
I/O |
CT |
|
X |
X |
|
X |
X |
X |
Port D1 |
ADC Analog Input 1 |
||
9 |
4 |
|
|
PD2/AIN2 |
I/O |
CT |
|
X |
X |
|
X |
X |
X |
Port D2 |
ADC Analog Input 2 |
||
10 |
5 |
|
|
PD3/AIN3 |
I/O |
CT |
|
X |
X |
|
X |
X |
X |
Port D3 |
ADC Analog Input 3 |
||
11 |
6 |
|
|
PD4/AIN4 |
I/O |
CT |
|
X |
X |
|
X |
X |
X |
Port D4 |
ADC Analog Input 4 |
||
12 |
7 |
|
|
PD5/AIN5 |
I/O |
CT |
|
X |
X |
|
X |
X |
X |
Port D5 |
ADC Analog Input 5 |
||
13 |
8 |
1 |
4 |
VAREF |
S |
|
|
|
|
|
|
|
|
Analog Reference Voltage for ADC |
|||
14 |
9 |
2 |
5 |
VSSA |
S |
|
|
|
|
|
|
|
|
Analog Ground Voltage |
|
||
15 |
10 |
3 |
6 |
PF0/MCO/AIN8 |
I/O |
CT |
|
X |
ei1 |
X |
X |
X |
Port F0 |
Main clock |
|
ADC Analog |
|
|
out (fOSC/2) |
|
Input 8 |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
16 |
11 |
4 |
7 |
PF1 (HS)/BEEP |
I/O |
CT |
HS |
X |
ei1 |
|
X |
X |
Port F1 |
Beep signal output |
|||
17 |
12 |
|
|
PF2 (HS) |
I/O |
CT |
HS |
X |
|
ei1 |
|
X |
X |
Port F2 |
|
|
|
|
|
|
|
PF4/OCMP1_A/ |
|
|
|
X |
|
|
|
|
|
|
Timer A Out- |
|
ADC Analog |
18 |
13 |
5 |
8 |
AIN10 |
I/O |
CT |
|
X |
|
X |
X |
X |
Port F4 |
put Com- |
|
Input 10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
pare 1 |
|
|
19 |
14 |
6 |
9 |
PF6 (HS)/ICAP1_A |
I/O |
CT |
HS |
X |
X |
|
|
X |
X |
Port F6 |
Timer A Input Capture 1 |
||
20 |
15 |
7 |
10 |
PF7 (HS)/ |
I/O |
CT |
HS |
X |
X |
|
|
X |
X |
Port F7 |
Timer A External Clock |
||
EXTCLK_A |
|
|
Source |
|
|||||||||||||
|
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|
21 |
|
|
|
VDD_0 |
S |
|
|
|
|
|
|
|
|
Digital Main Supply Voltage |
|||
22 |
|
|
|
VSS_0 |
S |
|
|
|
|
|
|
|
|
Digital Ground Voltage |
|
||
|
|
|
|
PC0/OCMP2_B/ |
|
|
|
X |
|
|
|
|
|
|
Timer B Out- |
|
ADC Analog |
23 |
16 |
8 |
11 |
AIN12 |
I/O |
CT |
|
X |
|
X |
X |
X |
Port C0 |
put Com- |
|
Input 12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
pare 2 |
|
|
10/161
ST72324
|
Pin n° |
|
|
|
|
|
|
|
Level |
|
|
Port |
|
|
Main |
|
|
|
|||
|
|
|
|
|
|
|
|
|
Type |
|
|
|
|
|
|
|
|
|
|
|
|
TQFP44 |
SDIP42 |
TQFP32 |
SDIP32 |
|
|
Pin Name |
Input |
Output |
float |
wpu |
int |
ana |
OD |
PP |
function |
|
Alternate Function |
||||
|
|
|
|
|
|
|
|
|
|
Input |
|
Output |
(after |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
reset) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
PC1/OCMP1_B/ |
|
|
|
X |
|
|
|
|
|
|
|
Timer B Out- |
ADC Analog |
|||
24 |
17 |
9 |
12 |
|
AIN13 |
I/O |
CT |
|
X |
|
X |
X |
X |
Port C1 |
|
put Com- |
Input 13 |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
pare 1 |
|
25 |
18 |
10 |
13 |
|
PC2 (HS)/ICAP2_B |
I/O |
CT |
HS |
X |
X |
|
|
X |
X |
Port C2 |
Timer B Input Capture 2 |
|||||
26 |
19 |
11 |
14 |
|
PC3 (HS)/ICAP1_B |
I/O |
CT |
HS |
X |
X |
|
|
X |
X |
Port C3 |
Timer B Input Capture 1 |
|||||
|
|
|
|
PC4/MISO/ICCDA- |
|
|
|
|
|
|
|
|
|
|
|
SPI Master |
ICC Data In- |
||||
27 |
20 |
12 |
15 |
I/O |
CT |
|
X |
X |
|
|
X |
X |
Port C4 |
|
In / Slave |
||||||
TA |
|
|
|
|
put |
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Out Data |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SPI Master |
ADC Analog |
28 |
21 |
13 |
16 |
|
PC5/MOSI/AIN14 |
I/O |
CT |
|
X |
X |
|
X |
X |
X |
Port C5 |
|
Out / Slave |
||||
|
|
|
|
Input 14 |
|||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
In Data |
|
29 |
22 |
14 |
17 |
|
PC6/SCK/ICCCLK |
I/O |
CT |
|
X |
X |
|
|
X |
X |
Port C6 |
|
SPI Serial |
ICC Clock |
|||
|
|
|
|
|
Clock |
Output |
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SPI Slave |
ADC Analog |
30 |
23 |
15 |
18 |
|
PC7/SS/AIN15 |
I/O |
CT |
|
X |
X |
|
X |
X |
X |
Port C7 |
|
Select (ac- |
||||
|
|
|
|
Input 15 |
|||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
tive low) |
|
31 |
24 |
16 |
19 |
|
PA3 (HS) |
I/O |
CT |
HS |
X |
|
ei0 |
|
X |
X |
Port A3 |
|
|
||||
32 |
25 |
|
|
|
VDD_1 |
S |
|
|
|
|
|
|
|
|
Digital Main Supply Voltage |
||||||
33 |
26 |
|
|
|
VSS_1 |
S |
|
|
|
|
|
|
|
|
Digital Ground Voltage |
|
|||||
34 |
27 |
17 |
20 |
|
PA4 (HS) |
I/O |
CT |
HS |
X |
X |
|
|
X |
X |
Port A4 |
|
|
||||
35 |
28 |
|
|
|
PA5 (HS) |
I/O |
CT |
HS |
X |
X |
|
|
X |
X |
Port A5 |
|
|
||||
36 |
29 |
18 |
21 |
|
PA6 (HS) |
I/O |
CT |
HS |
X |
|
|
|
T |
|
Port A6 1) |
|
|
||||
37 |
30 |
19 |
22 |
|
PA7 (HS) |
I/O |
CT |
HS |
X |
|
|
|
T |
|
Port A7 1) |
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Must be tied low. In the flash pro- |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gramming mode, this pin acts as the |
|||
38 |
31 |
20 |
23 |
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VPP /ICCSEL |
I |
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programming voltage input VPP. See |
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Section 12.9.2 for more details. High |
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voltage must not be applied to ROM |
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devices. |
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39 |
32 |
21 |
24 |
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I/O |
CT |
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Top priority non maskable interrupt. |
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RESET |
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40 |
33 |
22 |
25 |
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VSS_2 |
S |
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Digital Ground Voltage |
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41 |
34 |
23 |
26 |
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OSC2 |
O |
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Resonator oscillator inverter output |
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42 |
35 |
24 |
27 |
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OSC1 |
I |
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External clock input or Resonator os- |
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cillator inverter input |
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43 |
36 |
25 |
28 |
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VDD_2 |
S |
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Digital Main Supply Voltage |
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44 |
37 |
26 |
29 |
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PE0/TDO |
I/O |
CT |
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X |
X |
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X |
X |
Port E0 |
SCI Transmit Data Out |
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1 |
38 |
27 |
30 |
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PE1/RDI |
I/O |
CT |
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X |
X |
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X |
X |
Port E1 |
SCI Receive Data In |
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2 |
39 |
28 |
31 |
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PB0 |
I/O |
CT |
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X |
ei2 |
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X |
X |
Port B0 |
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3 |
40 |
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PB1 |
I/O |
CT |
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X |
ei2 |
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X |
X |
Port B1 |
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4 |
41 |
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PB2 |
I/O |
CT |
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X |
ei2 |
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X |
X |
Port B2 |
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5 |
42 |
29 |
32 |
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PB3 |
I/O |
CT |
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X |
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ei2 |
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X |
X |
Port B3 |
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Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
11/161
ST72324
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.
2.In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V DD are not implemented). See See “I/O PORTS” on page 45. and Section 12.8 I/O PORT PIN CHARACTERISTICS for more details.
3.OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for more details.
4.On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
5.In ROM devices, there is no weak pull-up on PB4.
12/161
ST72324
3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128 bytes of register locations, up to 1024 bytes of RAM and up to 32 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.
Figure 5. Memory Map
The highest address bytes contain the user reset and interrupt vectors.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the device.
0000h |
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0080h |
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HW Registers |
Short Addressing |
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(see Table 2) |
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007Fh |
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RAM (zero page) |
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00FFh |
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0080h |
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RAM |
0100h |
256 Bytes Stack |
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(1024, |
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01FFh |
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512 or 384 Bytes) |
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087Fh |
0200h |
16-bit Addressing |
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0880h |
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Reserved |
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RAM |
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027Fh |
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0FFFh |
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or 047Fh |
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1000h |
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Program Memory |
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8000h |
32 KBytes |
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(32K, 16K or 8K) |
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C000h |
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FFDFh |
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16 KBytes |
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FFE0h |
Interrupt & Reset Vectors |
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E000h |
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8 Kbytes |
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(see Table 7) |
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FFFFh |
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FFFFh |
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13/161
ST72324
Table 2. Hardware Register Map
Address |
Block |
Register |
Register Name |
Reset |
Remarks |
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Label |
Status |
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0000h |
Port A2) |
PADR |
Port A Data Register |
00h1) |
R/W |
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0001h |
PADDR |
Port A Data Direction Register |
00h |
R/W |
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0002h |
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PAOR |
Port A Option Register |
00h |
R/W |
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0003h |
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PBDR |
Port B Data Register |
00h1) |
R/W |
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0004h |
Port B |
PBDDR |
Port B Data Direction Register |
00h |
R/W |
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0005h |
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PBOR |
Port B Option Register |
00h |
R/W |
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0006h |
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PCDR |
Port C Data Register |
00h1) |
R/W |
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0007h |
Port C |
PCDDR |
Port C Data Direction Register |
00h |
R/W |
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0008h |
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PCOR |
Port C Option Register |
00h |
R/W |
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0009h |
Port D2) |
PDDR |
Port D Data Register |
00h1) |
R/W |
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000Ah |
PDDDR |
Port D Data Direction Register |
00h |
R/W |
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000Bh |
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PDOR |
Port D Option Register |
00h |
R/W |
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000Ch |
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PEDR |
Port E Data Register |
00h1) |
R/W |
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000Dh |
Port E2) |
PEDDR |
Port E Data Direction Register |
00h |
R/W2) |
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000Eh |
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PEOR |
Port E Option Register |
00h |
R/W2) |
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000Fh |
Port F 2) |
PFDR |
Port F Data Register |
00h1) |
R/W |
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0010h |
PFDDR |
Port F Data Direction Register |
00h |
R/W |
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0011h |
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PFOR |
Port F Option Register |
00h |
R/W |
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0012h |
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to |
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Reserved Area (15 Bytes) |
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0020h |
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0021h |
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SPIDR |
SPI Data I/O Register |
xxh |
R/W |
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0022h |
SPI |
SPICR |
SPI Control Register |
0xh |
R/W |
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0023h |
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SPICSR |
SPI Control/Status Register |
00h |
R/W |
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0024h |
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ISPR0 |
Interrupt Software Priority Register 0 |
FFh |
R/W |
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0025h |
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ISPR1 |
Interrupt Software Priority Register 1 |
FFh |
R/W |
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0026h |
ITC |
ISPR2 |
Interrupt Software Priority Register 2 |
FFh |
R/W |
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0027h |
ISPR3 |
Interrupt Software Priority Register 3 |
FFh |
R/W |
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0028h |
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EICR |
External Interrupt Control Register |
00h |
R/W |
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0029h |
FLASH |
FCSR |
Flash Control/Status Register |
00h |
R/W |
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002Ah |
WATCHDOG |
WDGCR |
Watchdog Control Register |
7Fh |
R/W |
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002Bh |
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SICSR |
System Integrity Control/Status Register |
000x 000x b |
R/W |
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002Ch |
MCC |
MCCSR |
Main Clock Control / Status Register |
00h |
R/W |
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002Dh |
MCCBCR |
Main Clock Controller: Beep Control Register |
00h |
R/W |
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002Eh |
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to |
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Reserved Area (3 Bytes) |
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0030h |
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14/161
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ST72324 |
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Address |
Block |
Register |
Register Name |
Reset |
Remarks |
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Label |
Status |
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0031h |
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TACR2 |
Timer A Control Register 2 |
00h |
R/W |
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0032h |
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TACR1 |
Timer A Control Register 1 |
00h |
R/W |
|
0033h |
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TACSR |
Timer A Control/Status Register5 |
xxx0 x0xx b |
R/W |
|
0034h |
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TAIC1HR |
Timer A Input Capture 1 High Register |
xxh |
Read Only |
|
0035h |
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TAIC1LR |
Timer A Input Capture 1 Low Register |
xxh |
Read Only |
|
0036h |
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TAOC1HR |
Timer A Output Compare 1 High Register |
80h |
R/W |
|
0037h |
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TAOC1LR |
Timer A Output Compare 1 Low Register |
00h |
R/W |
|
0038h |
TIMER A |
TACHR |
Timer A Counter High Register |
FFh |
Read Only |
|
0039h |
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TACLR |
Timer A Counter Low Register |
FCh |
Read Only |
|
003Ah |
|
TAACHR |
Timer A Alternate Counter High Register |
FFh |
Read Only |
|
003Bh |
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TAACLR |
Timer A Alternate Counter Low Register |
FCh |
Read Only |
|
003Ch |
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TAIC2HR |
Reserved3 |
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003Dh |
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TAIC2LR |
Reserved3 |
|
Write Only4 |
|
003Eh |
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TAOC2HR |
Timer A Output Compare 2 High Register |
80h |
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003Fh |
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TAOC2LR |
Timer A Output Compare 2 Low Register |
00h |
Write Only4 |
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0040h |
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Reserved Area (1 Byte) |
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0041h |
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TBCR2 |
Timer B Control Register 2 |
00h |
R/W |
|
0042h |
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TBCR1 |
Timer B Control Register 1 |
00h |
R/W |
|
0043h |
|
TBCSR |
Timer B Control/Status Register |
xxxx x0xx b |
R/W |
|
0044h |
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TBIC1HR |
Timer B Input Capture 1 High Register |
xxh |
Read Only |
|
0045h |
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TBIC1LR |
Timer B Input Capture 1 Low Register |
xxh |
Read Only |
|
0046h |
|
TBOC1HR |
Timer B Output Compare 1 High Register |
80h |
R/W |
|
0047h |
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TBOC1LR |
Timer B Output Compare 1 Low Register |
00h |
R/W |
|
0048h |
TIMER B |
TBCHR |
Timer B Counter High Register |
FFh |
Read Only |
|
0049h |
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TBCLR |
Timer B Counter Low Register |
FCh |
Read Only |
|
004Ah |
|
TBACHR |
Timer B Alternate Counter High Register |
FFh |
Read Only |
|
004Bh |
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TBACLR |
Timer B Alternate Counter Low Register |
FCh |
Read Only |
|
004Ch |
|
TBIC2HR |
Timer B Input Capture 2 High Register |
xxh |
Read Only |
|
004Dh |
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TBIC2LR |
Timer B Input Capture 2 Low Register |
xxh |
Read Only |
|
004Eh |
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TBOC2HR |
Timer B Output Compare 2 High Register |
80h |
R/W |
|
004Fh |
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TBOC2LR |
Timer B Output Compare 2 Low Register |
00h |
R/W |
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0050h |
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SCISR |
SCI Status Register |
C0h |
Read Only |
|
0051h |
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SCIDR |
SCI Data Register |
xxh |
R/W |
|
0052h |
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SCIBRR |
SCI Baud Rate Register |
00h |
R/W |
|
0053h |
SCI |
SCICR1 |
SCI Control Register 1 |
x000 0000b |
R/W |
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0054h |
SCICR2 |
SCI Control Register 2 |
00h |
R/W |
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0055h |
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SCIERPR |
SCI Extended Receive Prescaler Register |
00h |
R/W |
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0056h |
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Reserved area |
--- |
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0057h |
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SCIETPR |
SCI Extended Transmit Prescaler Register |
00h |
R/W |
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0070h |
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ADCCSR |
Control/Status Register |
00h |
R/W |
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0071h |
ADC |
ADCDRH |
Data High Register |
00h |
Read Only |
|
0072h |
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ADCDRL |
Data Low Register |
00h |
Read Only |
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0073h |
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Reserved Area (13 Bytes) |
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007Fh |
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Legend: x=undefined, R/W=read/write
15/161
ST72324
Notes:
1.The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2.The bits associated with unavailable pins must always keep their reset value.
3.These registers and the ICF2 and OCF2 flags are not present in the ST72324 but are present in the emulator. For compatibility with the emulator, it is recommended to perform a dummy access (read or write) to the TAIC2LR and TAOC2LR registers to clear the interrupt flags.
4.The registers can be written, but reading them will return undefined values.
5.Bits 2 and 4 of this register (ICF2 and OCF2) are forced by hardware to 0. Consequently, the corresponding interrupts cannot be used.
16/161
ST72324
4 FLASH PROGRAM MEMORY
4.1 Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply.
The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).
The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.
4.2 Main Features
■Three Flash programming modes:
–Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased.
–ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board.
–IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running.
■ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM
■Read-out protection against piracy
■Register Access Security System (RASS) to prevent accidental programming or erasing
4.3 Structure
The Flash memory is organised in sectors and can be used for both code and data storage.
Figure 6. Memory Map and Sector Address
Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 6). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).
Table 3. Sectors available in Flash devices
Flash Size (bytes) |
Available Sectors |
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4K |
Sector 0 |
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8K |
Sectors 0,1 |
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> 8K |
Sectors 0,1, 2 |
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4.3.1 Read-out Protection
Read-out protection, when selected, makes it impossible to extract the memory content from the microcontroller, thus preventing piracy. Even ST cannot access the user code.
In flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed.
Read-out protection selection depends on the device type:
–In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
–In ROM devices it is enabled by mask option specified in the Option List.
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4K |
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8K |
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10K |
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16K |
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24K |
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32K |
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48K |
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60K |
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FLASH |
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MEMORY SIZE |
1000h |
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3FFFh |
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7FFFh |
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9FFFh |
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D7FFh |
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24 Kbytes |
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52 Kbytes |
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EFFFh |
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FFFFh |
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17/161
ST72324
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC Interface
ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 7). These pins are:
–RESET: device reset
–VSS: device power supply ground
–ICCCLK: ICC output serial clock pin
–ICCDATA: ICC input/output serial data pin
–ICCSEL/VPP: programming voltage
–OSC1(or OSCIN): main clock input for external source (optional)
–VDD: application board power supply (optional, see Figure 7, Note 3)
Figure 7. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
OPTIONAL
(See Note 3)
APPLICATION CL2
POWER SUPPLY
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OSC2 |
V |
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DD |
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OPTIONAL |
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(See Note 4) |
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10kΩ |
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CL1 |
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SS |
ICCSEL/VPP |
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RESET |
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ICCCLK |
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ICCDATA |
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OSC1 |
V |
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ICC CONNECTOR
HE10 CONNECTOR TYPE
APPLICATION
RESET SOURCE
See Note 2
See Note 1
APPLICATION
I/O
Notes:
1.If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.
2.During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.
3.The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.
4.Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.
18/161
ST72324
FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (In-Circuit Programming)
To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool.
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).
When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 7). For more details on the pin locations, refer to the device pinout description.
4.6 IAP (In-Application Programming)
This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).
This mode is fully controlled by user software. This allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
4.7 Related Documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.7.1 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 0000 0000 (00h)
7 |
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This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations. Flash Control/Status Register Address and Reset Value
Address |
Register |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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(Hex.) |
Label |
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0029h |
FCSR |
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Reset Value |
0 |
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19/161
ST72324
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.
5.2 MAIN FEATURES
■Enable executing 63 basic instructions
■Fast 8-bit by 8-bit multiply
■17 main addressing modes (with indirect addressing mode)
■Two 8-bit index registers
■16-bit stack pointer
■Low power HALT and WAIT modes
■Priority maskable hardware interrupts
■Non-maskable software/hardware interrupts
5.3 CPU REGISTERS
The 6 CPU registers shown in Figure 8 are not present in the memory mapping and are accessed by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.
Index Registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
Figure 8. CPU Registers
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7 |
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0 |
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ACCUMULATOR |
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RESET VALUE = XXh |
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7 |
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0 |
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X INDEX REGISTER |
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RESET VALUE = XXh |
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7 |
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0 |
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Y INDEX REGISTER |
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RESET VALUE = XXh |
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PCH |
8 |
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7 |
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PCL |
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PROGRAM COUNTER |
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RESET VALUE = RESET VECTOR @ FFFEh-FFFFh |
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7 |
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1 |
1 |
I1 |
H |
I0 |
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C |
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CONDITION CODE REGISTER |
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RESET VALUE = 1 |
1 |
1 X |
1 X |
X |
X |
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15 |
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STACK POINTER |
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7 |
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RESET VALUE = STACK HIGHER ADDRESS |
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X = Undefined Value
20/161
ST72324
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Reset Value: 111x1xxx
7 |
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0 |
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1 |
1 |
I1 |
H |
I0 |
N |
Z |
C |
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The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic Management Bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.
0:No half carry has occurred.
1:A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the result 7th bit.
0:The result of the last operation is positive or null.
1:The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.
0:The result of the last operation is different from zero.
1:The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.
0:No overflow or underflow has occurred.
1:An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority |
I1 |
I0 |
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Level 0 |
(main) |
1 |
0 |
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Level 1 |
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1 |
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Level 2 |
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0 |
0 |
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Level 3 |
(= interrupt disable) |
1 |
1 |
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These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.
See the interrupt management chapter for more details.
21/161
ST72324
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 FFh
15 |
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8 |
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0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
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7 |
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0 |
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SP7 |
SP6 |
SP5 |
SP4 |
SP3 |
SP2 |
SP1 |
SP0 |
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The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
Figure 9. Stack Manipulation Example
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 9.
–When an interrupt is received, the SP is decremented and the context is pushed on the stack.
–On return from interrupt, the SP is incremented and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
CALL |
Interrupt |
PUSH Y |
POP Y |
IRET |
RET |
Subroutine |
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PCH |
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Stack Higher Address = 01FFh
Stack Lower Address = 0100h
22/161
ST72324
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 11.
For more details, refer to dedicated parametric section.
Main features
■Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator)
■Reset Sequence Manager (RSM)
■Multi-Oscillator Clock Management (MO)
–5 Crystal/Ceramic resonator oscillators
–1 Internal RC oscillator
■System Integrity Management (SI)
–Main supply Low voltage detection (LVD)
–Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply
–Clock Security System (CSS) with Clock Filter and Backup Safe Oscillator (enabled by option byte)
Figure 11. Clock, Reset and Supply Block Diagram
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL
is disabled, then fOSC2 = fOSC/2.
Caution: The PLL is not recommended for applications where timing accuracy is required. See “PLL Characteristics” on page 128.
Figure 10. PLL Block Diagram
fOSC |
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PLL x 2 |
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/ 2 |
1 |
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PLL OPTION BIT
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SYSTEM INTEGRITY MANAGEMENT |
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OSC2 |
MULTI- |
fOSC |
fOSC2 |
CLOCK |
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MAIN CLOCK |
fCPU |
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OSCILLATOR |
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FILTER |
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MANAGER |
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AVD AVD LVD |
0 CSS CSS WDG |
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RF |
IE |
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DETECTOR |
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VDD |
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23/161 |
ST72324
6.2 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by three different source types coming from the multioscillator block:
■an external source
■4 crystal or ceramic resonator oscillators
■an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 4. Refer to the electrical characteristics section for more details.
Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected.
External Clock Source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.
Note: External clock source is not supported with the PLL enabled.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 14.1 on page 149 for more details on the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.
Internal RC Oscillator
This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing.
In this mode, the two oscillator pins have to be tied to ground.
Table 4. ST7 Clock Sources
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Hardware Configuration |
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External Clock |
ST7 |
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OSC1 |
OSC2 |
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EXTERNAL |
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SOURCE |
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Resonators |
ST7 |
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OSC1 |
OSC2 |
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Crystal/Ceramic |
CL1 |
CL2 |
LOAD |
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CAPACITORS |
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Internal RC Oscillator |
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OSC1 |
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24/161
ST72324
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 13:
■External RESET source pulse
■Internal LVD RESET (Low Voltage Detection)
■Internal WATCHDOG RESET
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases as shown in Figure 12:
■Active Phase depending on the RESET source
■256 or 4096 CPU clock cycle delay (selected by option byte)
■RESET vector fetch
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application (see Section 14.1 on page 149).
Figure 13. Reset Block Diagram
The RESET vector fetch phase duration is 2 clock cycles.
Figure 12. RESET Sequence Phases
RESET
Active Phase |
INTERNAL RESET |
FETCH |
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256 or 4096 CLOCK CYCLES |
VECTOR |
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6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See “CONTROL PIN CHARACTERISTICS” on page 138 for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 14). This de-
tection is asynchronous and therefore the MCU can enter reset state even in HALT mode.
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VDD |
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RON |
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RESET |
Filter |
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INTERNAL |
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PULSE |
WATCHDOG RESET |
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GENERATOR |
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25/161
ST72324
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.
If the external RESET pulse is shorter than
tw(RSTL)out (see short ext. Reset in Figure 14), the signal on the RESET pin may be stretched. Other-
wise the delay will not be applied (see long ext. Reset in Figure 14). Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least
tw(RSTL)out.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. (see “OPERATING CONDITIONS” on page 115 )
Figure 14. RESET Sequences
A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■Power-On RESET
■Voltage Drop RESET
The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or VDD<VIT- (falling edge) as shown in Figure 14.
The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 14.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.
VDD
VIT+(LVD)
VIT-(LVD)
LVD |
SHORT EXT. |
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RESET |
RESET |
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RUN |
RUN |
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ACTIVE |
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WATCHDOG |
RESET |
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RESET |
RUN |
RUN |
RUN |
ACTIVE |
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ACTIVE |
PHASE |
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PHASE |
tw(RSTL)out |
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tw(RSTL)out |
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th(RSTL)in |
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th(RSTL)in |
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tw(RSTL)out |
DELAY
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU)
VECTOR FETCH
26/161
ST72324
6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains the Low Voltage Detector (LVD), Auxiliary Voltage Detector (AVD) functions and Clock Security System (CSS). It is managed by the SICSR register.
6.4.1 Low Voltage Detector (LVD)
Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes:
–under full software control
–in static safe reset
The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when VDD is below:
–VIT+ when VDD is rising
–VIT- when VDD is falling
The LVD function is illustrated in Figure 15.
The voltage threshold can be configured by option byte to be low, medium or high.
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.
Notes:
The LVD allows the device to be used without any external RESET circuitry.
If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed.
The LVD is an optional function which can be selected by option byte.
Figure 15. Low Voltage Detector vs Reset
VDD |
Vhys |
VIT+ |
VIT- |
RESET |
27/161
ST72324
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and
VIT+(AVD) reference value and the VDD main supply. The VIT- reference value for falling voltage is
lower than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis).
The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only.
Caution: The AVD function is active only if the LVD is enabled through the option byte.
6.4.2.1 Monitoring the VDD Main Supply
The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see Section 14.1 on page 149).
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles).
Figure 16. Using the AVD to Monitor VDD
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 16.
The interrupt on the rising edge is used to inform the application that the VDD warning state is over.
If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached.
If trv is greater than 256 or 4096 cycles then:
– If the AVD interrupt is enabled before the
VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is reached.
–If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD interrupt will occur.
VDD |
Early Warning Interrupt |
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(Power has dropped, MCU not not yet in reset)
Vhyst
VIT+(AVD)
VIT-(AVD)
VIT+(LVD)
VIT-(LVD) |
trv VOLTAGE RISE TIME |
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AVDF bit |
0 |
1 |
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RESET VALUE |
1 |
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0 |
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS |
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INTERRUPT PROCESS |
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LVD RESET
28/161
ST72324
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Clock Security System (CSS)
The Clock Security System (CSS) protects the ST7 against breakdowns, spikes and overfrequencies occurring on the main clock source (fOSC). It is based on a clock filter and a clock detection control with an internal safe oscillator (fSFOSC).
Caution: The CSS function is not guaranteed. Refer to Section 15
6.4.3.1 Clock Filter Control
The PLL has an integrated glitch filtering capability making it possible to protect the internal clock from overfrequencies created by individual spikes. This feature is available only when the PLL is enabled. If glitches occur on fOSC (for example, due to loose connection or noise), the CSS filters these automatically, so the internal CPU frequency (fCPU) continues deliver a glitch-free signal (see Figure 17).
6.4.3.2 Clock detection Control
If the clock signal disappears (due to a broken or disconnected resonator...), the safe oscillator de-
livers a low frequency clock signal (fSFOSC) which allows the ST7 to perform some rescue opera-
tions.
Automatically, the ST7 clock source switches back
from the safe oscillator (fSFOSC) if the main clock source (fOSC) recovers.
When the internal clock (fCPU) is driven by the safe
oscillator (fSFOSC), the application software is notified by hardware setting the CSSD bit in the SIC-
SR register. An interrupt can be generated if the CSSIE bit has been previously set.
These two bits are described in the SICSR register description.
6.4.4 Low Power Modes
Mode |
Description |
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WAIT |
No effect on SI. CSS and AVD interrupts |
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cause the device to exit from Wait mode. |
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previous CSS configuration resumes when |
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“exit from HALT mode” capability or from |
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the counter reset value when the MCU is |
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woken up by a RESET. |
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6.4.4.1 Interrupts
The CSS or AVD interrupt events generate an interrupt if the corresponding Enable Control Bit (CSSIE or AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
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Event |
Enable |
Exit |
Exit |
Interrupt Event |
Control |
from |
from |
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Bit |
Wait |
Halt |
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CSS event detection |
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(safe oscillator acti- |
CSSD |
CSSIE |
Yes |
No |
vated as main clock) |
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AVD event |
AVDF |
AVDIE |
Yes |
No |
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Figure 17. Clock Filter Function
Clock Filter Function |
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PLL ON |
fOSC2 |
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fCPU |
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Clock Detection Function |
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fCPU |
29/161
ST72324
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.5 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
Reset Value: 000x 000x (00h)
7 |
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AVD |
AVD |
LVD |
0 |
CSS |
CSS |
WDG |
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IE |
F |
RF |
IE |
D |
RF |
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Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine.
0:AVD interrupt disabled
1:AVD interrupt enabled
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. Refer to Figure 16 and to Section 6.4.2.1 for additional details.
0:VDD over VIT+(AVD) threshold
1:VDD under VIT-(AVD) threshold
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.
Bits 3 = Reserved, must be kept cleared.
Bit 2 = CSSIE Clock security syst. interrupt enable
This bit enables the interrupt when a disturbance is detected by the Clock Security System (CSSD bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the CSSIE bit has no effect.
Bit 1 = CSSD Clock security system detection
This bit indicates that the safe oscillator of the Clock Security System block has been selected by hardware due to a disturbance on the main clock
signal (fOSC). It is set by hardware and cleared by reading the SICSR register when the original oscil-
lator recovers.
0:Safe oscillator is not active
1:Safe oscillator has been activated
When the CSS is disabled by OPTION BYTE, the CSSD bit value is forced to 0.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is given by the following table.
RESET Sources |
LVDRF |
WDGRF |
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External |
RESET |
pin |
0 |
0 |
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Watchdog |
0 |
1 |
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LVD |
1 |
X |
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Application notes
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can not.
CAUTION: When the LVD is not activated with the associated option byte, the WDGRF flag can not be used in the application.
30/161