SGS Thomson Microelectronics ST72T331N4, ST72T331N2, ST72T331J4, ST72T331J2, ST72331N4 Datasheet

ST72E331

ST72T331

8-BIT MCU WITH 8 TO 16K OTP/EPROM, 256 EEPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS

DATASHEET

■User Program Memory (OTP/EPROM): 8 to 16K bytes

■User EEPROM: 256 bytes

■Data RAM: 384 to 512 bytes including 256 bytes of stack

■Master Reset and Power-On Reset

■Low Voltage Detector (LVD) Reset option

■Run and Power Saving modes

■44 or 32 multifunctional bidirectional I/O lines:

±15 or 9 programmable interrupt inputs

±8 or 4 high sink outputs

±8 or 6 analog alternate inputs

±13 alternate functions

±EMI filtering

■Software or Hardware Watchdog (WDG)

■Two 16-bit Timers, each featuring:

±2 Input Captures 1)

±2 Output Compares 1)

±External Clock input (on Timer A)

±PWM and Pulse Generator modes

■Synchronous Serial Peripheral Interface (SPI)

■Asynchronous Serial Communications Interface (SCI)

■8-bit ADC with 8 channels 2)

■8-bit Data Manipulation

■63 basic Instructions and 17 main Addressing Modes

■8 x 8 Unsigned Multiply Instruction

■True Bit Manipulation

■Complete Development Support on DOS/ WINDOWSTM Real-Time Emulator

■Full Software Package on DOS/WINDOWSTM (C-Compiler, Cross-Assembler, Debugger)

Device Summary

PSDIP42

CSDIP42W

PSDIP56

CSDIP56W

TQFP64

TQFP44

(See ordering information at the end of datashee

Notes:

1.One only on Timer A.

2.Six channels only for ST72T331J.

Features	ST72T331J2	ST72T331J4	ST72T331N2	ST72T331N4
Program Memory - bytes	8K	16K	8K	16K
EEPROM - bytes			256
RAM (stack) - bytes	384 (256)	512 (256)	384 (256)	512 (256)
Peripherals	Watchdog, Timers, SPI, SCI, ADC and optional Low Voltage Detector Reset
Operating Supply			3 to 5.5 V
CPU Frequency		8MHz max (16MHz oscillator) - 4MHz max over 85°C
Temperature Range		- 40°C to + 125°C
Package	TQFP44 - SDIP42		TQFP64 - SDIP56

Note: The ROM versions are supported by the ST72334 family.

Rev. 1.7

September 1999

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Table of Contents

ST72E331/ST72T331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.5 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
2.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
2.2	MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
2.3	CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . .		18

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.4 Low Voltage Detector Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4.2 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2 EEPROM (EEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.3 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95. . . 37

4.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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4.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.4.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.6.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.7 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.7.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.7.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	85
5.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	85

5.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3 RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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ST72E331 ST72T331

6.4 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.5 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.6 PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

7.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.2 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

8 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST72T331 HCMOS Microcontroller Unit (MCU) is a member of the ST7 family. The device is based on an industry-standard 8-bit core and features an enhanced instruction set. The device is normally operated at a 16 MHz oscillator frequency. Under software control, the ST72T331 may be placed in either Wait, Slow or Halt modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8-bit data management, the ST72T331 features true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes on the whole memory. The device includes a low consumption and

Figure 1. ST72T331 Block Diagram

ST72E331 ST72T331

fast start on-chip oscillator, CPU, program memory (OTP/EPROM versions), EEPROM, RAM, 44 (QFP64 and SDIP56) or 32 (QFP44 and SDIP42) I/O lines, a Low Voltage Detector (LVD) and the following on-chip peripherals: Analog-to-Digital converter (ADC) with 8 (QFP64, SDIP56) or 6 (QFP44, SDIP42) multiplexed analog inputs, industry standard synchronous SPI and asynchronous SCI serial interfaces, digital Watchdog, two independent 16-bit Timers, one featuring an External Clock Input, and both featuring Pulse Generator capabilities, 2 Input Captures and 2 Output Compares (only 1 Input Capture and 1 Output Compare on Timer A).

		Internal
	OSCIN	CLOCK
		OSC
	OSCOUT
	RESET	CONTROL
		AND LVD
		8-BIT CORE
		ALU
		PROGRAM
		MEMORY
		(8 - 16K Bytes)
		EEPROM
		(256 Bytes)
		RAM
		(384 - 512 Bytes)
	PF0 -> PF2,4,6,7	PORT F
	(6 bits)
		TIMER A
	VDD	POWER
	VSS	SUPPLY

BUS DATA AND ADDRESS

	PORT A	PA0 -> PA7
		(8 bits for ST72T331N)
		(5 bits for ST72T331J)
	PORT B	PB0 -> PB7
		(8 bits for ST72T331N)
	TIMER B	(5 bits for ST72T331J)
	PORT C	PC0 -> PC7
		(8 bits)
	SPI
	PORT D
		PD0 -> PD7
	8-BIT ADC	(8 bits for ST72T331N)
		(6 bits for ST72T331J)
	PORT E
		PE0 -> PE7
	SCI	(6 bits for ST72T331N)
		(2 bits for ST72T331J)
	WATCH DOG	VDDA
		VSSA

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ST72E331 ST72T331

1.2 PIN DESCRIPTION

Figure 2. 64-Pin Thin QFP Package Pinout

1)

NC

NC

PE1/RDI

PE0/TDO

OSCIN

OSCOUT

NC

NC

RESET

PP

PA7

PA6

PA5

PA4

V

V

TEST/V

DD_2

SS2_

	1	64 63 62 6160 59 58 5756 55 54 53 52 51 50 49									VSS_1
PE4										48
PE5	2									47	VDD _1
PE6	3									(EI0) 46	PA3
PE7	4									(EI0) 45	PA2
PB0	5	(EI2)								(EI0) 44	PA1
PB1	6	(EI2)								(EI0) 43	PA0
PB2	7	(EI2)								42	PC7/SS
PB3	8	(EI2)								41	PC6/SCK
PB4	9	(EI3)								40	PC5/MOSI
PB5	10	(EI3)								39	PC4/MISO
PB6	11	(EI3)								38	PC3/ICAP1_B
PB7	12	(EI3)								37	PC2/ICAP2_B
AIN0/PD0	13									36	PC1/OCMP1_B
AIN1/PD1	14						(EI1)	(EI1)	(EI1)	35	PC0/OCMP2_B
AIN2/PD2	15									34	VSS_0
AIN3/PD3	16									33	VDD _0
	17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
				DDA	SSA	DD_3	SS_3	PF1	PF2 NC OCMP1 A/PF4	NC ICAP1 A/PF6 EXTCLK A/PF7
		AIN4/PD4 AIN5/PD5	AIN6/PD6	AIN7/PD7 V	V	V	V CLKOUT/PF0

1.V on EPR OM/OTP only PP

Figure 4. 44-Pin Thin QFP Package Pinout

						1)
	PE0/TD0 V	OSCIN	OSCOUT		RESET	PP	PA7	PA6	PA5	PA4
				V		TEST/V
	DD2			SS2
PE1/RDI	44 43 42 41 40 39 38 37 36 35 34										VSS_1
	1									33
PB0	2 (EI2)									32	VDD_1
PB1	3 (EI2)								(EI0) 31		PA3
PB2	4 (EI2)									30	PC7/SS
PB3	5 (EI2)									29	PC6/SCK
PB4	6 (EI3)									28	PC5/MOSI
AIN0/PD0	7									27	PC4/MISO
AIN1/PD1	8									26	PC3/ICAP1_B
AIN2/PD2	9									25	PC2/ICAP2_B
AIN3/PD3	10		(EI1)	(EI1)	(EI1)					24	PC1/OCMP1_B
AIN4/PD4	11									23	PC0/OCMP2_B
	12 13 14 15 16 17 18 19 20 21 22
	DDA	SSA	CLKOUT/PF0	PF1	PF2	OCMP1 A/PF4	ICAP1 A/PF6	EXTCLK A/PF7	DD0	SS0
	AIN5/PD5 V	V							V	V

1.V on EPROM/OTP only PP

Figure 3. 56-Pin Shrink DIP Package Pinout					Figure 5. 42-Pin Shrink DIP Package Pinout
PB4	1 (EI3)	(EI2) 56	PB3
PB5	2 (EI3)	(EI2) 55	PB2
PB6	3 (EI3)	(EI2) 54	PB1
PB7	4 (EI3)	(EI2) 53	PB0		PB4	1 (EI3)	(EI2) 42	PB3
AIN0/PD0	5	52	PE7		AIN0/PD0	2	(EI2) 41	PB2
AIN1/PD1	6	51	PE6		AIN1/PD1	3	(EI2) 40	PB1
AIN2/PD2	7	50	PE5		AIN2/PD2	4	(EI2) 39	PB0
AIN3/PD3	8	49	PE4		AIN3/PD3	5	38	PE1/RDI
AIN4/PD4	9	48	PE1/RDI
					AIN4/PD4	6	37	PE0/TD0
AIN5/PD5	10	47	PE0/TD0		AIN5/PD5	7	36	VDD_2
AIN6/PD6	11	46	VDD _2		VDDA	8	35	OSCIN
AIN7/PD7	12	45	OSCIN		VSSA	9	34	OSCOUT
VDD A	13	44	OSCOUT		CLKOUT/PF0	10 (EI1)	33	VSS_2
VSSA
	14	43	V	SS_2	PF1	11 (EI1)	32	RESET
CLKOUT/PF0	15 (EI1)	42
			RESET		PF2	12 (EI1)	31	TEST/V	PP	1)
PF1	16 (EI1)	41		1)
					OCMP1_A/PF4	13	30	PA7
PF2			TEST/VPP
	17 (EI1)	40	PA7		ICAP1_A/PF6	14	29	PA6
OCMP1_A/PF4	18	39	PA6
					EXTCLK_A/PF7	15	28	PA5
ICAP1_A/PF6	19	38	PA5
					PC0/OCMP2_B	16	27	PA4
EXTCLK_A/PF7	20	37	PA4
					PC1/OCMP1_B	17	26	VSS_1
VDD_0	21	36	VSS_1
					PC2/ICAP2_B	18	25	VDD_1
VSS_0	22	35	VDD_1
					PC3/ICAP1_B	19	(EI0)24	PA3
PC0/OCMP2_B	23	(EI0) 34	PA3
					PC4/MISO	20	23	PC7/SS
PC1/OCMP1_B	24	(EI0) 33	PA2
					PC5/MOSI	21	22	PC6/SCK
PC2/ICAP2_B	25	(EI0) 32	PA1
PC3/ICAP1_B	26	(EI0) 31	PA0
PC4/MISO	27	30	PC7/SS
PC5/MOSI	28	29	PC6/SCK
1. V on EPROM/OTP only					1. V on EPROM/OTP only
PP					PP

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						ST72E331 ST72T331
	Table 1. ST72T331Nx Pin Description
	Pin n°	Pin n°	Pin Name	Type	Description	Remarks
	QFP64 SDIP56
	1	49	PE4	I/O	Port E4	High Sink
	2	50	PE5	I/O	Port E5	High Sink
	3	51	PE6	I/O	Port E6	High Sink
	4	52	PE7	I/O	Port E7	High Sink
	5	53	PB0	I/O	Port B0	External Interrupt: EI2
	6	54	PB1	I/O	Port B1	External Interrupt: EI2
	7	55	PB2	I/O	Port B2	External Interrupt: EI2
	8	56	PB3	I/O	Port B3	External Interrupt: EI2
	9	1	PB4	I/O	Port B4	External Interrupt: EI3
	10	2	PB5	I/O	Port B5	External Interrupt: EI3
	11	3	PB6	I/O	Port B6	External Interrupt: EI3
	12	4	PB7	I/O	Port B7	External Interrupt: EI3
	13	5	PD0/AIN0	I/O	Port D0 or ADC Analog Input 0
	14	6	PD1/AIN1	I/O	Port D1 or ADC Analog Input 1
	15	7	PD2/AIN2	I/O	Port D2 or ADC Analog Input 2
	16	8	PD3/AIN3	I/O	Port D3 or ADC Analog Input 3
	17	9	PD4/AIN4	I/O	Port D4 or ADC Analog Input 4
	18	10	PD5/AIN5	I/O	Port D5 or ADC Analog Input 5
	19	11	PD6/AIN6	I/O	Port D6 or ADC Analog Input 6
	20	12	PD7/AIN7	I/O	Port D7 or ADC Analog Input 7
	21	13	VDDA	S	Power Supply for analog peripheral (ADC)
	22	14	VSSA	S	Ground for analog peripheral (ADC)
	23		VDD_3	S	Main power supply
	24		VSS_3	S	Ground
	25	15	PF0/CLKOUT	I/O	Port F0 or CPU Clock Output	External Interrupt: EI1
	26	16	PF1	I/O	Port F1	External Interrupt: EI1
	27	17	PF2	I/O	Port F2	External Interrupt: EI1
	28		NC		Not Connected
	29	18	PF4/OCMP1_A	I/O	Port F4 or Timer A Output Compare 1
	30		NC		Not Connected
	31	19	PF6/ICAP1_A	I/O	Port F6 or Timer A Input Capture 1
	32	20	PF7/EXTCLK_A	I/O	Port F7 or External Clock on Timer A
	33	21	VDD_0	S	Main power supply
	34	22	VSS_0	S	Ground
	35	23	PC0/OCMP2_B	I/O	Port C0 or Timer B Output Compare 2
	36	24	PC1/OCMP1_B	I/O	Port C1 or Timer B Output Compare 1
	37	25	PC2/ICAP2_B	I/O	Port C2 or Timer B Input Capture 2
	38	26	PC3/ICAP1_B	I/O	Port C3 or Timer B Input Capture 1
	39	27	PC4/MISO	I/O	Port C4 or SPI Master In / Slave Out Data
	40	28	PC5/MOSI	I/O	Port C5 or SPI Master Out / Slave In Data
	41	29	PC6/SCK	I/O	Port C6 or SPI Serial Clock
	42	30	PC7/SS	I/O	Port C7 or SPI Slave Select
	43	31	PA0	I/O	Port A0	External Interrupt: EI0

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ST72E331 ST72T331

Pin n° Pin n°

Pin Name

QFP64 SDIP56

44	32	PA1
45	33	PA2
46	34	PA3
47	35	VDD_1
48	36	VSS_1
49	37	PA4
50	38	PA5
51	39	PA6
52	40	PA7
53	41	1)
		TEST/VPP

54 42 RESET

55NC

56NC

57	43	VSS_2
58	44	OSCOUT
59	45	OSCIN
60	46	VDD_2
61	47	PE0/TDO
62	48	PE1/RDI

63NC

64NC

Note 1: VPP on EPROM/OTP only.

	Type	Description	Remarks
	I/O	Port A1	External Interrupt: EI0
	I/O	Port A2	External Interrupt: EI0
	I/O	Port A3	External Interrupt: EI0
	S	Main power supply
	S	Ground
	I/O	Port A4	High Sink
	I/O	Port A5	High Sink
	I/O	Port A6	High Sink
	I/O	Port A7	High Sink
		Test mode pin . In the EPROM programming	This pin must be tied
	S	mode, this pin acts as the programming voltage
			low in user mode
		input VPP.
	I/O	Bidirectional. Active low. Top priority non maskable interrupt.
		Not Connected
		Not Connected
	S	Ground
	O	Input/Output Oscillator pin. These pins connect a parallel-resonant
	I	crystal, or an external source to the on-chip oscillator.
	S	Main power supply
	I/O	Port E1 or SCI Transmit Data Out
	I/O	Port E1 or SCI Receive Data In
		Not Connected
		Not Connected

Table 2. ST72T331Jx Pin Description

	Pin n°	Pin n°	Pin Name	Type	Description	Remarks
	QFP44 SDIP42
	1	38	PE1/RDI	I/O	Port E1 or SCI Receive Data In
	2	39	PB0	I/O	Port B0	External Interrupt: EI2
	3	40	PB1	I/O	Port B1	External Interrupt: EI2
	4	41	PB2	I/O	Port B2	External Interrupt: EI2
	5	42	PB3	I/O	Port B3	External Interrupt: EI2
	6	1	PB4	I/O	Port B4	External Interrupt: EI3
	7	2	PD0/AIN0	I/O	Port D0 or ADC Analog Input 0
	8	3	PD1/AIN1	I/O	Port D1 or ADC Analog Input 1
	9	4	PD2/AIN2	I/O	Port D2 or ADC Analog Input 2
	10	5	PD3/AIN3	I/O	Port D3 or ADC Analog Input 3
	11	6	PD4/AIN4	I/O	Port D4 or ADC Analog Input 4
	12	7	PD5/AIN5	I/O	Port D5 or ADC Analog Input 5
	13	8	VDDA	S	Power Supply for analog peripheral (ADC)
	14	9	VSSA	S	Ground for analog peripheral (ADC)
	15	10	PF0/CLKOUT	I/O	Port F0 or CPU Clock Output	External Interrupt: EI1
	16	11	PF1	I/O	Port F1	External Interrupt: EI1
	17	12	PF2	I/O	Port F2	External Interrupt: EI1

8/106

ST72E331 ST72T331

	Pin n°	Pin n°	Pin Name	Type	Description	Remarks
	QFP44 SDIP42
	18	13	PF4/OCMP1_A	I/O	Port F4 or Timer A Output Compare 1
	19	14	PF6/ICAP1_A	I/O	Port F6 or Timer A Input Capture 1
	20	15	PF7/EXTCLK_A	I/O	Port F7 or External Clock on Timer A
	21		VDD_0	S	Main power supply
	22		VSS_0	S	Ground
	23	16	PC0/OCMP2_B	I/O	Port C0 or Timer B Output Compare 2
	24	17	PC1/OCMP1_B	I/O	Port C1 or Timer B Output Compare 1
	25	18	PC2/ICAP2_B	I/O	Port C2 or Timer B Input Capture 2
	26	19	PC3/ICAP1_B	I/O	Port C3 or Timer B Input Capture 1
	27	20	PC4/MISO	I/O	Port C4 or SPI Master In / Slave Out Data
	28	21	PC5/MOSI	I/O	Port C5 or SPI Master Out / Slave In Data
	29	22	PC6/SCK	I/O	Port C6 or SPI Serial Clock
	30	23	PC7/SS	I/O	Port C7 or SPI Slave Select
	31	24	PA3	I/O	Port A3	External Interrupt: EI0
	32	25	VDD_1	S	Main power supply
	33	26	VSS_1	S	Ground
	34	27	PA4	I/O	Port A4	High Sink
	35	28	PA5	I/O	Port A5	High Sink
	36	29	PA6	I/O	Port A6	High Sink
	37	30	PA7	I/O	Port A7	High Sink
			1)		Test mode pin. In the EPROM programming	This pin must be tied
				S	mode, this pin acts as the programming
	38	31	TEST/VPP			low in user mode
					voltage input VPP.
	39	32	RESET	I/O	Bidirectional. Active low. Top priority non maskable interrupt.
	40	33	VSS_2	S	Ground
	41	34	OSCOUT	O	Input/Output Oscillator pin. These pins connect a parallel-resonant
	42	35	OSCIN	I	crystal, or an external source to the on-chip oscillator.
	43	36	VDD_2	S	Main power supply
	44	37	PE0/TDO	I/O	Port E0 or SCI Transmit Data Out

Note 1: VPP on EPROM/OTP only.

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ST72E331 ST72T331

1.3 EXTERNAL CONNECTIONS

The following figure shows the recommended external connections for the device.

The VPP pin is only used for programming OTP and EPROM devices and must be tied to ground in user mode.

The 10 nF and 0.1 μF decoupling capacitors on the power supply lines are a suggested EMC performance/cost tradeoff.

Figure 6. Recommended External Connections

The external reset network is intended to protect the device against parasitic resets, especially in noisy environments.

Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up.

VPP

	VDD	+	0.1μF
	10nF
			See
			A/D Converter
			Section
	Optional if Low Voltage
	Detector (LVD) is used		VDD
			4.7K
			0.1μF
	EXTERNAL RESET CIRCUIT
			0.1μF
			See
			Clocks
			Section

Or configure unused I/O ports by software as input with pull-up

10K

VDD

VDD

VSS

VDDA

VSSA

RESET

OSCIN

OSCOUT

Unused I/O

10/106

1.4 MEMORY MAP

Figure 7. Program Memory Map

0000h

HW Registers

(see Table 4)

007Fh

0080h

384 Bytes RAM

01FFh

512 Bytes RAM

	027Fh
	0200h / 0280h	Reserved
	0BFFh
	0C00h	256 Bytes EEPROM
	0CFFh
	0D00h	Reserved
	BFFFh
	C000h
			16K Bytes
			Program
	E000h	8K Bytes	Memory
		Program
	FFDFh	Memory
	FFE0h	Interrupt & Reset Vectors
	FFFF h	(see Table 3)

Table 3. Interrupt Vector Map

Vector Address	Description
FFE0-FFE1h	Not Used
FFE2-FFE3h	Not Used
FFE4-FFE5h	EEPROM Interrupt Vector
FFE6-FFE7h	SCI Interrupt Vector
FFE8-FFE9h	TIMER B Interrupt Vector
FFEA-FFEBh	TIMER A Interrupt Vector
FFEC-FFEDh	SPI interrupt vector
FFEE-FFEFh	Not Used
FFF0-FFF1h	External Interrupt Vector EI3
FFF2-FFF3h	External Interrupt Vector EI2
FFF4-FFF5h	External Interrupt Vector EI1
FFF6-FFF7h	External Interrupt Vector EI0
FFF8-FFF9h	Not Used
FFFA-FF FBh	Not Used
FFFC-FFFDh	TRAP (software) Interrupt Vector
FFFE-FFFFh	RESET Vector

ST72E331 ST72T331

0080h

Short Addressing

RAM (zero page)

00FFh

0100h 256 Bytes Stack/ 01FFh 16-bit Addressing RAM

0080h	Short Addressing
00FFh	RAM (zero page)
0100h
	256 Bytes Stack/
	16-bit Addressing RAM
01FFh
0200h	16-bit Addressing
027Fh	RAM

Remarks

Internal Interrupt

Internal Interrupt

Internal Interrupt

Internal Interrupt

Internal Interrupt

External Interrupt

External Interrupt

External Interrupt

External Interrupt

CPU Interrupt

11/106

ST72E331 ST72T331

Table 4. Hardware Register Memory Map

	Address	Block	Register	Register Name	Reset	Remarks
			Label		Status
	0000h		PADR	Data Register	00h	R/W
	0001h	Port A	PADDR	Data Direction Register	00h	R/W
	0002h		PAOR	Option Register	00h	R/W 1)
	0003h			Reserved Area (1 byte)
	0004h		PCDR	Data Register	00h	R/W
	0005h	Port C	PCDDR	Data Direction Register	00h	R/W
	0006h		PCOR	Option Register	00h	R/W
	0007h			Reserved Area (1 byte)
	0008h		PBDR	Data Register	00h	R/W
	0009h	Port B	PBDDR	Data Direction Register	00h	R/W
	000Ah		PBOR	Option Register	00h	R/W 1)
	000Bh			Reserved Area (1 byte)
	000Ch		PEDR	Data Register	00h	R/W
	000Dh	Port E	PEDDR	Data Direction Register	00h	R/W
	000Eh		PEOR	Option Register	0Ch	R/W 1)
	000Fh			Reserved Area (1 byte)
	0010h		PDDR	Data Register	00h	R/W
	0011h	Port D	PDDDR	Data Direction Register	00h	R/W
	0012h		PDOR	Option Register	00h	R/W 1)
	0013h			Reserved Area (1 byte)
	0014h		PFDR	Data Register	00h	R/W
	0015h	Port F	PFDDR	Data Direction Register	00h	R/W
	0016h		PFOR	Option Register	28h	R/W 1)
	0017h to			Reserved Area (9 bytes)
	001Fh
	0020h		MISCR	Miscellaneous Register	00h
	0021h		SPIDR	SPI Data I/O Register	xxh	R/W
	0022h	SPI	SPICR	SPI Control Register	xxh	R/W
	0023h		SPISR	SPI Status Register	00h	Read Only
	0024h to			Reserved Area (6 bytes)
	0029h
	002Ah	WDG	WDGCR	Watchdog Control Register	7Fh	R/W
	002Bh		WDGSR	Watchdog Status Register	00h	R/W3)
	002Ch	EEPROM	EEPCR	EEPROM Control Register	00h	R/W Register
	002Dh to

0030h

Reserved Area (4 bytes)

12/106

	Address	Block	Register	Register Name	Reset	Remarks
			Label		Status
	0031h		TACR2	Control Register2	00h	R/W
	0032h		TACR1	Control Register1	00h	R/W
	0033h		TASR	Status Register	xxh	Read Only
	0034h-0035h		TAIC1HR	Input Capture1 High Register	xxh	Read Only
			TAIC1LR	Input Capture1 Low Register	xxh	Read Only
	0036h-0037h		TAOC1HR	Output Compare1 High Register	80h	R/W
			TAOC1LR	Output Compare1 Low Register	00h	R/W
	0038h-0039h	Timer A	TACHR	Counter High Register	FFh	Read Only
			TACLR	Counter Low Register	FCh	Read Only
	003Ah-003Bh		TAACHR	Alternate Counter High Register	FFh	Read Only
			TAACLR	Alternate Counter Low Register	FCh	Read Only
	003Ch-003Dh		TAIC2HR	Input Capture2 High Register	xxh	Read Only2)
			TAIC2LR	Input Capture2 Low Register	xxh	Read Only2)
	003Eh-003Fh		TAOC2HR	Output Compare2 High Register	80h	R/W2)
			TAOC2LR	Output Compare2 Low Register	00h	R/W2)
	0040h			Reserved Area (1 byte)
	0041h		TBCR2	Control Register2	00h	R/W
	0042h		TBCR1	Control Register1	00h	R/W
	0043h		TBSR	Status Register	xxh	Read Only
	0044h-0045h		TBIC1HR	Input Capture1 High Register	xxh	Read Only
			TBIC1LR	Input Capture1 Low Register	xxh	Read Only
	0046h-0047h		TBOC1HR	Output Compare1 High Register	80h	R/W
			TBOC1LR	Output Compare1 Low Register	00h	R/W
	0048h-0049h	Timer B	TBCHR	Counter High Register	FFh	Read Only
			TBCLR	Counter Low Register	FCh	Read Only
	004Ah-004Bh		TBACHR	Alternate Counter High Register	FFh	Read Only
			TBACLR	Alternate Counter Low Register	FCh	Read Only
	004Ch-004Dh		TBIC2HR	Input Capture2 High Register	xxh	Read Only
			TBIC2LR	Input Capture2 Low Register	xxh	Read Only
	004Eh-004Fh		TBOC2HR	Output Compare2 High Register	80h	R/W
			TBOC2LR	Output Compare2 Low Register	00h	R/W
	0050h		SCISR	SCI Status Register	C0h	Read Only
	0051h		SCIDR	SCI Data Register	xxh	R/W
	0052h		SCIBRR	SCI Baud Rate Register	00x----xb	R/W
	0053h	SCI	SCICR1	SCI Control Register 1	xxh	R/W
	0054h		SCICR2	SCI Control Register 2	00h	R/W
	0055h		SCIERPR	SCI Extended Receive Prescaler Register	00h	R/W
	0056h			Reserved	---	Reserved
	0057h		SCIETPR	SCI Extended Transmit Prescaler Register	00h	R/W
	0058h to			Reserved Area (24 bytes)
	006Fh
	0070h	ADC	ADCDR	ADC Data Register	00h	Read Only
	0071h		ADCCSR	ADC Control/Status Register	00h	R/W
	0072h to				ST72E331 ST72T331

Reserved Area (14 bytes)

007Fh

Notes:

1.The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.

2.External pin not available.

3.Not used in versions without Low Voltage Detector Reset.

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ST72E331 ST72T331

1.5 OPTION BYTE

The user has the option to select software watchdog or hardware watchdog (see description in the Watchdog chapter). When programming EPROM or OTP devices, this option is selected in a menu by the user of the EPROM programmer before burning the EPROM/OTP. The Option Byte is located in a non-user map. No address has to be specified. The Option Byte is at FFh after UV erasure and must be properly programmed to set desired options.

OPTBYTE

7				0
-	-	-	- b3 b2	- WDG

Bit 7:4 = Not used

Bit 3 = Reserved, must be cleared.

Bit 2 = Reserved, must be set on ST72T331N devices and must be cleared on ST72T331J devices.

Bit 1 = Not used

Bit 0 = WDG Watchdog disable

0:The Watchdog is enabled after reset (Hardware Watchdog).

1:The Watchdog is not enabled after reset (Software Watchdog).

14/106

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

2.2 MAIN FEATURES

■63 basic instructions

■Fast 8-bit by 8-bit multiply

■17 main addressing modes (with indirect addressing mode)

■Two 8-bit index registers

■16-bit stack pointer

■8 MHz CPU internal frequency

■Low power modes

■Maskable hardware interrupts

■Non-maskable software interrupt

2.3 CPU REGISTERS

The 6 CPU registers shown in Figure 8 are not present in the memory mapping and are accessed by specific instructions.

Figure 8. CPU Registers

			7							0
			RESET VALUE = XXh
			7							0
			RESET VALUE = XXh
			7							0
			RESET VALUE = XXh
15	PCH	8	7			PCL				0
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
			7							0
			1	1	1	H	I	N	Z	C
	RESET VALUE = 1			1	1	X	1	X	X	X
15		8	7							0

RESET VALUE = STACK HIGHER ADDRESS

ST72E331 ST72T331

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

ACCUMULATOR

XINDEX REGISTER

YINDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

15/106

ST72E331 ST72T331

CENTRAL PROCESSING UNIT (Cont'd)

CONDITION CODE REGISTER (CC)

Read/Write

Reset Value: 111x1xxx

7							0
1	1	1	H	I	N	Z	C

The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.

0:No half carry has occurred.

1:A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 3 = I Interrupt mask.

This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.

0:Interrupts are enabled.

1:Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware when you en-

ter it and reset by the IRET instruction at the end of the interrupt routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.

0:The result of the last operation is positive or null.

1:The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0:The result of the last operation is different from zero.

1:The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0:No overflow or underflow has occurred.

1:An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the ªbit test and branchº, shift and rotate instructions.

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ST72E331 ST72T331

CENTRAL PROCESSING UNIT (Cont'd)

Stack Pointer (SP)

Read/Write

Reset Value: 01FFh

15							8
0	0	0	0	0	0	0	1
7							0
SP7	SP6	SP5	SP4	SP3	SP2	SP1	SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9).

Since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

Figure 9. Stack Manipulation Example

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 9.

±When an interrupt is received, the SP is decremented and the context is pushed on the stack.

±On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

CALL	Interrupt	PUSH Y	POP Y	IRET	RET
Subroutine	Event				or RSP
@ 0100h

			SP
		SP	Y	SP
		CC	CC	CC
		A	A	A
		X	X	X
	SP	PCH	PCH	PCH	SP
		PCL	PCL	PCL
	PCH	PCH	PCH	PCH	PCH
	@ 01FFh PCL	PCL	PCL	PCL	SP
					PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

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ST72E331 ST72T331

3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES

3.1 CLOCK SYSTEM

3.1.1 General Description

Figure 10. External Clock Source Connections

The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (fOSC). The

external Oscillator clock is first divided by 2, and an additional division factor of 2, 4, 8, or 16 can be applied, in Slow Mode, to reduce the frequency of the fCPU; this clock signal is also routed to the onchip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%.

The internal oscillator is designed to operate with an AT-cut parallel resonant quartz crystal resonator in the frequency range specified for fosc. The circuit shown in Figure 11 is recommended when using a crystal, and Table 5 lists the recommended capacitance and feedback resistance values. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time.

Use of an external CMOS oscillator is recommended when crystals outside the specified frequency ranges are to be used.

3.1.2 External Clock

An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 10.

Table 5 Recommended Values for 16 MHz Crystal Resonator (C0 < 7pF)

RSMAX	40 Ω	60 Ω	150 Ω
COSCIN	56pF	47pF	22pF
COSCOUT	56pF	47pF	22pF

RSMAX: Parasitic series resistance of the quartz crystal (upper limit).

C0: Parasitic shunt capacitance of the quartz crystal (upper limit 7pF).

COSCOUT, COSCIN: Maximum total capacitance on pins OSCIN and OSCOUT (the value includes the

external capacitance tied to the pin plus the parasitic capacitance of the board and of the device).

OSCIN OSCOUT

NC

EXTERNAL

CLOCK

Figure 11. Crystal/Ceramic Resonator

OSCIN OSCOUT

COSCIN

COSCOUT

Figure 12. Clock Prescaler Block Diagram

%2 % 2, 4, 8, 16

		fCPU
	OSCIN OSCOUT	to CPU and
		Peripherals

COSCIN	C
	OSCOUT

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ST72E331 ST72T331

3.2 RESET

3.2.1 Introduction

There are four sources of Reset:

±RESET pin (external source)

±Power-On Reset (Internal source)

±WATCHDOG (Internal Source)

±Low Voltage Detection Reset (internal source)

The Reset Service Routine vector is located at address FFFEh-FFFFh.

3.2.2 External Reset

The RESET pin is both an input and an open-drain output with integrated pull-up resistor. When one of the internal Reset sources is active, the Reset

pin is driven low for a duration of tRESET to reset the whole application.

3.2.3 Reset Operation

The duration of the Reset state is a minimum of 4096 internal CPU Clock cycles. During the Reset state, all I/Os take their reset value.

A Reset signal originating from an external source must have a duration of at least tPULSE in order to

Figure 13. Reset Block Diagram

be recognised. This detection is asynchronous and therefore the MCU can enter Reset state even in Halt mode.

At the end of the Reset cycle, the MCU may be held in the Reset state by an External Reset signal. The RESET pin may thus be used to ensure VDD has risen to a point where the MCU can operate correctly before the user program is run. Following a Reset event, or after exiting Halt mode, a 4096 CPU Clock cycle delay period is initiated in order to allow the oscillator to stabilise and to ensure that recovery has taken place from the Reset state.

In the high state, the RESET pin is connected internally to a pull-up resistor (RON). This resistor can be pulled low by external circuitry to reset the device.

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to use the external connections shown in Figure 6.

OSCILLATOR

SIGNAL

TO ST7

RESET

RESET

VDD

RON

INTERNAL

RESET

COUNTER

POWER-ON RESET

WATCHDOG RESET

LOW VOLTAGE DETECTOR RESET

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ST72E331 ST72T331

RESET (Cont'd)

3.2.4 Low Voltage Detector Reset

The on-chip Low Voltage Detector (LVD) generates a static reset when the supply voltage is below a reference value. The LVD functions both during power-on as well as when the power supply drops (brown-out). The reference value for a voltage drop is lower than the reference value for pow- er-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when VDD is below:

VLVDUP when VDD is rising VLVDDOWN when VDD is falling

Provided the minimun VDD value (guaranteed for

the oscillator frequency) is above VLVDDOWN , the MCU can only be in two modes:

-under full software control or

-in static safe reset

In this condition, secure operation is always ensured for the application without the need for external reset hardware.

cases, it is recommended to use devices without the LVD Reset option and to rely on the watchdog function to detect application runaway conditions.

Figure 14. Low Voltage Detector Reset Function

LOW VOLTAGE

VDD

DETECTOR RESET

RESET

FROM

WATCHDOG

RESET

Figure 15. Low Voltage Detector Reset Signal

VLVDUP

VLVDDOWN

VDD

RESET

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

In noisy environments, the power supply may drop for short periods and cause the Low Voltage Detector to generate a Reset too frequently. In such

Note: See electrical characteristics for values of

VLVDUP and VLVDDOWN

Figure 16. Temporization timing diagram after an internal Reset

VLVDUP

VDD

Temporization (4096 CPU clock cycles)

Addresses	$FFFE

20/106

3.3 INTERRUPTS

The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 17.

The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).

When an interrupt has to be serviced:

±Normal processing is suspended at the end of the current instruction execution.

±The PC, X, A and CC registers are saved onto the stack.

±The I bit of the CC register is set to prevent additional interrupts.

±The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses).

The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume.

Priority management

By default, a servicing interrupt can not be interrupted because the I bit is set by hardware entering in interrupt routine.

In the case several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table).

Non Maskable Software Interrupts

This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 17.

Interrupts and Low power mode

All interrupts allow the processor to leave the Wait low power mode. Only external and specific mentioned interrupts allow the processor to leave the

ST72E331 ST72T331

Halt low power mode (refer to the ªExit from HALTª column in the Interrupt Mapping Table).

External Interrupts

External interrupt vectors can be loaded in the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode.

The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available).

External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.

If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed before entering the edge/ level detection block.

Warning: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the EI source. In case of an ANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of rising-edge sensitivity.

Peripheral Interrupts

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:

±The I bit of the CC register is cleared.

±The corresponding enable bit is set in the control register.

If any of these two conditions is false, the interrupt is latched and thus remains pending.

Clearing an interrupt request is done by:

±writing ª0º to the corresponding bit in the status register or

±an access to the status register while the flag is set followed by a read or write of an associated register.

Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.

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ST72E331 ST72T331

INTERRUPTS (Cont'd)

Figure 17. Interrupt Processing Flowchart

FROM RESET

N
BIT I SET
Y	N
	BIT I SET
FETCH NEXT INSTR UCTION	Y

N

IRET

STACK PC, X, A, CC Y SET I BIT

LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

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ST72E331 ST72T331

Table 6. Interrupt Mapping

	Source		Register		Exit
		Description		Flag	from
	Block		Label
					HALT
	RESET	Reset	N/A	N/A	yes
	TRAP	Software	N/A	N/A	no
		NOT USED
		NOT USED
	EI0	Ext. Interrupt (Ports PA0:PA3)	N/A	N/A
	EI1	Ext. Interrupt (Ports PF0:PF2)	N/A	N/A	yes
	EI2	Ext. Interrupt (Ports PB0:PB3)	N/A	N/A
	EI3	Ext. Interrupt (Ports PB4:PB7)	N/A	N/A
		NOT USED
	SPI	Transfer Complete	SPISR	SPIF
		Mode Fault		MODF
		Input Capture 1		ICF1_A
		Output Compare 1		OCF1_A
	TIMER A	Input Capture 2	TASR	ICF2_A
		Output Compare 2		OCF2_A
		Timer Overflow		TOF_A
		Input Capture 1		ICF1_B
		Output Compare 1		OCF1_B	no
	TIMER B	Input Capture 2	TBSR	ICF2_B
		Output Compare 2		OCF2_B
		Timer Overflow		TOF_B
		Transmit Buffer Empty		TDRE
		Transmit Complete		TC
	SCI	Receive Buffer Full	SCISR	RDRF
		Idle Line Detect		IDLE
		Overrun		OR
	EEPROM	EEPROM End of Programming	EEPCR	E2ITE
		NOT USED
		NOT USED

Vector

Address

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

FFF8h-FFF9h

FFF6h-FFF7h

FFF4h-FFF5h

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

FFE2h-FFE3h

FFE0h-FFE1h

Priority

Order

Highest

Priority

Lowest

Priority

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ST72E331 ST72T331

3.4 POWER SAVING MODES

3.4.1 Introduction

There are three Power Saving modes. Slow Mode is selected by setting the relevant bits in the Miscellaneous register. Wait and Halt modes may be entered using the WFI and HALT instructions.

3.4.2 Slow Mode

In Slow mode, the oscillator frequency can be divided by a value defined in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow mode is used to reduce power consumption, and enables the user to adapt clock frequency to available supply voltage.

3.4.3 Wait Mode

Wait mode places the MCU in a low power consumption mode by stopping the CPU. All peripherals remain active. During Wait mode, the I bit (CC Register) is cleared, so as to enable all interrupts. All other registers and memory remain unchanged. The MCU will remain in Wait mode until an Interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the Interrupt or Reset Service Routine.

The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up.

Refer to Figure 18 below.

Figure 18. WAIT Flow Chart

WFI INSTRUCTION

OSCILLATOR	ON
PERIPH. CLOCK	ON
CPU CLOCK	OFF
I-BIT	CLEARED

N

RESET

N

	INTERRUPT	Y
	Y	OSCILLATOR	ON
		PERIPH. CLOCK	ON
		CPU CLOCK	ON
		I-BIT	SET
		4096 CPU CLOCK
		CYCLES DELAY
		OSCILLATOR	ON
		PERIPH. CLOCK	ON
		CPU CLOCK	ON
		I-BIT	SET

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.

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POWER SAVING MODES (Cont'd)

3.4.4 Halt Mode

The Halt mode is the MCU lowest power consumption mode. The Halt mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. The Halt mode cannot be used when the watchdog is enabled, if the HALT instruction is executed while the watchdog system is enabled, a watchdog reset is generated thus resetting the entire MCU.

When entering Halt mode, the I bit in the CC Register is cleared so as to enable External Interrupts. If an interrupt occurs, the CPU becomes active.

The MCU can exit the Halt mode upon reception of an interrupt or a reset. Refer to the Interrupt Mapping Table. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles.

After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up.

ST72E331 ST72T331

Figure 19. HALT Flow Chart

		HALT INSTRUCTION
WATCHDOG	Y	WDG
RESET		ENABLED?
		N
	OSCILLATOR		OFF
	PERIPH. CLOCK		OFF
	CPU CLOCK		OFF
	I-BIT		CLEARED
	N
		RESET
N
EXTERNAL		Y
INTERRUPT1)
Y		OSCILLATOR	ON
		PERIPH. CLOCK2) OFF
		CPU CLOCK	ON
		I-BIT	SET
		4096 CPU CLOCK
		CYCLES DELAY
		OSCILLATOR	ON
		PERIPH. CLOCK	ON
		CPU CLOCK	ON
		I-BIT	SET

FETCH RESET VECTOR

OR SERVICE INTERRUPT

1)or some specific interrupts

2)if reset PERIPH. CLOCK = ON ; if interrupt PERIPH. CLOCK = OFF

Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.

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ST72E331 ST72T331

3.5 MISCELLANEOUS REGISTER

The Miscellaneous register allows to select the SLOW operating mode, the polarity of external interrupt requests and to output the internal clock.

Register Address: 0020h Ð Read/ Write

Reset Value: 0000 0000 (00h)

7

0

PEI3 PEI2 MCO PEI1 PEI0 PSM1 PSM0 SMS

Bit 7:6 = PEI[3:2] External Interrupt EI3 and EI2 Polarity Options.

These bits are set and cleared by software. They determine which event on EI2 and EI3 causes the external interrupt according to Table 7.

Table 7. EI2 and EI3 External Interrupt Polarity

Options

	MODE	PEI3	PEI2
	Falling edge and low level	0	0
	(Reset state)
	Falling edge only	1	0
	Rising edge only	0	1
	Rising and falling edge	1	1

Note: Any modification of one of these two bits resets the interrupt request related to this interrupt vector.

Bit 5 = MCO Main Clock Out

This bit is set and cleared by software. When set, it enables the output of the Internal Clock on the PPF0 I/O port.

0 - PF0 is a general purpose I/O port.

1 - MCO alternate function (fCPU is output on PF0 pin).

Bit 4:3 = PEI[1:0] External Interrupt EI1 and EI0 Polarity Options.

These bits are set and cleared by software. They determine which event on EI0 and EI1 causes the external interrupt according to Table 8.

Table 8. EI0 and EI1 External Interrupt Polarity

Options

	MODE	PEI1	PEI0
	Falling edge and low level	0	0
	(Reset state)
	Falling edge only	1	0
	Rising edge only	0	1
	Rising and falling edge	1	1

Note: Any modification of one of these two bits resets the interrupt request related to this interrupt vector.

Bit 2:1 = PSM[1:0] Prescaler for Slow Mode

These bits are set and cleared by software. They determine the CPU clock when the SMS bit is set according to the following table.

Table 9. fCPU Value in Slow Mode

fCPU Value	PSM1	PSM0
fOSC / 4	0	0
fOSC / 16	0	1
fOSC / 8	1	0
fOSC / 32	1	1

Bit 0 = SMS Slow Mode Select

This bit is set and cleared by software.

0:Normal Mode - fCPU = fOSC/ 2 (Reset state)

1:Slow Mode - the fCPU value is determined by the PSM[1:0] bits.

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4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

4.1.1 Introduction

The I/O ports offer different functional modes:

±transfer of data through digital inputs and outputs and for specific pins:

±analog signal input (ADC)

±alternate signal input/output for the on-chip peripherals.

±external interrupt generation

An I/O port is composed of up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

4.1.2 Functional Description

Each port is associated to 2 main registers:

±Data Register (DR)

±Data Direction Register (DDR)

and some of them to an optional register:

± Option Register (OR)

Each I/O pin may be programmed using the corresponding register bits in DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.

The following description takes into account the OR register, for specific ports which do not provide this register refer to the I/O Port Implementation Section 4.1.3. The generic I/O block diagram is shown on Figure 21.

4.1.2.1 Input Modes

The input configuration is selected by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Notes:

1.All the inputs are triggered by a Schmitt trigger.

2.When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is con-

figured as an output.

ST72E331 ST72T331

Interrupt function

When an I/O is configured in Input with Interrupt, an event on this I/O can generate an external Interrupt request to the CPU. The interrupt polarity is given independently according to the description mentioned in the Miscellaneous register or in the interrupt register (where available).

Each pin can independently generate an Interrupt request.

Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If several input pins are configured as inputs to the same interrupt vector, their signals are logically ANDed before entering the edge/level detection block. For this reason if one of the interrupt pins is tied low, it masks the other ones.

4.1.2.2 Output Mode

The pin is configured in output mode by setting the corresponding DDR register bit.

In this mode, writing ª0º or ª1º to the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value.

Note: In this mode, the interrupt function is disabled.

4.1.2.3 Digital Alternate Function

When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).

When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin's state is also digitally readable by addressing the DR register.

Notes:

1.Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input.

2.When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0).

Warning: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

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ST72E331 ST72T331

I/O PORTS (Cont'd)

4.1.2.4 Analog Alternate Function

When the pin is used as an ADC input the I/O must be configured as input, floating. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin.

Warning: The analog input voltage level must be within the limits stated in the Absolute Maximum Ratings.

4.1.3 I/O Port Implementation

The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input (see Figure 21) or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 20. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.

Figure 20. Recommended I/O State Transition Diagram
INPUT	INPUT	OUTPUT	OUTPUT
with interrupt	no interrupt	open-drain	push-pull

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ST72E331 ST72T331

I/O PORTS (Cont'd)

Figure 21. I/O Block Diagram

ALTERNATE ENABLE

ANALOG RAIL	DATA BUS
COMMON

ALTERNATE 1	M		VDD
OUTPUT
	U
0	X		P-BUFFER
			(SEE TABLE BELOW)
DR		ALTERNATE	PULL-UP
LATCH		ENABLE

		PULL-UP	VDD
	DDR		DIODE
		CONDITION
			(SEE TABLE BELOW)
	LATCH
	OR		PAD
		ANALOG ENABLE
	LATCH
	(SEE TABLE BELOW)	(ADC)
		ANALOG	GND
	OR SEL
		SWITCH
		(SEE NOTE BELOW)
	DDR SEL
			N-BUFFER
		ALTERNATE

		DR SEL	1	ENABLE
			M
			U
			X		GND
			0
	ALTERNATE INPUT
				CMOS
		POLARITY	FROM	SCHMITT TRIGGER
EXTERNAL		SEL
			OTHER
INTERRUPT			BITS
SOURCE (EIx)
Table 10. Port Mode Configuration
		Configuratio n Mode		Pull-up	P-buffer	VDD Diode
Floating				0	0	1
Pull-up				1	0	1
Push-pull				0	1	1
True Open Drain				not present	not present	not present
Open Drain (logic level)				0	0	1
Legend:				Notes:
0 -	present, not activated			± No OR Register on some ports (see register map).
1 -	present and activated			± ADC Switch on ports with analog alternate functions.

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ST72E331 ST72T331

I/O PORTS (Cont'd)

Table 11. Port Configuration

	Port	Pin name	Input (DDR = 0)		Output (DDR = 1)
			OR = 0	OR = 1	OR = 0	OR =1
		PA0:PA2 1)	floating*	pull-up with interrupt	open-drain	push-pull
	Port A	PA3	floating*	pull-up with interrupt	open-drain	push-pull
		PA4:PA7		floating*	open drain, high sink capability
	Port B	PB0:PB4	floating*	pull-up with interrupt	open-drain	push-pull
		PB5:PB7 1)	floating*	pull-up with interrupt	open-drain	push-pull
	Port C	PC0:PC7	floating*	pull-up	open-drain	push-pull
	Port D	PD0:PD5	floating*	pull-up	open-drain	push-pull
		PD6:PD7 1)	floating*	pull-up	open-drain	push-pull
	Port E	PE0:PE1	floating*	pull-up	open-drain	push-pull
		PE4:PE7 1)		floating*2)	open drain, high sink capability3)
	Port F	PF0:PF2	floating*	pull-up with interrupt	open-drain	push-pull
		PF4, PF6, PF7	floating*	pull-up	open-drain	push-pull

Notes:

1.ST72T331N only

2.For OTP/EPROM version, when OR=0: floating & when OR=1: reserved

3.For OTP/EPROM version, when OR=0: open-drain, high sink capability & when OR=1: reserved

* Reset state (The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value).

Warning: All bits of the DDR register which correspond to unconnected I/Os must be left at their reset value. They must not be modified by the user otherwise a spurious interrupt may be generated.

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