SGS Thomson Microelectronics ST72F521R9, ST72F521R7, ST72F521R6, ST72F521M9, ST72F521M7 Datasheet

ST72521

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

■Memories

–32K to 60K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and In-Circuit Programming for HDFlash devices

–1K to 2K RAM

–HDFlash endurance: 100 cycles, data retention: 20 years at 55°C

■Clock, Reset And Supply Management

–Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector (AVD) with interrupt capability

–Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock

–PLL for 2x frequency multiplication

–Four power saving modes: Halt, Active-Halt, Wait and Slow

■Interrupt Management

–Nested interrupt controller

–14 interrupt vectors plus TRAP and RESET

–Top Level Interrupt (TLI) pin

–15 external interrupt lines (on 4 vectors)

■Up to 64 I/O Ports

–48 multifunctional bidirectional I/O lines

–34 alternate function lines

–16 high sink outputs

■5 Timers

–Main Clock Controller with: Real time base, Beep and Clock-out capabilities

–Configurable watchdog timer

–Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes

–8-bit PWM Auto-Reload timer with: 2 input captures, 4 PWM outputs, output compare

Device Summary

	TQFP64
	14 x 14
TQFP80	TQFP64
	10 x 10
14 x 14

and time base interrupt, external clock with event detector

■4 Communications Interfaces

–SPI synchronous serial interface

–SCI asynchronous serial interface (LIN compatible)

–I2C multimaster interface

–CAN interface (2.0B Passive)

■Analog peripheral

–10-bit ADC with 16 input pins

■Instruction Set

–8-bit Data Manipulation

–63 Basic Instructions

–17 main Addressing Modes

–8 x 8 Unsigned Multiply Instruction

■Development Tools

–Full hardware/software development package

–In-Circuit Testing capability

Features	ST72521(M/R/AR)9		ST72521(R/AR)6
Program memory - bytes	60K		32K
RAM (stack) - bytes	2048 (256)		1024 (256)
Operating Voltage		3.8V to 5.5V
Temp. Range		up to -40°C to +125 °C
Package	TQFP80 14x14 (M), TQFP64 14x14 (R), TQFP64		TQFP64 14x14 (R), TQFP64 10x10 (AR)
	10x10 (AR)

Rev. 1.9

August 2003

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1

				Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . . 7
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . . 8
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . 1 4
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . 18
4.1		INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 18
4.2		MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 18
4.3		STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 18
		4.3.1	Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 18
4.4		ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 19
4.5		ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 20
4.6		IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 20
4.7		RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 20
		4.7.1	Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 20
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . 21
5.1		INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 21
5.2		MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 21
5.3		CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 21
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . 24
6.1		PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 24
6.2		MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 25
6.3		RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 26
		6.3.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 26
		6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 26
		6.3.3	External Power-On RESET . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 27
		6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 27
		6.3.5	Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 27
6.4		SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 28
		6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 28
		6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 29
		6.4.3 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 31
		6.4.4	Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 31
		6.4.5	Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 32
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . 33
7.1		INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 33
7.2		MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 33
7.3		INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 35
7.4		CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 35
7.5		INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 36
7.6		EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 38
		7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 38
7.7		EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . .			. . . . . . . . . . . . . . . . . . . . 40
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . 42
8.1		INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 42
8.2		SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 42
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Table of Contents

8.3	WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
8.4	ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		44
	8.4.1	ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
	8.4.2	HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
9 I/O PORTS .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
9.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		47
9.2	FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		47
	9.2.1	Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
	9.2.2	Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
	9.2.3	Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
9.3	I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		50
9.4	LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		50
9.5	INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		50
	9.5.1	I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			53

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 56 10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 58

10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	59
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	59
10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	59
10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.5.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 10.5.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.5.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.5.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.5.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	100
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	100
10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	100
10.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	102
10.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	107
10.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	107
10.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	108
10.7 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	114

10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

10.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

10.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

10.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

10.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

10.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

10.8 CONTROLLER AREA NETWORK (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

10.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	127
10.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	128
10.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	128
10.8.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	134
10.8.5 List of CAN Cell Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	144
10.9 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	152

10.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

10.9.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

10.9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

10.9.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

10.9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

10.9.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	156
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	156

11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

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12.1	PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	162
	12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	162
	12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	162
	12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	162
	12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	162
	12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	162
12.2	ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	163
	12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	163
	12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	163
	12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	164
12.3	OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	164
	12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	164
	12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . .	165
	12.3.3 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . .	166
	12.3.4 External Voltage Detector (EVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . .	166
12.4	SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	167
	12.4.1 RUN and SLOW Modes (Flash devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	167
	12.4.2 WAIT and SLOW WAIT Modes (Flash devices) . . . . . . . . . . . . . . . . . . . . . . . . . .	168
	12.4.3 RUN and SLOW Modes (ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	169
	12.4.4 WAIT and SLOW WAIT Modes (ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . .	169
	12.4.5 HALT and ACTIVE-HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	170
	12.4.6 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	170
	12.4.7 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	171
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		172
	12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	172
	12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	172
	12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	173
	12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	175
	12.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	176
	12.5.6 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	176
12.6	MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	177
	12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	177
	12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	177
12.7	EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	178
	12.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	178
	12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	178
	12.7.3 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	179
	12.7.4 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	181
12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		183

12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.10.18-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	187
12.10.216-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	187

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12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 188

12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

12.11.2CAN - Controller Area Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.11.3I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

12.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.12.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	193
12.12.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	193
12.12.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	194
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	195

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

14 ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 199

14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

199

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 201

14.2.1 Version-Specific Sales Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

14.3.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		206
15.1	SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	206
15.2	ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	206
	15.2.1 External RC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	206
	15.2.2 CSS Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	206
	15.2.3 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	206
	15.2.4 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	206
	15.2.5 Internal RC Oscillator with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	206
	15.2.6 Read-out protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	206
	15.2.7 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	206
	15.2.8 I/O behaviour during ICC mode entry sequence . . . . . . . . . . . . . . . . . . . . . . . . .	206
	15.2.9 CAN Cell Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	207
15.3	FLASH REV “S” AND ROM REV “W” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	208
	15.3.1 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	208
	15.3.2 LVD Startup behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	208
	15.3.3 I/O Port D Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	208
15.4	FLASH REV “S” DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	208
	15.4.1 LVD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	208
16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		210

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet.

Please also pay special attention to the Section “IMPORTANT NOTES” on page 206

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1

ST72521

1 INTRODUCTION

The ST72521(A)R and ST72521M devices are members of the ST7 microcontroller family designed for mid-range applications with a CAN bus interface (Controller Area Network).

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with FLASH or ROM program memory.

Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

Figure 1. Device Block Diagram
	8-BIT CORE		PROGRAM
	ALU		MEMORY
			(32K - 60K Bytes)
RESET	CONTROL
VPP
			RAM
TLI
			(1024-2048 Bytes)
VSS
	LVD
VDD
EVD	AVD		WATCHDOG
OSC1
	OSC
OSC2
			I2C
		ADDRESS
	MCC/RTC/BEEP		PA7:0
			(8-bits)
			PORT A
	PORT F	AND	PORT B
PF7:0
(8-bits)	TIMER A	DATA	PB7:0
			PWM ART
			(8-bits)
	BEEP	BUS	PORT C

PORT E

PC7:0

PE7:0

TIMER B

(8-bits)

(8-bits)

CAN

SPI

SCI

PG7:0

PORT D

PORT G1

PD7:0

(8-bits)

(8-bits)

PH7:0

10-BIT ADC

PORT H1

VAREF

(8-bits)

VSSA

1On some devices only, see Device Summary on page 1

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3

ST72521

2 PIN DESCRIPTION

Figure 2. 80-Pin TQFP 14x14 Package Pinout

(HS) PE4 1

(HS) PE5 2

(HS) PE6 3

(HS) PE7 4

PWM3 / PB0 5 PWM2 / PB1 6 PWM1 / PB2 7 PWM0 / PB3 8

PG0 9

PG1 10

PG2 11

PG3 12 ARTCLK / (HS) PB4 13

ARTIC1 / PB5 14

ARTIC2 / PB6 15 PB7 16 AIN0 / PD0 17

AIN1 / PD1 18

AIN2 / PD2 19

AIN3 / PD3 20

CANRX/PE3	CANTX/PE2		RDI/PE1		TDO/PE0		V		OSC1		OSC2		V			PH7			PH6			PH5		PH4			TLI		EVD			RESET
							2						2
							DD							SS
80	79		78		77		76		75		74		73			72			71			70		69			68		67		66

ei2

ei3

																													ei1
21	22		23		24		25		26		27			28			29			30			31		32		33		34			35
			AIN4/PD4																													(HS) PF2
PG6	PG7				AIN5 / PD5		AIN6 / PD6		AIN7 / PD7			AREF			SSA			DD3			SS3		PG4		PG5		MCO /AIN8 / PF0		BEEP / (HS) PF1
											V			V			V				V

/ ICCSEL		(HS) / SCLI			(HS) / SDAI			(HS)			(HS)
V		PA7			PA6			PA5			PA4
PP
65		64			63			62			61

ei0

36		37		38			39			40
		OCMP1 A/AIN10 /PF4
OCMP2 A / AIN9 /PF3				ICAP2 A/ AIN11 /PF5			ICAP1 A / (HS) / PF6			EXTCLK A / (HS) PF7

(HS) eix

60			VSS_1
59			VDD_1
58			PA3 (HS)
57			PA2
56			PA1
55			PA0
54
			PC7 /	SS	/ AIN15
53			PC6 / SCK /ICCCLK
52			PH3
51			PH2
50			PH1
49			PH0
48			PC5 / MOSI / AIN14
			PC4 / MISO / ICCDATA
47
46			PC3 (HS) /ICAP1_B
45			PC2(HS) / ICAP2_B
44			PC1 / OCMP1_B / AIN13
43			PC0 / OCMP2_B /AIN12
42			VSS_0
41			VDD_0

20mA high sink capability associated external interrupt vector

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DD_0

SS_0

ST72521

PIN DESCRIPTION (Cont’d)

Figure 3. 64-Pin TQFP 14x14 and 10x10 Package Pinout

	CANRX/PE3	CANTX/PE2 RDI/PE1 TDO/PE0	V OSC1 OSC2	V	TLI EVD RESET		V (HS)PA7/ SCLI	(HS)PA6/ SDAI (HS)PA5	(HS)PA4
			2	2			ICCSEL/
			DD	SS			PP
(HS) PE4	64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
	1								48
(HS) PE5	2								47
(HS) PE6	3								46
(HS) PE7	4							ei0	45
PWM3 / PB0	5								44
PWM2 / PB1	6	ei2							43
PWM1 / PB2	7								42
PWM0 /PB3	8								41
ARTCLK /(HS) PB4	9								40
ARTIC1 / PB5	10	ei3							39
ARTIC2 / PB6	11								38
PB7	12								37
AIN0 / PD0	13								36
AIN1 / PD1	14								35
AIN2 / PD2	15				ei1				34
AIN3 / PD3	16								33
	17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

VSS_1

VDD_1

PA3 (HS)

PA2

PA1

PA0

PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC5 / MOSI / AIN14

PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12 V

V

AIN4 / PD4

AIN5 / PD5

AIN6 / PD6

AIN7 / PD7

AREF

SSA

DD_3

SS_3

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

OCMP2 A / AIN9 / PF3

OCMP1 A / AIN10 / PF4

ICAP2 A / AIN11 / PF5

ICAP1 A / (HS) PF6

EXTCLK A / (HS) PF7

V

V

V

V

(HS)

20mA high sink capability

eix

associated external interrupt vector

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ST72521

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 162.

Legend / Abbreviations for Table 1:

Type:		I = input, O = output, S = supply
Input level:		A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD
		CT= CMOS 0.3VDD/0.7VDD with input trigger
		TT= TTL 0.8V / 2V with Schmitt trigger
Output level:		HS = 20mA high sink (on N-buffer only)
Port and control configuration:
–	Input:	float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
–	Output:	OD = open drain 2), PP = push-pull

Refer to “I/O PORTS” on page 47 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.

Table 1. Device Pin Description

Pin n°

Level

Port

Main

TQFP80

TQFP64

Type

Input

Output

float

wpu

int

ana

OD

PP

function

Pin Name

Input

Output

(after

Alternate function

reset)

1

1

PE4 (HS)

I/O

CT

HS

X

X

X

X

Port E4

2

2

PE5 (HS)

I/O

CT

HS

X

X

X

X

Port E5

3

3

PE6 (HS)

I/O

CT

HS

X

X

X

X

Port E6

4

4

PE7 (HS)

I/O

CT

HS

X

X

X

X

Port E7

5

5

PB0/PWM3

I/O

CT

X

ei2

X

X

Port B0

PWM Output 3

6

6

PB1/PWM2

I/O

CT

X

ei2

X

X

Port B1

PWM Output 2

7

7

PB2/PWM1

I/O

CT

X

ei2

X

X

Port B2

PWM Output 1

8

8

PB3/PWM0

I/O

CT

X

ei2

X

X

Port B3

PWM Output 0

9

-

PG0

I/O

TT

X

X

X

X

Port G0

10

-

PG1

I/O

TT

X

X

X

X

Port G1

11

-

PG2

I/O

TT

X

X

X

X

Port G2

12

-

PG3

I/O

TT

X

X

X

X

Port G3

13

9

PB4 (HS)/ARTCLK

I/O

CT

HS

X

ei3

X

X

Port B4

PWM-ART External Clock

14

10

PB5/ARTIC1

I/O

CT

X

ei3

X

X

Port B5

PWM-ART Input Capture 1

15

11

PB6/ARTIC2

I/O

CT

X

ei3

X

X

Port B6

PWM-ART Input Capture 2

16

12

PB7

I/O

CT

X

ei3

X

X

Port B7

17

13

PD0 /AIN0

I/O

CT

X

X

X

X

X

Port D0

ADC Analog Input 0

18

14

PD1/AIN1

I/O

CT

X

X

X

X

X

Port D1

ADC Analog Input 1

19

15

PD2/AIN2

I/O

CT

X

X

X

X

X

Port D2

ADC Analog Input 2

20

16

PD3/AIN3

I/O

CT

X

X

X

X

X

Port D3

ADC Analog Input 3

21

-

PG6

I/O

TT

X

X

X

X

Port G6

22

-

PG7

I/O

TT

X

X

X

X

Port G7

23

17

PD4/AIN4

I/O

CT

X

X

X

X

X

Port D4

ADC Analog Input 4

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ST72521

Pin n°

Level

Port

Main

TQFP80

TQFP64

Type

Input

Output

float

wpu

int

ana

OD

PP

function

Pin Name

Input

Output

(after

Alternate function

reset)

24

18

PD5/AIN5

I/O

CT

X

X

X

X

X

Port D5

ADC Analog Input 5

25

19

PD6/AIN6

I/O

CT

X

X

X

X

X

Port D6

ADC Analog Input 6

26

20

PD7/AIN7

I/O

CT

X

X

X

X

X

Port D7

ADC Analog Input 7

27

21

VAREF

I

Analog Reference Voltage for ADC

28

22

VSSA

S

Analog Ground Voltage

29

23

VDD_3

S

Digital Main Supply Voltage

30

24

VSS_3

S

Digital Ground Voltage

31

-

PG4

I/O

TT

X

X

X

X

Port G4

32

-

PG5

I/O

TT

X

X

X

X

Port G5

33

25

PF0/MCO/AIN8

I/O

CT

X

ei1

X

X

X

Port F0

Main clock

ADC Analog

out (fOSC/2)

Input 8

34

26

PF1 (HS)/BEEP

I/O

CT

HS

X

ei1

X

X

Port F1

Beep signal output

35

27

PF2 (HS)

I/O

CT

HS

X

ei1

X

X

Port F2

X

Timer A Out-

ADC Analog

36

28

PF3/OCMP2_A/AIN9

I/O

CT

X

X

X

X

Port F3

put Compare

Input 9

2

37

29

PF4/OCMP1_A/AIN10

I/O

CT

X

Timer A Out-

ADC Analog

X

X

X

X

Port F4

put Compare

Input 10

1

38

30

PF5/ICAP2_A/AIN11

I/O

CT

X

X

X

X

X

Port F5

Timer A Input

ADC Analog

Capture 2

Input 11

39

31

PF6 (HS)/ICAP1_A

I/O

CT

HS

X

X

X

X

Port F6

Timer A Input Capture 1

40

32

PF7 (HS)/EXTCLK_A

I/O

CT

HS

X

X

X

X

Port F7

Timer A External Clock

Source

41

33

VDD_0

S

Digital Main Supply Voltage

42

34

VSS_0

S

Digital Ground Voltage

X

Timer B Out-

ADC Analog

43

35

PC0/OCMP2_B/AIN12

I/O

CT

X

X

X

X

Port C0

put Compare

Input 12

2

44

36

PC1/OCMP1_B/AIN13

I/O

CT

X

Timer B Out-

ADC Analog

X

X

X

X

Port C1

put Compare

Input 13

1

45

37

PC2 (HS)/ICAP2_B

I/O

CT

HS

X

X

X

X

Port C2

Timer B Input Capture 2

46

38

PC3 (HS)/ICAP1_B

I/O

CT

HS

X

X

X

X

Port C3

Timer B Input Capture 1

X

SPI Master In

ICC Data In-

47

39

PC4/MISO/ICCDATA

I/O

CT

X

X

X

Port C4

/ Slave Out

put

Data

SPI Master

ADC Analog

48

40

PC5/MOSI/AIN14

I/O

CT

X

X

X

X

X

Port C5

Out / Slave In

Input 14

Data

49

-

PH0

I/O

TT

X

X

X

X

Port H0

50

-

PH1

I/O

TT

X

X

X

X

Port H1

51

-

PH2

I/O

TT

X

X

X

X

Port H2

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ST72521

Pin n°

Level

Port

Main

TQFP80

TQFP64

Type

Input

Output

float

wpu

int

ana

OD

PP

function

Pin Name

Input

Output

(after

Alternate function

reset)

52

-

PH3

I/O

TT

X

X

X

X

Port H3

53

41

PC6/SCK/ICCCLK

I/O

CT

X

X

X

X

Port C6

SPI Serial

ICC Clock

Clock

Output

SPI Slave

ADC Analog

54

42

PC7/SS/AIN15

I/O

CT

X

X

X

X

X

Port C7

Select (active

Input 15

low)

55

43

PA0

I/O

CT

X

ei0

X

X

Port A0

56

44

PA1

I/O

CT

X

ei0

X

X

Port A1

57

45

PA2

I/O

CT

X

ei0

X

X

Port A2

58

46

PA3 (HS)

I/O

CT

HS

X

ei0

X

X

Port A3

59

47

VDD_1

S

Digital Main Supply Voltage

60

48

VSS_1

S

Digital Ground Voltage

61

49

PA4 (HS)

I/O

CT

HS

X

X

X

X

Port A4

62

50

PA5 (HS)

I/O

CT

HS

X

X

X

X

Port A5

63

51

PA6 (HS)/SDAI

I/O

CT

HS

X

T

Port A6

I2C Data 1)

64

52

PA7 (HS)/SCLI

I/O

CT

HS

X

T

Port A7

I2C Clock 1)

Must be tied low. In flash programming

mode, this pin acts as the programming

65

53

VPP/ ICCSEL

I

voltage input VPP. See Section 12.9.2

for more details. High voltage must not

be applied to ROM devices

66

54

RESET

I/O

CT

Top priority non maskable interrupt.

67

55

EVD

External voltage detector

68

56

TLI

I

CT

X

X

Top level interrupt input pin

69

-

PH4

I/O

TT

X

X

X

X

Port H4

70

-

PH5

I/O

TT

X

X

X

X

Port H5

71

-

PH6

I/O

TT

X

X

X

X

Port H6

72

-

PH7

I/O

TT

X

X

X

X

Port H7

73

57

VSS_2

S

Digital Ground Voltage

74

58

OSC23)

I/O

Resonator oscillator inverter output

75

59

OSC13)

I

External clock input or Resonator oscil-

lator inverter input

76

60

VDD_2

S

Digital Main Supply Voltage

77

61

PE0/TDO

I/O

CT

X

X

X

X

Port E0

SCI Transmit Data Out

78

62

PE1/RDI

I/O

CT

X

X

X

X

Port E1

SCI Receive Data In

79

63

PE2/CANTX

I/O

CT

X

Port E2

CAN Transmit Data Output

80

64

PE3/CANRX

I/O

CT

X

X

X

X

Port E3

CAN Receive Data Input

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,

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ST72521

else the configuration is floating interrupt input.

2.In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V DD are not implemented). See See “I/O PORTS” on page 47. and Section 12.8 I/O PORT PIN CHARACTERISTICS for more details.

3.OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for more details.

4.On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.

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ST72521

3 REGISTER & MEMORY MAP

As shown in Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 2Kbytes of RAM and up to 60Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

Figure 4. Memory Map

The highest address bytes contain the user reset and interrupt vectors.

IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the device.

0000h		0080h
	HW Registers		Short Addressing
	(see Table 2)
007Fh			RAM (zero page)
		00FFh
0080h
	RAM	0100h	256 Bytes Stack
	(2048 or 1024 Bytes)
		01FFh
				1000h
087Fh		0200h	16-bit Addressing		60 KBytes
0880h
	Reserved		RAM
		or 047Fh
0FFFh
		or 067Fh
1000h				8000h
	Program Memory	or 087Fh			32 KBytes
	(60K or 32K)
FFDFh
FFE0h	Interrupt & Reset Vectors
FFFFh	(see Table 7)			FFFFh

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					ST72521
Table 2. Hardware Register Map
Address	Block	Register	Register Name	Reset	Remarks
		Label		Status
0000h		PADR	Port A Data Register	00h1)	R/W
0001h	Port A	PADDR	Port A Data Direction Register	00h	R/W
0002h		PAOR	Port A Option Register	00h	R/W
0003h		PBDR	Port B Data Register	00h1)	R/W
0004h	Port B	PBDDR	Port B Data Direction Register	00h	R/W
0005h		PBOR	Port B Option Register	00h	R/W
0006h		PCDR	Port C Data Register	00h1)	R/W
0007h	Port C	PCDDR	Port C Data Direction Register	00h	R/W
0008h		PCOR	Port C Option Register	00h	R/W
0009h		PDDR	Port D Data Register	00h1)	R/W
000Ah	Port D	PDDDR	Port D Data Direction Register	00h	R/W
000Bh		PDOR	Port D Option Register	00h	R/W
000Ch		PEDR	Port E Data Register	00h1)	R/W
000Dh	Port E	PEDDR	Port E Data Direction Register	00h	R/W2)
000Eh		PEOR	Port E Option Register	00h	R/W2)
000Fh		PFDR	Port F Data Register	00h1)	R/W
0010h	Port F	PFDDR	Port F Data Direction Register	00h	R/W
0011h		PFOR	Port F Option Register	00h	R/W
0012h	Port G 2)	PGDR	Port G Data Register	00h1)	R/W
0013h		PGDDR	Port G Data Direction Register	00h	R/W
0014h		PGOR	Port G Option Register	00h	R/W
0015h	Port H 2)	PHDR	Port H Data Register	00h1)	R/W
0016h		PHDDR	Port H Data Direction Register	00h	R/W
0017h		PHOR	Port H Option Register	00h	R/W
0018h		I2CCR	I2C Control Register	00h	R/W
0019h		I2CSR1	I2C Status Register 1	00h	Read Only
001Ah		I2CSR2	I2C Status Register 2	00h	Read Only
001Bh	I2C	I2CCCR	I2C Clock Control Register	00h	R/W
001Ch		I2COAR1	I2C Own Address Register 1	00h	R/W
001Dh		I2COAR2	I2C Own Address Register2	00h	R/W
001Eh		I2CDR	I2C Data Register	00h	R/W
001Fh			Reserved Area (2 Bytes)
0020h
0021h		SPIDR	SPI Data I/O Register	xxh	R/W
0022h	SPI	SPICR	SPI Control Register	0xh	R/W
0023h		SPICSR	SPI Control/Status Register	00h	R/W

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ST72521

	Address	Block	Register	Register Name	Reset	Remarks
			Label		Status
	0024h		ISPR0	Interrupt Software Priority Register 0	FFh	R/W
	0025h		ISPR1	Interrupt Software Priority Register 1	FFh	R/W
	0026h	ITC	ISPR2	Interrupt Software Priority Register 2	FFh	R/W
	0027h		ISPR3	Interrupt Software Priority Register 3	FFh	R/W
	0028h		EICR	External Interrupt Control Register	00h	R/W
	0029h	FLASH	FCSR	Flash Control/Status Register	00h	R/W
	002Ah	WATCHDOG	WDGCR	Watchdog Control Register	7Fh	R/W
	002Bh		SICSR	System Integrity Control/Status Register	000x 000x b	R/W
	002Ch	MCC	MCCSR	Main Clock Control / Status Register	00h	R/W
	002Dh		MCCBCR	Main Clock Controller: Beep Control Register	00h	R/W
	002Eh
	to			Reserved Area (3 Bytes)
	0030h
	0031h		TACR2	Timer A Control Register 2	00h	R/W
	0032h		TACR1	Timer A Control Register 1	00h	R/W
	0033h		TACSR	Timer A Control/Status Register	xxxx x0xx b	R/W
	0034h		TAIC1HR	Timer A Input Capture 1 High Register	xxh	Read Only
	0035h		TAIC1LR	Timer A Input Capture 1 Low Register	xxh	Read Only
	0036h		TAOC1HR	Timer A Output Compare 1 High Register	80h	R/W
	0037h		TAOC1LR	Timer A Output Compare 1 Low Register	00h	R/W
	0038h	TIMER A	TACHR	Timer A Counter High Register	FFh	Read Only
	0039h		TACLR	Timer A Counter Low Register	FCh	Read Only
	003Ah		TAACHR	Timer A Alternate Counter High Register	FFh	Read Only
	003Bh		TAACLR	Timer A Alternate Counter Low Register	FCh	Read Only
	003Ch		TAIC2HR	Timer A Input Capture 2 High Register	xxh	Read Only
	003Dh		TAIC2LR	Timer A Input Capture 2 Low Register	xxh	Read Only
	003Eh		TAOC2HR	Timer A Output Compare 2 High Register	80h	R/W
	003Fh		TAOC2LR	Timer A Output Compare 2 Low Register	00h	R/W
	0040h			Reserved Area (1 Byte)
	0041h		TBCR2	Timer B Control Register 2	00h	R/W
	0042h		TBCR1	Timer B Control Register 1	00h	R/W
	0043h		TBCSR	Timer B Control/Status Register	xxxx x0xx b	R/W
	0044h		TBIC1HR	Timer B Input Capture 1 High Register	xxh	Read Only
	0045h		TBIC1LR	Timer B Input Capture 1 Low Register	xxh	Read Only
	0046h		TBOC1HR	Timer B Output Compare 1 High Register	80h	R/W
	0047h		TBOC1LR	Timer B Output Compare 1 Low Register	00h	R/W
	0048h	TIMER B	TBCHR	Timer B Counter High Register	FFh	Read Only
	0049h		TBCLR	Timer B Counter Low Register	FCh	Read Only
	004Ah		TBACHR	Timer B Alternate Counter High Register	FFh	Read Only
	004Bh		TBACLR	Timer B Alternate Counter Low Register	FCh	Read Only
	004Ch		TBIC2HR	Timer B Input Capture 2 High Register	xxh	Read Only
	004Dh		TBIC2LR	Timer B Input Capture 2 Low Register	xxh	Read Only
	004Eh		TBOC2HR	Timer B Output Compare 2 High Register	80h	R/W
	004Fh		TBOC2LR	Timer B Output Compare 2 Low Register	00h	R/W

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					ST72521
Address	Block	Register	Register Name	Reset	Remarks
		Label		Status
0050h		SCISR	SCI Status Register	C0h	Read Only
0051h		SCIDR	SCI Data Register	xxh	R/W
0052h		SCIBRR	SCI Baud Rate Register	00h	R/W
0053h	SCI	SCICR1	SCI Control Register 1	x000 0000b	R/W
0054h		SCICR2	SCI Control Register 2	00h	R/W
0055h		SCIERPR	SCI Extended Receive Prescaler Register	00h	R/W
0056h			Reserved area	---
0057h		SCIETPR	SCI Extended Transmit Prescaler Register	00h	R/W
0058h			Reserved Area (2 Bytes)
0059h
005Ah		CANISR	CAN Interrupt Status Register	00h	R/W
005Bh		CANICR	CAN Interrupt Control Register	00h	R/W
005Ch		CANCSR	CAN Control / Status Register	00h	R/W
005Dh		CANBRPR	CAN Baud Rate Prescaler Register	00h	R/W
005Eh	CAN	CANBTR	CAN Bit Timing Register	23h	R/W
005Fh		CANPSR	CAN Page Selection Register	00h	R/W
0060h			First address	--	See CAN
to			to		Description
006Fh			Last address of CAN page x
0070h		ADCCSR	Control/Status Register	00h	R/W
0071h	ADC	ADCDRH	Data High Register	00h	Read Only
0072h		ADCDRL	Data Low Register	00h	Read Only
0073h		PWMDCR3	PWM AR Timer Duty Cycle Register 3	00h	R/W
0074h		PWMDCR2	PWM AR Timer Duty Cycle Register 2	00h	R/W
0075h		PWMDCR1	PWM AR Timer Duty Cycle Register 1	00h	R/W
0076h		PWMDCR0	PWM AR Timer Duty Cycle Register 0	00h	R/W
0077h		PWMCR	PWM AR Timer Control Register	00h	R/W
0078h	PWM ART	ARTCSR	Auto-Reload Timer Control/Status Register	00h	R/W
0079h		ARTCAR	Auto-Reload Timer Counter Access Register	00h	R/W
007Ah		ARTARR	Auto-Reload Timer Auto-Reload Register	00h	R/W
007Bh		ARTICCSR	AR Timer Input Capture Control/Status Reg.	00h	R/W
007Ch		ARTICR1	AR Timer Input Capture Register 1	00h	Read Only
007Dh		ARTICR2	AR Timer Input Capture Register 1	00h	Read Only
007Eh			Reserved Area (2 Bytes)
007Fh

Legend: x=undefined, R/W=read/write

Notes:

1.The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

2.The bits associated with unavailable pins must always keep their reset value.

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4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply.

The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■Three Flash programming modes:

–Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased.

–ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board.

–IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running.

■ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM

■Read-out protection against piracy

■Register Access Security System (RASS) to prevent accidental programming or erasing

4.3 Structure

The Flash memory is organised in sectors and can be used for both code and data storage.

Figure 5. Memory Map and Sector Address

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).

Table 3. Sectors available in Flash devices

Flash Size (bytes)	Available Sectors
4K	Sector 0
8K	Sectors 0,1
> 8K	Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, makes it impossible to extract the memory content from the microcontroller, thus preventing piracy. Even ST cannot access the user code.

In flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed.

Read-out protection selection depends on the device type:

–In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

–In ROM devices it is enabled by mask option specified in the Option List.

Note: The LVD is not supported if read-out protection is enabled

4K

8K

10K

16K

24K

32K

48K

60K

FLASH

MEMORY SIZE

1000h

3FFFh

7FFFh

9FFFh

SECTOR 2

BFFFh

D7FFh

52 Kbytes

DFFFh

2 Kbytes

8 Kbytes

16 Kbytes

24 Kbytes

40 Kbytes

EFFFh

4 Kbytes

SECTOR 1

FFFFh

4 Kbytes

SECTOR 0

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ST72521

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 6). These pins are:

–RESET: device reset

–VSS: device power supply ground

–ICCCLK: ICC output serial clock pin

–ICCDATA: ICC input/output serial data pin

–ICCSEL/VPP: programming voltage

–OSC1(or OSCIN): main clock input for external source (optional)

–VDD: application board power supply (optional, see Figure 6, Note 3)

Figure 6. Typical ICC Interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

APPLICATION BOARD

OPTIONAL

(See Note 3)

APPLICATION CL2

POWER SUPPLY

				OSC2
V
	DD

					OPTIONAL
					(See Note 4)											9				7			5			3			1
																	10			8			6			4			2
								CL1						10kΩ
			OSC1									V								ICCSEL/VPP			RESET			ICCCLK				ICCDATA
													SS
								ST7

ICC CONNECTOR

HE10 CONNECTOR TYPE

APPLICATION

RESET SOURCE

See Note 2

See Note 1

APPLICATION

I/O

Notes:

1.If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2.During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset man-

agement IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3.The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4.Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

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ST72521

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool.

Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 6). For more details on the pin locations, refer to the device pinout description.

4.6 IAP (In-Application Programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI, USB

or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.7 Related Documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.

4.7.1 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 0000 0000 (00h)

7							0
0	0	0	0	0	0	0	0

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations. Flash Control/Status Register Address and Reset Value

	Address	Register	7	6	5	4	3	2	1	0
	(Hex.)	Label
	0029h	FCSR
		Reset Value	0	0	0	0	0	0	0	0

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ST72521

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■Enable executing 63 basic instructions

■Fast 8-bit by 8-bit multiply

■17 main addressing modes (with indirect addressing mode)

■Two 8-bit index registers

■16-bit stack pointer

■Low power HALT and WAIT modes

■Priority maskable hardware interrupts

■Non-maskable software/hardware interrupts

5.3 CPU REGISTERS

The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

Figure 7. CPU Registers

										7										0
																							ACCUMULATOR
												RESET VALUE = XXh
										7										0
																							X INDEX REGISTER
											RESET VALUE = XXh
										7										0
																							Y INDEX REGISTER
											RESET VALUE = XXh
					PCH			8			7				PCL					0			PROGRAM COUNTER
	15
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
										7										0
												1	1	I1	H	I0	N		Z	C			CONDITION CODE REGISTER
				RESET VALUE = 1									1	1 X		1	X		X	X
		15						8												0			STACK POINTER
											7
RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

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ST72521

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write

Reset Value: 111x1xxx

7							0
1	1	I1	H	I0	N	Z	C

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.

0:No half carry has occurred.

1:A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the result 7th bit.

0:The result of the last operation is positive or null.

1:The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

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Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0:The result of the last operation is different from zero.

1:The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0:No overflow or underflow has occurred.

1:An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt

The combination of the I1 and I0 bits gives the current interrupt software priority.

Interrupt Software Priority		I1	I0
Level 0	(main)	1	0
Level 1		0	1
Level 2		0	0
Level 3	(= interrupt disable)	1	1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

ST72521

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write

Reset Value: 01 FFh

15							8
0	0	0	0	0	0	0	1
7							0
SP7	SP6	SP5	SP4	SP3	SP2	SP1	SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

Figure 8. Stack Manipulation Example

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8.

–When an interrupt is received, the SP is decremented and the context is pushed on the stack.

–On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

CALL	Interrupt	PUSH Y	POP Y	IRET	RET
Subroutine	Event				or RSP

@ 0100h

SP

SP

SP

Y

CC

CC

CC

A

A

A

X

X

X

SP

PCH

PCH

PCH

SP

PCL

PCL

PCL

PCH

PCH

PCH

PCH

PCH

SP

@ 01FFh PCL

PCL

PCL

PCL

PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

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ST72521

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 10.

For more details, refer to dedicated parametric section.

Main features

■Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator)

■Reset Sequence Manager (RSM)

■Multi-Oscillator Clock Management (MO)

–5 Crystal/Ceramic resonator oscillators

–1 Internal RC oscillator

■System Integrity Management (SI)

–Main supply Low voltage detection (LVD)

–Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply or the EVD pin

–Clock Security System (CSS) with Clock Filter and Backup Safe Oscillator (enabled by op-

tion byte)

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply

the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL

is disabled, then fOSC2 = fOSC/2.

Caution: The PLL is not recommended for applications where timing accuracy is required. See “PLL Characteristics” on page 176.

Figure 9. PLL Block Diagram

fOSC			PLL x 2		0			fOSC2
			/ 2		1

PLL OPTION BIT

Figure 10. Clock, Reset and Supply Block Diagram

SYSTEM INTEGRITY MANAGEMENT

CLOCK SECURITY SYSTEM

(CSS)

OSC2

MULTI-

fOSC

fOSC2

CLOCK

SAFE

fOSC2

MAIN CLOCK

fCPU

CONTROLLER

OSCILLATOR

PLL

FILTER

OSC

WITH REALTIME

OSC1

(option)

(MO)

CLOCK (MCC/RTC)

RESET SEQUENCE

AVD Interrupt Request

WATCHDOG

RESET

MANAGER

SICSR

TIMER (WDG)

(RSM)

AVD AVD AVD LVD

0

CSS CSS WDG

S

IE

F

RF

IE

D

RF

CSS Interrupt Request

LOW VOLTAGE

VSS

DETECTOR

VDD

(LVD)

0

AUXILIARY VOLTAGE

EVD

1

DETECTOR

(AVD)

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ST72521

6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by three different source types coming from the multioscillator block:

■an external source

■4 crystal or ceramic resonator oscillators

■an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 4. Refer to the electrical characteristics section for more details.

Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Note: External clock source is not supported with the PLL enabled.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 14.1 on page 199 for more details on the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing.

In this mode, the two oscillator pins have to be tied to ground.

Table 4. ST7 Clock Sources

	Hardware Configuration
External Clock	ST7
	OSC1	OSC2
	EXTERNAL
	SOURCE
Resonators	ST7
	OSC1	OSC2
Crystal/Ceramic	CL1	CL2
	LOAD
	CAPACITORS
Internal RC Oscillator	ST7
	OSC1	OSC2
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ST72521

6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

The reset sequence manager includes three RESET sources as shown in Figure 12:

■External RESET source pulse

■Internal LVD RESET (Low Voltage Detection)

■Internal WATCHDOG RESET

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases as shown in Figure 11:

■Active Phase depending on the RESET source

■256 or 4096 CPU clock cycle delay (selected by option byte)

■RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application (see Section 14.1 on page 199).

Figure 12. Reset Block Diagram

The RESET vector fetch phase duration is 2 clock cycles.

Figure 11. RESET Sequence Phases

RESET

	Active Phase	INTERNAL RESET	FETCH
		256 or 4096 CLOCK CYCLES	VECTOR

6.3.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See “CONTROL PIN CHARACTERISTICS” on page 186 for more details.

A RESET signal originating from an external

source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 13). This de-

tection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

VDD

RON

Filter

INTERNAL

RESET

RESET

PULSE

WATCHDOG RESET

GENERATOR

LVD RESET

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ST72521

RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

If the external RESET pulse is shorter than

tw(RSTL)out (see short ext. Reset in Figure 13), the signal on the RESET pin may be stretched. Other-

wise the delay will not be applied (see long ext. Reset in Figure 13). Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least

tw(RSTL)out.

6.3.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. (see “OPERATING CONDITIONS” on page 164 )

Figure 13. RESET Sequences

A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin.

6.3.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■Power-On RESET

■Voltage Drop RESET

The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or VDD<VIT- (falling edge) as shown in Figure 13.

The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 13.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.

VDD

VIT+(LVD)

VIT-(LVD)

	LVD	SHORT EXT.
	RESET	RESET
	RUN	RUN
	ACTIVE PHASE	ACTIVE
		PHASE

LONG EXT.		WATCHDOG
RESET		RESET
RUN	RUN	RUN
ACTIVE		ACTIVE
PHASE		PHASE

tw(RSTL)out

tw(RSTL)out

th(RSTL)in

th(RSTL)in

tw(RSTL)out

DELAY

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

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ST72521

6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains the Low Voltage Detector (LVD), Auxiliary Voltage Detector (AVD) functions and Clock Security System (CSS). It is managed by the SICSR register.

6.4.1 Low Voltage Detector (LVD)

Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes:

–under full software control

–in static safe reset

The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.

The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when VDD is below:

–VIT+ when VDD is rising

–VIT- when VDD is falling

The LVD function is illustrated in Figure 14.

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

Notes:

The LVD allows the device to be used without any external RESET circuitry.

If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed.

The LVD is an optional function which can be selected by option byte.

Figure 14. Low Voltage Detector vs Reset

VDD

Vhys

VIT+

VIT-

RESET

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ST72521

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and

VIT+(AVD) reference value and the VDD main supply or the external EVD pin voltage level (VEVD). The VIT- reference value for falling voltage is lower

than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis).

The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only.

Caution: The AVD function is active only if the LVD is enabled through the option byte.

6.4.2.1 Monitoring the VDD Main Supply

This mode is selected by clearing the AVDS bit in the SICSR register.

The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see Section 14.1 on page 199).

If the AVD interrupt is enabled, an interrupt is gen-

erated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles).

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 15.

The interrupt on the rising edge is used to inform the application that the VDD warning state is over.

If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached.

If trv is greater than 256 or 4096 cycles then:

– If the AVD interrupt is enabled before the

VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE

bit is set, and the second when the threshold is reached.

–If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD interrupt will occur.

Figure 15. Using the AVD to Monitor VDD (AVDS bit=0)

VDD			Early Warning Interrupt
			(Power has dropped, MCU not
			not yet in reset)
VIT+(AVD)			Vhyst
VIT-(AVD)
VIT+(LVD)
VIT-(LVD)				trv VOLTAGE RISE TIME
AVDF bit	0	1	RESET VALUE	1	0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
			INTERRUPT PROCESS		INTERRUPT PROCESS
LVD RESET
					29/211

ST72521

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2.2 Monitoring a Voltage on the EVD pin

This mode is selected by setting the AVDS bit in the SICSR register.

The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set. This interrupt is generated on the rising and falling edges

of the comparator output. This means it is generated when either one of these two events occur:

–VEVD rises up to VIT+(EVD)

–VEVD falls down to VIT-(EVD)

The EVD function is illustrated in Figure 16.

For more details, refer to the Electrical Characteristics section.

Figure 16. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)

VEVD

Vhyst

VIT+(EVD)

VIT-(EVD)

AVDF

0

1

0

AVD INTERRUPT

REQUEST

IF AVDIE = 1

INTERRUPT PROCESS		INTERRUPT PROCESS

30/211