MOTOROLA MC14077BD, MC14077BDR2, MC14077BF, MC14077BFEL, MC14077BCP Datasheet
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MC14070B, MC14077B
CMOS SSI
Quad Exclusive ªORº and ªNORº Gates
The MC14070B quad exclusive OR gate and the MC14077B quad exclusive NOR gate are constructed with MOS P±channel and N±channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired.
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•All Outputs Buffered
•Capable of Driving Two Low±Power TTL Loads or One Low±Power Schottky TTL Load Over the Rated Temperature Range
•Double Diode Protection on All Inputs
•MC14070B Ð Replacement for CD4030B and CD4070B Types
•MC14077B Ð Replacement for CD4077B Type
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol |
Parameter |
Value |
Unit |
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VDD |
DC Supply Voltage Range |
± 0.5 to +18.0 |
V |
Vin, Vout |
Input or Output Voltage Range |
± 0.5 to VDD + 0.5 |
V |
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(DC or Transient) |
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Iin, Iout |
Input or Output Current |
± 10 |
mA |
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(DC or Transient) per Pin |
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PD |
Power Dissipation, |
500 |
mW |
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per Package (Note 3.) |
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TA |
Ambient Temperature Range |
± 55 to +125 |
°C |
Tstg |
Storage Temperature Range |
± 65 to +150 |
°C |
TL |
Lead Temperature |
260 |
°C |
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(8±Second Soldering) |
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2.Maximum Ratings are those values beyond which damage to the device may occur.
3.Temperature Derating:
Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
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MARKING |
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DIAGRAMS |
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14 |
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PDIP±14 |
MC140XXBCP |
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P SUFFIX |
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AWLYYWW |
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CASE 646 |
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1 |
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14 |
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SOIC±14 |
140XXB |
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D SUFFIX |
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AWLYWW |
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CASE 751A |
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1 |
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14 |
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SOEIAJ±14 |
MC140XXB |
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F SUFFIX |
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AWLYWW |
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CASE 965 |
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1 |
XX |
= Specific Device Code |
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A |
= Assembly Location |
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WL or L = Wafer Lot |
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YY or Y |
= Year |
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WW or W = Work Week |
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ORDERING INFORMATION |
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Device |
Package |
Shipping |
MC140XXBCP |
PDIP±14 |
2000/Box |
MC140XXBD |
SOIC±14 |
2750/Box |
MC140XXBDR2 |
SOIC±14 |
2500/Tape & Reel |
MC140XXBF |
SOEIAJ±14 |
See Note 1. |
MC140XXBFEL |
SOEIAJ±14 |
See Note 1. |
1.For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
Semiconductor Components Industries, LLC, 2000 |
1 |
Publication Order Number: |
March, 2000 ± Rev. 3 |
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MC14070B/D |
MC14070B, MC14077B
PIN ASSIGNMENT
IN 1A |
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1 |
14 |
VDD |
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IN 2A |
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2 |
13 |
IN 2D |
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OUTA |
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3 |
12 |
IN 1D |
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OUTB |
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4 |
11 |
OUTD |
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IN 1B |
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5 |
10 |
OUTC |
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IN 2B |
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6 |
9 |
IN 2C |
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VSS |
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7 |
8 |
IN 1C |
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MC14070B |
MC14077B |
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QUAD Exclusive OR |
QUAD Exclusive NOR |
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Gate |
Gate |
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1 |
1 |
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3 |
3 |
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2 |
2 |
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5 |
5 |
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4 |
4 |
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6 |
6 |
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8 |
8 |
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10 |
10 |
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9 |
9 |
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12 |
12 |
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11 |
11 |
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13 |
13 |
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VDD = PIN 14 |
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VSS = PIN 7 |
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(BOTH DEVICES) |
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20 ns |
20 ns |
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VDD |
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90% |
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50% |
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IDD |
Vin |
10% |
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1/f |
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Vin |
* |
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50% DUTY CYCLE |
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CL
*Inverted output on MC14077B only.
Figure 1. Power Dissipation Test Circuit and Waveform
VDD
VSS
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VDD |
20 ns |
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20 ns |
PULSE |
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INPUT |
90% |
VDD |
* |
50% |
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GENERATOR |
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# |
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10% |
VSS |
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tPHL |
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CL |
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tPLH |
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VSS |
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90% |
VOH |
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OUTPUT |
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50% |
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10% |
VOL |
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*Inverted output on MC14077B only. |
tTHL |
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tTLH |
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#Connect unused input to VDD for MC14070B, to VSS for MC14077B. |
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Figure 2. Switching Time Test Circuit and Waveforms
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MC14070B, MC14077B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
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VDD |
± 55_C |
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25_C |
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125_C |
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Characteristic |
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Symbol |
Vdc |
Min |
Max |
Min |
Typ (4.) |
Max |
Min |
Max |
Unit |
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Output Voltage |
ª0º Level |
VOL |
5.0 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
Vdc |
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Vin = VDD or 0 |
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10 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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15 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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ª1º Level |
VOH |
5.0 |
4.95 |
Ð |
4.95 |
5.0 |
Ð |
4.95 |
Ð |
Vdc |
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Vin = 0 or VDD |
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10 |
9.95 |
Ð |
9.95 |
10 |
Ð |
9.95 |
Ð |
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15 |
14.95 |
Ð |
14.95 |
15 |
Ð |
14.95 |
Ð |
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Input Voltage |
ª0º Level |
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VIL |
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Vdc |
(VO = 4.5 or 0.5 Vdc) |
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5.0 |
Ð |
1.5 |
Ð |
2.25 |
1.5 |
Ð |
1.5 |
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(VO = 9.0 or 1.0 Vdc) |
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10 |
Ð |
3.0 |
Ð |
4.50 |
3.0 |
Ð |
3.0 |
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(VO = 13.5 or 1.5 Vdc) |
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15 |
Ð |
4.0 |
Ð |
6.75 |
4.0 |
Ð |
4.0 |
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(VO = 0.5 or 4.5 Vdc) |
ª1º Level |
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VIH |
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5.0 |
3.5 |
Ð |
3.5 |
2.75 |
Ð |
3.5 |
Ð |
Vdc |
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(VO = 1.0 or 9.0 Vdc) |
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10 |
7.0 |
Ð |
7.0 |
5.50 |
Ð |
7.0 |
Ð |
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(VO = 1.5 or 13.5 Vdc) |
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15 |
11 |
Ð |
11 |
8.25 |
Ð |
11 |
Ð |
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Output Drive Current |
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IOH |
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mAdc |
(VOH = 2.5 Vdc) |
Source |
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5.0 |
± 3.0 |
Ð |
± 2.4 |
± 4.2 |
Ð |
± 1.7 |
Ð |
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(VOH = 4.6 Vdc) |
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5.0 |
± 0.64 |
Ð |
± 0.51 |
± 0.88 |
Ð |
± 0.36 |
Ð |
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(VOH = 9.5 Vdc) |
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10 |
± 1.6 |
Ð |
± 1.3 |
± 2.25 |
Ð |
± 0.9 |
Ð |
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(VOH = 13.5 Vdc) |
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15 |
± 4.2 |
Ð |
± 3.4 |
± 8.8 |
Ð |
± 2.4 |
Ð |
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(VOL = 0.4 Vdc) |
Sink |
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IOL |
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5.0 |
0.64 |
Ð |
0.51 |
0.88 |
Ð |
0.36 |
Ð |
mAdc |
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(VOL = 0.5 Vdc) |
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10 |
1.6 |
Ð |
1.3 |
2.25 |
Ð |
0.9 |
Ð |
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(VOL = 1.5 Vdc) |
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15 |
4.2 |
Ð |
3.4 |
8.8 |
Ð |
2.4 |
Ð |
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Input Current |
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Iin |
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15 |
Ð |
± 0.1 |
Ð |
± 0.00001 |
± 0.1 |
Ð |
± 1.0 |
μAdc |
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Input Capacitance |
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Cin |
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Ð |
Ð |
Ð |
Ð |
5.0 |
7.5 |
Ð |
Ð |
pF |
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(Vin = 0) |
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Quiescent Current |
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IDD |
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5.0 |
Ð |
0.25 |
Ð |
0.0005 |
0.25 |
Ð |
7.5 |
μAdc |
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(Per Package) |
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10 |
Ð |
0.5 |
Ð |
0.0010 |
0.5 |
Ð |
15 |
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15 |
Ð |
1.0 |
Ð |
0.0015 |
1.0 |
Ð |
30 |
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Total Supply Current (5.) (6.) |
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I |
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5.0 |
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I = (0.3 μA/kHz) f + I |
DD |
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μAdc |
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T |
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T |
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(Dynamic plus Quiescent, |
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10 |
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IT = (0.6 μA/kHz) f + IDD |
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Per Package) |
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15 |
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IT = (0.9 μA/kHz) f + IDD |
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(CL = 50 pF on all outputs, all |
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buffers switching) |
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Output Rise and Fall Times (5.) |
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t |
TLH |
, |
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ns |
(CL = 50 pF) |
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tTHL |
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tTLH, tTHL = (1.35 ns/pF) CL + 33 ns |
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5.0 |
Ð |
Ð |
Ð |
100 |
200 |
Ð |
Ð |
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tTLH, tTHL = (0.60 ns/pF) CL + 20 ns |
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10 |
Ð |
Ð |
Ð |
50 |
100 |
Ð |
Ð |
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tTLH, tTHL = (0.40 ns/pF) CL + 20 ns |
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15 |
Ð |
Ð |
Ð |
40 |
80 |
Ð |
Ð |
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Propagation Delay Times (5.) |
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t |
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, |
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ns |
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PLH |
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(CL = 50 pF) |
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tPHL |
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tPLH, tPHL = (0.90 ns/pF) CL + 130 ns |
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5.0 |
Ð |
Ð |
Ð |
175 |
350 |
Ð |
Ð |
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tPLH, tPHL = (0.36 ns/pF) CL + 57 ns |
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10 |
Ð |
Ð |
Ð |
75 |
150 |
Ð |
Ð |
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tPLH, tPHL = (0.26 ns/pF) CL + 37 ns |
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15 |
Ð |
Ð |
Ð |
55 |
110 |
Ð |
Ð |
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4.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.
5.The formulas given are for the typical characteristics only at 25_C.
6.To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL ± 50) Vfk
where: IT is in μH (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.002.
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