MOTOROLA MC14082BDR2, MC14082BF, MC14082BFR2, MC14082BCP, MC14081BFL2 Datasheet

MC14001B Series

B-Suffix Series CMOS Gates

MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B

The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired.

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•All Outputs Buffered

•Capable of Driving Two Low±power TTL Loads or One Low±power Schottky TTL Load Over the Rated Temperature Range.

•Double Diode Protection on All Inputs Except: Triple Diode Protection on MC14011B and MC14081B

•Pin±for±Pin Replacements for Corresponding CD4000 Series B Suffix Devices

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)

Symbol	Parameter	Value	Unit
VDD	DC Supply Voltage Range	± 0.5 to +18.0	V
Vin, Vout	Input or Output Voltage Range	± 0.5 to VDD + 0.5	V
	(DC or Transient)
Iin, Iout	Input or Output Current	± 10	mA
	(DC or Transient) per Pin
PD	Power Dissipation,	500	mW
	per Package (Note 2.)
TA	Ambient Temperature Range	± 55 to +125	°C
Tstg	Storage Temperature Range	± 65 to +150	°C
TL	Lead Temperature	260	°C
	(8±Second Soldering)

1.Maximum Ratings are those values beyond which damage to the device may occur.

2.Temperature Derating:

Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

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		MARKING
		DIAGRAMS
		14
	PDIP±14	MC140XXBCP
	P SUFFIX
		AWLYYWW
	CASE 646
		1
		14
	SOIC±14	140XXB
	D SUFFIX
		AWLYWW
	CASE 751A
		1
		14
	TSSOP±14	14
	DT SUFFIX	0XXB
	CASE 948G	ALYW
		1
		14
	SOEIAJ±14	MC140XXB
	F SUFFIX
		AWLYWW
	CASE 965
		1
XX	= Specific Device Code
A	= Assembly Location
WL or L = Wafer Lot
YY or Y	= Year
WW or W = Work Week
DEVICE INFORMATION
Device	Description
MC14001B	Quad 2±Input NOR Gate
MC14011B	Quad 2±Input NAND Gate
MC14023B	Triple 3±Input NAND Gate
MC14025B	Triple 3±Input NOR Gate
MC14071B	Quad 2±Input OR Gate
MC14073B	Triple 3±Input AND Gate
MC14081B	Quad 2±Input AND Gate
MC14082B	Dual 4±Input AND Gate

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 1		MC14001B/D

NOR

MC14001B

Quad 2±Input NOR Gate

1

3

2

INPUT2	5
	4

	6
	8	10
	9

12

11

13

MC14025B

Triple 3±Input NOR Gate

	1
	2	9
INPUT3	8
	5
	3
	4	6
	11
	12	10
	13

MC14001B

Quad 2±Input NOR Gate

IN 1A	1	14	VDD
IN 2A	2	13	IN 2D
OUTA	3	12	IN 1D
OUTB	4	11	OUTD
IN 1B	5	10	OUTC
IN 2B	6	9	IN 2C
VSS	7	8	IN 1C

MC14071B Quad 2±Input OR Gate

IN 1A	1	14	VDD
IN 2A	2	13	IN 2D
OUTA	3	12	IN 1D
OUTB	4	11	OUTD
IN 1B	5	10	OUTC
IN 2B	6	9	IN 2C
VSS	7	8	IN 1C

MC14001B Series

LOGIC DIAGRAMS

					NAND											OR												AND
				MC14011B											MC14071B											MC14081B
Quad 2±Input NAND Gate											Quad 2±Input OR Gate										Quad 2±Input AND Gate
1										3	1								3		1												3
2											2										2
5									4		5								4		5											4
6											6										6
8									10		8								10		8											10
9											9										9
12									11		12								11		12											11
13											13										13
				MC14023B										MC14073B												MC14082B
Triple 3±Input NAND Gate											Triple 3±Input AND Gate										Dual 4±Input AND Gate
1											1										2
2										9	2								9
																					3											1
8											8
																					4
3											3
																					5
4										6	4									6	9
5											5
																					10												13
11											11
																					11
12										10	12									10	12							NC = 6, 8
13											13									VDD = PIN 14
																				VSS = PIN 7
																			FOR ALL DEVICES
					PIN ASSIGNMENTS
			MC14011B											MC14023B											MC14025B
Quad 2±Input NAND Gate											Triple 3±Input NAND Gate										Triple 3±Input NOR Gate
IN 1A			1	14					VDD		IN 1A			1	14				VDD		IN 1A				1	14						VDD
IN 2A			2	13					IN 2D		IN 2A			2	13				IN 3C		IN 2A				2	13						IN 3C
OUTA			3	12					IN 1D		IN 1B			3	12				IN 2C		IN 1B				3	12						IN 2C
OUTB			4	11					OUTD		IN 2B			4	11				IN 1C		IN 2B				4	11						IN 1C
IN 1B			5	10					OUTC		IN 3B			5	10				OUTC		IN 3B				5	10						OUTC
IN 2B			6	9					IN 2C		OUTB			6	9				OUTA		OUTB				6	9						OUTA
VSS			7	8					IN 1C		VSS			7	8				IN 3A		VSS				7	8						IN 3A
			MC14073B											MC14081B											MC14082B
Triple 3±Input AND Gate											Quad 2±Input AND Gate										Dual 4±Input AND Gate
IN 1A			1	14					VDD		IN 1A			1	14				VDD		OUTA				1	14						VDD
IN 2A			2	13					IN 3C		IN 2A			2	13				IN 2D		IN 1A				2	13						OUTB
IN 1B			3	12					IN 2C		OUTA			3	12				IN 1D		IN 2A				3	12						IN 4B
IN 2B			4	11					IN 1C		OUTB			4	11				OUTD		IN 3A				4	11						IN 3B
IN 3B			5	10					OUTC		IN 1B			5	10				OUTC		IN 4A				5	10						IN 2B
OUTB			6	9					OUTA		IN 2B			6	9				IN 2C		NC				6	9						IN 1B
VSS			7	8					IN 3A		VSS			7	8				IN 1C		VSS				7	8						NC

NC = NO CONNECTION

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MC14001B Series

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD

± 55_C

25_C

125_C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ (3.)

Max

Min

Max

Unit

Output Voltage

ª0º Level

VOL

5.0

Ð

0.05

Ð

0

0.05

Ð

0.05

Vdc

Vin = VDD or 0

10

Ð

0.05

Ð

0

0.05

Ð

0.05

15

Ð

0.05

Ð

0

0.05

Ð

0.05

ª1º Level

VOH

5.0

4.95

Ð

4.95

5.0

Ð

4.95

Ð

Vdc

Vin = 0 or VDD

10

9.95

Ð

9.95

10

Ð

9.95

Ð

15

14.95

Ð

14.95

15

Ð

14.95

Ð

Input Voltage

ª0º Level

VIL

Vdc

(VO = 4.5 or 0.5 Vdc)

5.0

Ð

1.5

Ð

2.25

1.5

Ð

1.5

(VO = 9.0 or 1.0 Vdc)

10

Ð

3.0

Ð

4.50

3.0

Ð

3.0

(VO = 13.5 or 1.5 Vdc)

15

Ð

4.0

Ð

6.75

4.0

Ð

4.0

(VO = 0.5 or 4.5 Vdc)

ª1º Level

VIH

5.0

3.5

Ð

3.5

2.75

Ð

3.5

Ð

Vdc

(VO = 1.0 or 9.0 Vdc)

10

7.0

Ð

7.0

5.50

Ð

7.0

Ð

(VO = 1.5 or 13.5 Vdc)

15

11

Ð

11

8.25

Ð

11

Ð

Output Drive Current

IOH

mAdc

(VOH = 2.5 Vdc)

Source

5.0

± 3.0

Ð

± 2.4

± 4.2

Ð

± 1.7

Ð

(VOH = 4.6 Vdc)

5.0

± 0.64

Ð

± 0.51

± 0.88

Ð

± 0.36

Ð

(VOH = 9.5 Vdc)

10

± 1.6

Ð

± 1.3

± 2.25

Ð

± 0.9

Ð

(VOH = 13.5 Vdc)

15

± 4.2

Ð

± 3.4

± 8.8

Ð

± 2.4

Ð

(VOL = 0.4 Vdc)

Sink

IOL

5.0

0.64

Ð

0.51

0.88

Ð

0.36

Ð

mAdc

(VOL = 0.5 Vdc)

10

1.6

Ð

1.3

2.25

Ð

0.9

Ð

(VOL = 1.5 Vdc)

15

4.2

Ð

3.4

8.8

Ð

2.4

Ð

Input Current

Iin

15

Ð

± 0.1

Ð

± 0.00001

± 0.1

Ð

± 1.0

μAdc

Input Capacitance

Cin

Ð

Ð

Ð

Ð

5.0

7.5

Ð

Ð

pF

(Vin = 0)

Quiescent Current

IDD

5.0

Ð

0.25

Ð

0.0005

0.25

Ð

7.5

μAdc

(Per Package)

10

Ð

0.5

Ð

0.0010

0.5

Ð

15

15

Ð

1.0

Ð

0.0015

1.0

Ð

30

Total Supply Current (4.) (5.)

I

5.0

I = (0.3 μA/kHz) f + I

DD

/N

μAdc

T

T

(Dynamic plus Quiescent,

10

IT = (0.6 μA/kHz) f + IDD/N

Per Gate, CL = 50 pF)

15

IT = (0.9 μA/kHz) f + IDD/N

3.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

4.The formulas given are for the typical characteristics only at 25_C.

5.To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL ± 50) Vfk

where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package.

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MC14001B Series

B±SERIES GATE SWITCHING TIMES

SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)

		VDD		Typ (7.)
Characteristic	Symbol	Vdc	Min		Max	Unit
Output Rise Time, All B±Series Gates	tTLH					ns
tTLH = (1.35 ns/pF) CL + 33 ns		5.0	Ð	100	200
tTLH = (0.60 ns/pF) CL + 20 ns		10	Ð	50	100
tTLH = (0.40 ns/PF) CL + 20 ns		15	Ð	40	80
Output Fall Time, All B±Series Gates	tTHL					ns
tTHL = (1.35 ns/pF) CL + 33 ns		5.0	Ð	100	200
tTHL = (0.60 ns/pF) CL + 20 ns		10	Ð	50	100
tTHL = (0.40 ns/pF) CL + 20 ns		15	Ð	40	80
Propagation Delay Time	tPLH, tPHL					ns
MC14001B, MC14011B only
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns		5.0	Ð	125	250
tPLH, tPHL = (0.36 ns/pF) CL + 32 ns		10	Ð	50	100
tPLH, tPHL = (0.26 ns/pF) CL + 27 ns		15	Ð	40	80
All Other 2, 3, and 4 Input Gates
tPLH, tPHL = (0.90 ns/pF) CL + 115 ns		5.0	Ð	160	300
tPLH, tPHL = (0.36 ns/pF) CL + 47 ns		10	Ð	65	130
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns		15	Ð	50	100
8±Input Gates (MC14068B, MC14078B)
tPLH, tPHL = (0.90 ns/pF) CL + 155 ns		5.0	Ð	200	350
tPLH, tPHL = (0.36 ns/pF) CL + 62 ns		10	Ð	80	150
tPLH, tPHL = (0.26 ns/pF) CL + 47 ns		15	Ð	60	110

6.The formulas given are for the typical characteristics only at 25_C.

7.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

14	VDD	20 ns			20 ns	VDD
		INPUT		90%
INPUT				50%		0 V
PULSE	OUTPUT		tPHL	10%	tPLH
GENERATOR
*	CL			90%		VOH
		OUTPUT		50%
				10%		VOL
		INVERTING
			tTHL		tTLH
7	VSS	OUTPUT	tPLH		tPHL	VOH
				90%
*All unused inputs of AND, NAND gates must be connected to V .		NON±INVERTING		50%		VOL
				10%
	DD		tTLH		tTHL
All unused inputs of OR, NOR gates must be connected to VSS.

Figure 1. Switching Time Test Circuit and Waveforms

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