MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Complementary Pair
Plus Inverter
The MC14007UB multi±purpose device consists of three N±channel and three P±channel enhancement mode devices packaged to provide access to each device. These versatile parts are useful in inverter circuits, pulse± shapers, linear amplifiers, high input impedance amplifiers, threshold detectors, transmission gating, and functional gating.
•Diode Protection on All Inputs
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low±power TTL Loads or One Low±power Schottky TTL Load Over the Rated Temperature Range
•Pin±for±Pin Replacement for CD4007A or CD4007UB
•This device has 2 outputs without ESD Protection. Anti±static precautions must be taken.
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol |
Parameter |
Value |
|
Unit |
|
|
|
|
|
VDD |
DC Supply Voltage |
± 0.5 to + |
18.0 |
V |
Vin, Vout |
Input or Output Voltage (DC or Transient) |
± 0.5 to VDD + 0.5 |
V |
|
lin, lout |
Input or Output Current (DC or Transient), |
± 10 |
|
mA |
|
per Pin |
|
|
|
|
|
|
|
|
PD |
Power Dissipation, per Package² |
500 |
|
mW |
Tstg |
Storage Temperature |
± 65 to + |
150 |
_C |
TL |
Lead Temperature (8±Second Soldering) |
260 |
|
_C |
* Maximum Ratings are those values beyond which damage to the device may occur. ²Temperature Derating:
Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C Ceramic ªLº Packages: ± 12 mW/C From 100_C To 125_C
A
B
C |
INPUT |
INPUT |
OUTPUT CONDITION |
INPUT |
1 |
A = C, B = OPEN |
|
0 |
A = B, C = OPEN |
|
|
|
|
Substrates of P±channel devices internally connected to VDD; substrates of N±channel devices internally connected to VSS.
|
|
A |
|
12 |
9 |
|
1 |
B |
|
3 |
2 |
|
|
|
VDD |
5 |
4 |
14 |
|
C |
|
|
|
|
|
11 |
|
13 |
|
6 |
8 |
10 |
7 |
VSS |
|
Figure 1. Typical Application: 2±Input Analog Multiplexer
MC14007UB
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXUBCP |
Plastic |
MC14XXXUBCL |
Ceramic |
MC14XXXUBD |
SOIC |
TA = ± 55° to 125°C for all packages.
PIN ASSIGNMENT
|
D±PB |
1 |
|
14 |
VDD |
|
|
S±PB |
2 |
|
13 |
D±PA |
|
GATEB |
3 |
|
12 |
OUTC |
|
|
|
S±NB |
4 |
|
11 |
S±PC |
|
|
D±NB |
5 |
|
10 |
GATEC |
|
GATEA |
6 |
|
9 |
S±NC |
|
|
|
VSS |
7 |
|
8 |
D±NA |
|
|
|
D = DRAIN |
|
|
|
|
|
|
S = SOURCE |
|
|
||
|
|
SCHEMATIC |
|
|
||
14 |
13 |
|
2 |
1 |
|
11 |
6 |
|
|
|
|
|
12 |
7 |
8 |
3 |
4 |
5 |
10 |
9 |
|
|
VDD = PIN 14 |
|
|
||
|
|
VSS = PIN 7 |
|
|
||
REV 3 1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
|
|
|
VDD |
± 55_C |
|
25_C |
|
125_C |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
Characteristic |
|
Symbol |
Vdc |
Min |
Max |
Min |
Typ # |
Max |
Min |
Max |
Unit |
|
|
|
|
|
|
|
|
|
|
|
|
Output Voltage |
ª0º Leve |
VOL |
5.0 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
Vdc |
Vin = VDD or 0 |
|
|
10 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
|
|
|
|
15 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Vin = 0 or VDD |
ª1º Leve |
VOH |
5.0 |
4.95 |
Ð |
4.95 |
5.0 |
Ð |
4.95 |
Ð |
Vdc |
|
|
|
10 |
9.95 |
Ð |
9.95 |
10 |
Ð |
9.95 |
Ð |
|
|
|
|
15 |
14.95 |
Ð |
14.95 |
15 |
Ð |
14.95 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|
|
Input Voltage |
ª0º Leve |
VIL |
|
|
|
|
|
|
|
|
Vdc |
(VO = 4.5 Vdc) |
|
|
5.0 |
Ð |
1.0 |
Ð |
2.25 |
1.0 |
Ð |
1.0 |
|
(VO = 9.0 Vdc) |
|
|
10 |
Ð |
2.0 |
Ð |
4.50 |
2.0 |
Ð |
2.0 |
|
(VO = 13.5 Vdc) |
|
|
15 |
Ð |
2.5 |
Ð |
6.75 |
2.5 |
Ð |
2.5 |
|
(VO = 0.5 Vdc) |
ª1º Leve |
VIH |
5.0 |
4.0 |
Ð |
4.0 |
2.75 |
Ð |
4.0 |
Ð |
Vdc |
(VO = 1.0 Vdc) |
|
|
10 |
8.0 |
Ð |
8.0 |
5.50 |
Ð |
8.0 |
Ð |
|
(VO = 1.5 Vdc) |
|
|
15 |
12.5 |
Ð |
12.5 |
8.25 |
Ð |
12.5 |
Ð |
|
Output Drive Current |
|
IOH |
|
|
|
|
|
|
|
|
mAdc |
(VOH = 2.5 Vdc) |
Source |
|
5.0 |
± 3.0 |
Ð |
± 2.4 |
± 5.0 |
Ð |
± 1.7 |
Ð |
|
(VOH = 4.6 Vdc) |
|
|
5.0 |
± 0.64 |
Ð |
± 0.51 |
± 1.0 |
Ð |
± 0.36 |
Ð |
|
(VOH = 9.5 Vdc) |
|
|
10 |
± 1.6 |
Ð |
± 1.3 |
± 2.5 |
Ð |
± 0.9 |
Ð |
|
(VOH = 13.5 Vdc) |
|
|
15 |
± 4.2 |
Ð |
± 3.4 |
± 10 |
Ð |
± 2.4 |
Ð |
|
(VOL = 0.4 Vdc) |
Sink |
IOL |
5.0 |
0.64 |
Ð |
0.51 |
1.0 |
Ð |
0.36 |
Ð |
mAdc |
(VOL = 0.5 Vdc) |
|
|
10 |
1.6 |
Ð |
1.3 |
2.5 |
Ð |
0.9 |
Ð |
|
(VOL = 1.5 Vdc) |
|
|
15 |
4.2 |
Ð |
3.4 |
10 |
Ð |
2.4 |
Ð |
|
Input Current |
|
Iin |
15 |
Ð |
± 0.1 |
Ð |
± 0.00001 |
± 0.1 |
Ð |
± 1.0 |
μAdc |
Input Capacitance |
|
Cin |
Ð |
Ð |
Ð |
Ð |
5.0 |
7.5 |
Ð |
Ð |
pF |
(Vin = 0) |
|
|
|
|
|
|
|
|
|
|
|
Quiescent Current |
|
IDD |
5.0 |
Ð |
0.25 |
Ð |
0.0005 |
0.25 |
Ð |
7.5 |
μAdc |
(Per Package) |
|
|
10 |
Ð |
0.5 |
Ð |
0.0010 |
0.5 |
Ð |
15 |
|
|
|
|
15 |
Ð |
1.0 |
Ð |
0.0015 |
1.0 |
Ð |
30 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Total Supply Current**² |
|
IT |
5.0 |
|
|
IT = (0.7 μA/kHz) f + IDD/6 |
|
|
μAdc |
||
(Dynamic plus Quiescent, |
|
10 |
|
|
IT = (1.4 μA/kHz) f + IDD/6 |
|
|
|
|||
Per Gate) (CL = 50 pF) |
|
|
15 |
|
|
IT = (2.2 μA/kHz) f + IDD/6 |
|
|
|
||
#Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C.
²T o calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL ± 50) Vfk
where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.003.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14007UB |
MOTOROLA CMOS LOGIC DATA |
32 |
|
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