MC14060B
14-Bit Binary Counter and
Oscillator
The MC14060B is a 14±stage binary ripple counter with an on±chip oscillator buffer. The oscillator configuration allows design of either RC or crystal oscillator circuits. Also included on the chip is a reset function which places all outputs into the zero state and disables the oscillator. A negative transition on Clock will advance the counter to the next state. Schmitt trigger action on the input line permits very slow input rise and fall times. Applications include time delay circuits, counter controls, and frequency dividing circuits.
•Fully static operation
•Diode Protection on All Inputs
•Supply Voltage Range = 3.0 V to 18 V
•Capable of Driving Two Low±power TTL Loads or One Low±power Schottky TTL Load Over the Rated Temperature Range
•Buffered Outputs Available from Stages 4 Through 10 and 12 Through 14
•Common Reset Line
•Pin±for±Pin Replacement for CD4060B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol |
Parameter |
Value |
Unit |
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VDD |
DC Supply Voltage Range |
± 0.5 to +18.0 |
V |
Vin, Vout |
Input or Output Voltage Range |
± 0.5 to VDD + 0.5 |
V |
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(DC or Transient) |
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Iin, Iout |
Input or Output Current |
± 10 |
mA |
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(DC or Transient) per Pin |
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PD |
Power Dissipation, |
500 |
mW |
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per Package (Note 3.) |
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TA |
Ambient Temperature Range |
± 55 to +125 |
°C |
Tstg |
Storage Temperature Range |
± 65 to +150 |
°C |
TL |
Lead Temperature |
260 |
°C |
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(8±Second Soldering) |
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2.Maximum Ratings are those values beyond which damage to the device may occur.
3.Temperature Derating:
Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
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MARKING |
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DIAGRAMS |
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16 |
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PDIP±16 |
MC14060BCP |
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P SUFFIX |
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AWLYYWW |
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CASE 648 |
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1 |
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16 |
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SOIC±16 |
14060B |
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D SUFFIX |
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AWLYWW |
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CASE 751B |
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1 |
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16 |
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TSSOP±16 |
14 |
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DT SUFFIX |
060B |
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CASE 948F |
ALYW |
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1 |
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16 |
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SOEIAJ±16 |
MC14060B |
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F SUFFIX |
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AWLYWW |
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CASE 966 |
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1 |
A |
= Assembly Location |
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WL or L = Wafer Lot |
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YY or Y |
= Year |
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WW or W = Work Week |
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ORDERING INFORMATION |
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Device |
Package |
Shipping |
MC14060BCP |
PDIP±16 |
2000/Box |
MC14060BD |
SOIC±16 |
2400/Box |
MC14060BDR2 |
SOIC±16 |
2500/Tape & Reel |
MC14060BDT |
TSSOP±16 |
96/Rail |
MC14060BDTR2 |
TSSOP±16 |
2500/Tape & Reel |
MC14060BF |
SOEIAJ±16 |
See Note 1. |
MC14060BFEL |
SOEIAJ±16 |
See Note 1. |
1.For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
Semiconductor Components Industries, LLC, 2000 |
1 |
Publication Order Number: |
March, 2000 ± Rev. 3 |
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MC14060B/D |
OUT 2
9
OUT 1
10
CLOCK
11
RESET
12
MC14060B
PIN ASSIGNMENT
Q12 |
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1 |
16 |
VDD |
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Q13 |
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2 |
15 |
Q10 |
Q14 |
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3 |
14 |
Q8 |
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Q6 |
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4 |
13 |
Q9 |
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Q5 |
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5 |
12 |
RESET |
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Q7 |
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6 |
11 |
CLOCK |
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Q4 |
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7 |
10 |
OUT 1 |
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VSS |
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8 |
9 |
OUT 2 |
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TRUTH TABLE
Clock |
Reset |
Output State |
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L |
No Change |
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L |
Advance to next state |
X |
H |
All Outputs are low |
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X = Don't Care
LOGIC DIAGRAM
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Q4 |
Q5 |
Q12 |
Q13 |
Q14 |
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7 |
5 |
1 |
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2 |
3 |
C Q |
C Q |
C Q |
C Q |
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C Q |
C Q |
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C R Q |
C R Q |
C R Q |
C R Q |
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C R Q |
C R Q |
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Q6 = PIN 4 |
Q8 = PIN 14 |
Q10 = PIN 15 |
VDD = PIN 16 |
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Q7 = PIN 6 |
Q9 = PIN 13 |
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VSS = PIN 8 |
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MC14060B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
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VDD |
± 55_C |
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25_C |
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125_C |
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Characteristic |
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Symbol |
Vdc |
Min |
Max |
Min |
Typ (4.) |
Max |
Min |
Max |
Unit |
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Output Voltage |
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ª0º Level |
VOL |
5.0 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
V |
Vin = VDD or 0 |
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10 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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15 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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Vin = 0 or VDD |
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ª1º Level |
VOH |
5.0 |
4.95 |
Ð |
4.95 |
5.0 |
Ð |
4.95 |
Ð |
V |
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10 |
9.95 |
Ð |
9.95 |
10 |
Ð |
9.95 |
Ð |
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15 |
14.95 |
Ð |
14.95 |
15 |
Ð |
14.95 |
Ð |
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Input Voltage |
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ª0º Level |
VIL |
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V |
(VO = 4.5 or 0.5 V) |
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5.0 |
Ð |
1.5 |
Ð |
2.25 |
1.5 |
Ð |
1.5 |
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(VO = 9.0 or 1.0 V) |
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10 |
Ð |
3.0 |
Ð |
4.50 |
3.0 |
Ð |
3.0 |
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(VO = 13.5 or 1.5 V) |
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15 |
Ð |
4.0 |
Ð |
6.75 |
4.0 |
Ð |
4.0 |
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(VO = 0.5 or 4.5 V) |
ª1º Level |
VIH |
5.0 |
3.5 |
Ð |
3.5 |
2.75 |
Ð |
3.5 |
Ð |
V |
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(VO = 1.0 or 9.0 V) |
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10 |
7.0 |
Ð |
7.0 |
5.50 |
Ð |
7.0 |
Ð |
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(VO = 1.5 or 13.5 V) |
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15 |
11.0 |
Ð |
11.0 |
8.25 |
Ð |
11.0 |
Ð |
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Input Voltage |
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ª0º Level |
VIL |
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Vdc |
(VO = 4.5 Vdc) |
(For Input 11 |
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5.0 |
Ð |
1.0 |
Ð |
2.25 |
1.0 |
Ð |
1.0 |
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(VO = 9.0 Vdc) |
and Output 10) |
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10 |
Ð |
2.0 |
Ð |
4.50 |
2.0 |
Ð |
2.0 |
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(VO = 13.5 Vdc) |
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15 |
Ð |
2.5 |
Ð |
6.75 |
2.5 |
Ð |
2.5 |
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(VO = 0.5 Vdc) |
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ª1º Level |
VIH |
5.0 |
4.0 |
Ð |
4.0 |
2.75 |
Ð |
4.0 |
Ð |
Vdc |
(VO = 1.0 Vdc) |
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10 |
8.0 |
Ð |
8.0 |
5.50 |
Ð |
8.0 |
Ð |
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(VO = 1.5 Vdc) |
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15 |
12.5 |
Ð |
12.5 |
8.25 |
Ð |
12.5 |
Ð |
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Output Drive Current |
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IOH |
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mA |
(VOH = 2.5 V) |
(Except Source |
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5.0 |
± 3.0 |
Ð |
± 2.4 |
± 4.2 |
Ð |
± 1.7 |
Ð |
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(VOH = 4.6 V) |
Pins 9 and 10) |
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5.0 |
± 0.64 |
Ð |
± 0.51 |
± 0.88 |
Ð |
± 0.36 |
Ð |
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(VOH = 9.5 V) |
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10 |
± 1.6 |
Ð |
± 1.3 |
± 2.25 |
Ð |
± 0.9 |
Ð |
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(VOH = 13.5 V) |
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15 |
± 4.2 |
Ð |
± 3.4 |
± 8.8 |
Ð |
± 2.4 |
Ð |
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(VOL = 0.4 V) |
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Sink |
IOL |
5.0 |
0.64 |
Ð |
0.51 |
0.88 |
Ð |
0.36 |
Ð |
mA |
(VOL = 0.5 V) |
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10 |
1.6 |
Ð |
1.3 |
2.25 |
Ð |
0.9 |
Ð |
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(VOL = 1.5 V) |
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15 |
4.2 |
Ð |
3.4 |
8.8 |
Ð |
2.4 |
Ð |
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Input Current |
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Iin |
15 |
Ð |
± 0.1 |
Ð |
± 0.00001 |
± 0.1 |
Ð |
± 1.0 |
μA |
Input Capacitance (Vin = 0) |
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Cin |
Ð |
Ð |
Ð |
Ð |
5.0 |
7.5 |
Ð |
Ð |
pF |
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Quiescent Current |
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IDD |
5.0 |
Ð |
5.0 |
Ð |
0.005 |
5.0 |
Ð |
150 |
μA |
(Per Package) |
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10 |
Ð |
10 |
Ð |
0.010 |
10 |
Ð |
300 |
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15 |
Ð |
20 |
Ð |
0.015 |
20 |
Ð |
600 |
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Total Supply Current (5.) (6.) |
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I |
5.0 |
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I = (0.25 μA/kHz) f + I |
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μA |
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T |
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T |
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DD |
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(Dynamic plus Quiescent, |
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10 |
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IT = (0.54 μA/kHz) f + IDD |
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Per Package) |
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15 |
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IT = (0.85 μA/kHz) f + IDD |
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(CL = 50 pF on all outputs, |
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all buffers switching) |
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4.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.
5.The formulas given are for the typical characteristics only at 25_C.
6.To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL ± 50) Vfk
where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.002.
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