MOTOROLA MC14094BFR1, MC14094BFR2, MC14094BDTR2, MC14094BF, MC14094BFEL Datasheet

MC14094B

8-Stage Shift/Store Register with Three-State Outputs

The MC14094B combines an 8±stage shift register with a data latch for each stage and a three±state output from each latch.

Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QS output data is for use in high±speed cascaded systems. The Q′S output data is shifted on the following negative clock transition for use in low±speed cascaded systems.

Data from each stage of the shift register is latched on the negative transition of the strobe input. Data propagates through the latch while strobe is high.

Outputs of the eight data latches are controlled by three±state buffers which are placed in the high±impedance state by a logic Low on Output Enable.

•Three±State Outputs

•Capable of Driving Two Low±Power TTL Loads or One Low±Power Schottky TTL Load Over the Rated Temperature Range

•Input Diode Protection

•Data Latch

•Dual Outputs for Data Out on Both Positive and Negative Clock Transitions

•Useful for Serial±to±Parallel Data Conversion

•Pin±for±Pin Compatible with CD4094B

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol	Parameter	Value	Unit
VDD	DC Supply Voltage Range	± 0.5 to +18.0	V
Vin, Vout	Input or Output Voltage Range	± 0.5 to VDD + 0.5	V
	(DC or Transient)
Iin, Iout	Input or Output Current	± 10	mA
	(DC or Transient) per Pin
PD	Power Dissipation,	500	mW
	per Package (Note 3.)
TA	Ambient Temperature Range	± 55 to +125	°C
Tstg	Storage Temperature Range	± 65 to +150	°C
TL	Lead Temperature	260	°C
	(8±Second Soldering)

2.Maximum Ratings are those values beyond which damage to the device may occur.

3.Temperature Derating:

Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

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		MARKING
		DIAGRAMS
		16
	PDIP±16	MC14094BCP
	P SUFFIX
		AWLYYWW
	CASE 648
		1
		16
	SOIC±16	14094B
	D SUFFIX
		AWLYWW
	CASE 751B
		1
		16
	TSSOP±16	14
	DT SUFFIX	094B
	CASE 948F	ALYW
		1
		16
	SOEIAJ±16	MC14094B
	F SUFFIX
		AWLYWW
	CASE 966
		1
A	= Assembly Location
WL or L = Wafer Lot
YY or Y	= Year
WW or W = Work Week
ORDERING INFORMATION
Device	Package	Shipping
MC14094BCP	PDIP±16	2000/Box
MC14094BD	SOIC±16	48/Rail
MC14094BDR2	SOIC±16	2500/Tape & Reel
MC14094BDT	TSSOP±16	96/Rail
MC14094BDTR2	TSSOP±16	2500/Tape & Reel
MC14094BF	SOEIAJ±16	See Note 1.

1.For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 3		MC14094B/D

MC14094B

PIN ASSIGNMENT

STROBE		1	16	VDD
DATA		2	15	OUTPUT
				ENABLE
CLOCK
		3	14	Q5
Q1		4	13	Q6
Q2		5	12	Q7
Q3		6	11	Q8
Q4		7	10	Q′S
VSS		8	9	QS

	Output			Parallel Outputs		Serial Outputs
Clock	Enable	Strobe	Data	Q1	QN	QS*	Q′S
	0	X	X	Z	Z	Q7	No Chg.
	0	X	X	Z	Z	No Chg.	Q7
	1	0	X	No Chg.	No Chg.	Q7	No Chg.
	1	1	0	0	QN±1	Q7	No Chg.
	1	1	1	1	QN±1	Q7	No Chg.
	1	1	1	No Chg.	No Chg.	No Chg.	Q7
Z = High Impedance		X = Don't Care

* At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS.

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MC14094B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD

± 55_C

25_C

125_C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ (4.)

Max

Min

Max

Unit

Output Voltage

ª0º Level

VOL

5.0

Ð

0.05

Ð

0

0.05

Ð

0.05

Vdc

Vin = VDD or 0

10

Ð

0.05

Ð

0

0.05

Ð

0.05

15

Ð

0.05

Ð

0

0.05

Ð

0.05

ª1º Level

VOH

5.0

4.95

Ð

4.95

5.0

Ð

4.95

Ð

Vdc

Vin = 0 or VDD

10

9.95

Ð

9.95

10

Ð

9.95

Ð

15

14.95

Ð

14.95

15

Ð

14.95

Ð

Input Voltage

ª0º Level

VIL

Vdc

(VO = 4.5 or 0.5 Vdc)

5.0

Ð

1.5

Ð

2.25

1.5

Ð

1.5

(VO = 9.0 or 1.0 Vdc)

10

Ð

3.0

Ð

4.50

3.0

Ð

3.0

(VO = 13.5 or 1.5 Vdc)

15

Ð

4.0

Ð

6.75

4.0

Ð

4.0

(VO = 0.5 or 4.5 Vdc)

ª1º Level

VIH

5.0

3.5

Ð

3.5

2.75

Ð

3.5

Ð

Vdc

(VO = 1.0 or 9.0 Vdc)

10

7.0

Ð

7.0

5.50

Ð

7.0

Ð

(VO = 1.5 or 13.5 Vdc)

15

11

Ð

11

8.25

Ð

11

Ð

Output Drive Current

IOH

mAdc

(VOH = 2.5 Vdc)

Source

5.0

± 3.0

Ð

± 2.4

± 4.2

Ð

± 1.7

Ð

(VOH = 4.6 Vdc)

5.0

± 0.64

Ð

± 0.51

± 0.88

Ð

± 0.36

Ð

(VOH = 9.5 Vdc)

10

± 1.6

Ð

± 1.3

± 2.25

Ð

± 0.9

Ð

(VOH = 13.5 Vdc)

15

± 4.2

Ð

± 3.4

± 8.8

Ð

± 2.4

Ð

(VOL = 0.4 Vdc)

Sink

IOL

5.0

0.64

Ð

0.51

0.88

Ð

0.36

Ð

mAdc

(VOL = 0.5 Vdc)

10

1.6

Ð

1.3

2.25

Ð

0.9

Ð

(VOL = 1.5 Vdc)

15

4.2

Ð

3.4

8.8

Ð

2.4

Ð

Input Current

Iin

15

Ð

± 0.1

Ð

± 0.00001

± 0.1

Ð

± 1.0

μAdc

Input Capacitance

Cin

Ð

Ð

Ð

Ð

5.0

7.5

Ð

Ð

pF

(Vin = 0)

Quiescent Current

IDD

5.0

Ð

5.0

Ð

0.005

5.0

Ð

150

μAdc

(Per Package)

10

Ð

10

Ð

0.010

10

Ð

300

15

Ð

20

Ð

0.015

20

Ð

600

Total Supply Current (5.) (6.)

I

5.0

I = (4.1 μA/kHz) f + I

DD

μAdc

T

T

(Dynamic plus Quiescent,

10

IT = (14 μA/kHz) f + IDD

Per Package)

15

IT = (140 μA/kHz) f + IDD

(CL = 50 pF on all outputs, all

buffers switching)

3±State Output Leakage Current

ITL

15

Ð

± 0.1

Ð

± 0.0001

± 0.1

Ð

± 3.0

μA

4.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

5.The formulas given are for the typical characteristics only at 25_C.

6.To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL ± 50) Vfk

where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.001.

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