MOTOROLA MC14541BCP, MC14541BFL1, MC14541BFR2, MC14541BF, MC14541BD Datasheet

MC14541B

Programmable Timer

The MC14541B programmable timer consists of a 16±stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, an automatic power±on reset circuit, and output control logic.

Timing is initialized by turning on power, whereupon the power±on reset is enabled and initializes the counter, within the specified VDD range. With the power already on, an external reset pulse can be applied. Upon release of the initial reset command, the oscillator will oscillate with a frequency determined by the external RC network. The 16±stage counter divides the oscillator frequency (fosc) with the nth stage frequency being fosc/2n.

•Available Outputs 28, 210, 213 or 216

•Increments on Positive Edge Clock Transitions

•Built±in Low Power RC Oscillator (± 2% accuracy over temperature range and ± 20% supply and ± 3% over processing at < 10 kHz)

•Oscillator May Be Bypassed if External Clock Is Available (Apply external clock to Pin 3)

•External Master Reset Totally Independent of Automatic Reset Operation

•Operates as 2n Frequency Divider or Single Transition Timer

•Q/Q Select Provides Output Logic Level Flexibility

•Reset (auto or master) Disables Oscillator During Resetting to Provide No Active Power Dissipation

•Clock Conditioning Circuit Permits Operation with Very Slow Clock Rise and Fall Times

•Automatic Reset Initializes All Counters On Power Up

•Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset

Disabled (Pin 5 = VDD)

=8.5 Vdc to 18 Vdc with Auto Reset Enabled (Pin 5 = VSS)

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol	Parameter	Value	Unit
VDD	DC Supply Voltage Range	± 0.5 to +18.0	V
Vin, Vout	Input or Output Voltage Range	± 0.5 to VDD + 0.5	V
	(DC or Transient)
Iin	Input Current (DC or Transient)	± 10 (per Pin)	mA
Iout	Output Current (DC or Transient)	± 45 (per Pin)	mA
PD	Power Dissipation,	500	mW
	per Package (Note 3.)
TA	Ambient Temperature Range	± 55 to +125	°C
Tstg	Storage Temperature Range	± 65 to +150	°C
TL	Lead Temperature	260	°C
	(8±Second Soldering)

2.Maximum Ratings are those values beyond which damage to the device may occur.

3.Temperature Derating:

Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C

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		MARKING
		DIAGRAMS
	14
	PDIP±14	MC14541BCP
	P SUFFIX
		AWLYYWW
	CASE 646
		1
	14
	SOIC±14	14541B
	D SUFFIX
		AWLYWW
	CASE 751A
		1
	TSSOP±14	14
		14
	DT SUFFIX	541B
	CASE 948G	ALYW
		1
	14
	SOEIAJ±14	MC14541B
	F SUFFIX
		AWLYWW
	CASE 965
		1
A	= Assembly Location
WL or L = Wafer Lot
YY or Y	= Year
WW or W = Work Week
ORDERING INFORMATION
Device	Package	Shipping
MC14541BCP	PDIP±14	2000/Box
MC14541BD	SOIC±14	55/Rail
MC14541BDR2	SOIC±14	2500/Tape & Reel
MC14541BDT	TSSOP±14	96/Rail
MC14541BDTR2	TSSOP±14	2500/Tape & Reel
MC14541BF	SOEIAJ±14	See Note 1.
MC14541BFEL	SOEIAJ±14	See Note 1.

1.For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 6		MC14541B/D

MC14541B

PIN ASSIGNMENT

Rtc	1	14	VDD
Ctc	2	13	B
RS	3	12	A
NC	4	11	NC
AR	5	10	MODE
MR	6	9			SEL
			Q/Q
VSS	7	8	Q

NC = NO CONNECTION

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD

± 55_C

25_C

125_C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ (4.)

Max

Min

Max

Unit

Output Voltage

ª0º Level

VOL

5.0

Ð

0.05

Ð

0

0.05

Ð

0.05

Vdc

Vin = VDD or 0

10

Ð

0.05

Ð

0

0.05

Ð

0.05

15

Ð

0.05

Ð

0

0.05

Ð

0.05

Vin = 0 or VDD

ª1º Level

VOH

5.0

4.95

Ð

4.95

5.0

Ð

4.95

Ð

Vdc

10

9.95

Ð

9.95

10

Ð

9.95

Ð

15

14.95

Ð

14.95

15

Ð

14.95

Ð

Input Voltage

ª0º Level

VIL

Vdc

(VO = 4.5 or 0.5 Vdc)

5.0

Ð

1.5

Ð

2.25

1.5

Ð

1.5

(VO = 9.0 or 1.0 Vdc)

10

Ð

3.0

Ð

4.50

3.0

Ð

3.0

(VO = 13.5 or 1.5 Vdc)

15

Ð

4.0

Ð

6.75

4.0

Ð

4.0

(VO = 0.5 or 4.5 Vdc)

ª1º Level

VIH

5.0

3.5

Ð

3.5

2.75

Ð

3.5

Ð

Vdc

(VO = 1.0 or 9.0 Vdc)

10

7.0

Ð

7.0

5.50

Ð

7.0

Ð

(VO = 1.5 or 13.5 Vdc)

15

11

Ð

11

8.25

Ð

11

Ð

Output Drive Current

IOH

mAdc

(VOH = 2.5 Vdc)

Source

5.0

± 7.96

Ð

± 6.42

± 12.83

Ð

± 4.49

Ð

(VOH = 9.5 Vdc)

10

± 4.19

Ð

± 3.38

± 6.75

Ð

± 2.37

Ð

(VOH = 13.5 Vdc)

15

± 16.3

Ð

± 13.2

± 26.33

Ð

± 9.24

Ð

(VOL = 0.4 Vdc)

Sink

IOL

5.0

1.93

Ð

1.56

3.12

Ð

1.09

Ð

mAdc

(VOL = 0.5 Vdc)

10

4.96

Ð

4.0

8.0

Ð

2.8

Ð

(VOL = 1.5 Vdc)

15

19.3

Ð

15.6

31.2

Ð

10.9

Ð

Input Current

Iin

15

Ð

± 0.1

Ð

± 0.00001

± 0.1

Ð

± 1.0

μAdc

Input Capacitance

Cin

Ð

Ð

Ð

Ð

5.0

7.5

Ð

Ð

pF

(Vin = 0)

Quiescent Current

IDD

5.0

Ð

5.0

Ð

0.005

5.0

Ð

150

μAdc

(Pin 5 is High)

10

Ð

10

Ð

0.010

10

Ð

300

Auto Reset Disabled

15

Ð

20

Ð

0.015

20

Ð

600

Auto Reset Quiescent Current

IDDR

10

Ð

250

Ð

30

250

Ð

1500

μAdc

(Pin 5 is low)

15

Ð

500

Ð

82

500

Ð

2000

Supply Current (5.) (6.)

I

5.0

I = (0.4 μA/kHz) f + I

DD

μAdc

D

D

(Dynamic plus Quiescent)

10

ID = (0.8 μA/kHz) f + IDD

15

ID = (1.2 μA/kHz) f + IDD

4.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

5.The formulas given are for the typical characteristics only at 25_C.

6.When using the on chip oscillator the total supply current (in μAdc) becomes: IT = ID + 2 Ctc VDD f x 10±3 where ID is in μA, Ctc is in pF, VDD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during power±on with automatic reset enabled is typically 50 μA @ VDD = 10 Vdc.

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MC14541B

SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)

Characteristic	Symbol	V	Min	Typ (8.)	Max	Unit
		DD
Output Rise and Fall Time	tTLH,					ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns	tTHL	5.0	Ð	100	200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns		10	Ð	50	100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns		15	Ð	40	80
Propagation Delay, Clock to Q (28 Output)	t					μs
tPLH, tPHL = (1.7 ns/pF) CL + 3415 ns	PLH
	tPHL	5.0	Ð	3.5	10.5
tPLH, tPHL = (0.66 ns/pF) CL + 1217 ns		10	Ð	1.25	3.8
tPLH, tPHL = (0.5 ns/pF) CL + 875 ns		15	Ð	0.9	2.9
Propagation Delay, Clock to Q (216 Output)	t					μs
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns	PHL
	tPLH	5.0	Ð	6.0	18
tPHL, tPLH = (0.66 ns/pF) CL + 3467 ns		10	Ð	3.5	10
tPHL, tPLH = (0.5 ns/pF) CL + 2475 ns		15	Ð	2.5	7.5
Clock Pulse Width	tWH(cl)	5.0	900	300	Ð	ns
		10	300	100	Ð
		15	225	85	Ð
Clock Pulse Frequency (50% Duty Cycle)	fcl	5.0	Ð	1.5	0.75	MHz
		10	Ð	4.0	2.0
		15	Ð	6.0	3.0
MR Pulse Width	tWH(R)	5.0	900	300	Ð	ns
		10	300	100	Ð
		15	225	85	Ð
Master Reset Removal Time	trem	5.0	420	210	Ð	ns
		10	200	100	Ð
		15	200	100	Ð

7.The formulas given are for the typical characteristics only at 25_C.

8.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

VDD

VDD

PULSE	RS		PULSE	RS
			GENERATOR
GENERATOR				AR
	AR
	Q/Q SELECT			Q/Q SELECT
	MODE	Q		MODE	Q
	A	CL		A	CL
	B			B
	MR			MR
	VSS			V
				SS
	(Rtc AND Ctc OUTPUTS ARE LEFT OPEN)		20 ns	20 ns

			90%		50%	50%
20 ns	20 ns	RS	10%			tPHL
90%	50%	tPLH
				90%
10%	50%		50%			50%
		Q		10%
	DUTY CYCLE	tTLH				tTHL
Figure 1. Power Dissipation Test Circuit		Figure 2. Switching Time Test Circuit
and Waveform				and Waveforms

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