Motorola MC14526BDW, MC14526BCP, MC14526BCL, MC14522BCL, MC14522BCP Datasheet

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC14522B

Presettable 4-Bit Down Counters MC14526B

The MC14522B BCD counter and the MC14526B binary counter are constructed with MOS P±channel and N±channel enhancement mode devices in a monolithic structure.

These devices are presettable, cascadable, synchronous down counters with a decoded ª0º state output for divide±by±N applications. In single stage applications the ª0º output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide±by±N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock.

These complementary MOS counters can be used in frequency synthesizers, phase±locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Logic Edge±Clocked Design Ð Incremented on Positive Transition of Clock or Negative Transition of Inhibit

•Asynchronous Preset Enable

•Capable of Driving Two Low±power TTL Loads or One Low±power Schottky TTL Load Over the Rated Temperature Range

MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol	Parameter	Value		Unit

VDD	DC Supply Voltage	± 0.5 to +	18.0	V
Vin, Vout	Input or Output Voltage (DC or Transient)	± 0.5 to VDD + 0.5		V
Iin, Iout	Input or Output Current (DC or Transient),	± 10		mA
	per Pin

PD	Power Dissipation, per Package²	500		mW
Tstg	Storage Temperature	± 65 to +	150	_C
TL	Lead Temperature (8±Second Soldering)	260		_C

* Maximum Ratings are those values beyond which damage to the device may occur. ²Temperature Derating:

Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C

Ceramic ªLº Packages: ± 12 mW/C From 100_C To 125_C

FUNCTION TABLE

Inputs

Output

Resulting

Preset

Cascade

Clock

Reset

Inhibit

Enable

Feedback

ª0º

Function

Asynchronous reset*

Asynchronous reset

Asynchronous preset

Decrement inhibited

No change** (inactive edge)

Decrement**

X = Don't Care

NOTES:

*Output ª0º is low when reset goes high only it PE and CF are low.

**Output ª0º is high when reset is low, only if CF is high and count is 0000.

L SUFFIX

CERAMIC

CASE 620

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

ORDERING INFORMATION

MC14XXXBCP	Plastic
MC14XXXBCL	Ceramic
MC14XXXBDW	SOIC

TA = ± 55° to 125°C for all packages.

PIN ASSIGNMENT

Q3	1	16	VDD


P3	2	15	Q2
PE	3	14	P2

INHIBIT	4	13	CF

P0	5	12	ª0º

CLOCK	6	11	P1

Q0	7	10	RESET

VSS	8	9	Q1

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

REV 3 1/94

Motorola, Inc. 1995

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

			VDD	± 55_C			25_C		125_C
Characteristic		Symbol	Vdc	Min	Max	Min	Typ #	Max	Min	Max	Unit

Output Voltage	ª0º Leve	VOL	5.0	Ð	0.05	Ð	0	0.05	Ð	0.05	Vdc
Vin = VDD or 0			10	Ð	0.05	Ð	0	0.05	Ð	0.05
			15	Ð	0.05	Ð	0	0.05	Ð	0.05

	ª1º Leve	VOH	5.0	4.95	Ð	4.95	5.0	Ð	4.95	Ð	Vdc
Vin = 0 or VDD			10	9.95	Ð	9.95	10	Ð	9.95	Ð
			15	14.95	Ð	14.95	15	Ð	14.95	Ð

Input Voltage	ª0º Leve	VIL									Vdc
(VO = 4.5 or 0.5 Vdc)			5.0	Ð	1.5	Ð	2.25	1.5	Ð	1.5
(VO = 9.0 or 1.0 Vdc)			10	Ð	3.0	Ð	4.50	3.0	Ð	3.0
(VO = 13.5 or 1.5 Vdc)			15	Ð	4.0	Ð	6.75	4.0	Ð	4.0
(VO = 0.5 or 4.5 Vdc)	ª1º Leve	VIH	5.0	3.5	Ð	3.5	2.75	Ð	3.5	Ð	Vdc
(VO = 0.5 or 4.5 Vdc)			5.0	3.5	Ð	3.5	2.75	Ð	3.5	Ð
(VO = 1.0 or 9.0 Vdc)			10	7.0	Ð	7.0	5.50	Ð	7.0	Ð
(VO = 1.5 or 13.5 Vdc)			15	11	Ð	11	8.25	Ð	11	Ð
Output Drive Current		IOH									mAdc
(VOH = 2.5 Vdc)	Source		5.0	± 3.0	Ð	± 2.4	± 4.2	Ð	± 1.7	Ð
(VOH = 4.6 Vdc)			5.0	± 0.64	Ð	± 0.51	± 0.88	Ð	± 0.36	Ð
(VOH = 9.5 Vdc)			10	± 1.6	Ð	± 1.3	± 2.25	Ð	± 0.9	Ð
(VOH = 13.5 Vdc)			15	± 4.2	Ð	± 3.4	± 8.8	Ð	± 2.4	Ð
(VOL = 0.4 Vdc)	Sink	IOL	5.0	0.64	Ð	0.51	0.88	Ð	0.36	Ð	mAdc
(VOL = 0.5 Vdc)			10	1.6	Ð	1.3	2.25	Ð	0.9	Ð
(VOL = 1.5 Vdc)			15	4.2	Ð	3.4	8.8	Ð	2.4	Ð
Input Current		Iin	15	Ð	± 0.1	Ð	± 0.00001	± 0.1	Ð	± 1.0	μAdc
Input Capacitance		Cin	Ð	Ð	Ð	Ð	5.0	7.5	Ð	Ð	pF
(Vin = 0)
Quiescent Current		IDD	5.0	Ð	5.0	Ð	0.005	5.0	Ð	150	μAdc
(Per Package)			10	Ð	10	Ð	0.010	10	Ð	300
			15	Ð	20	Ð	0.015	20	Ð	600

Total Supply Current**²		IT	5.0			IT = (1.7 μA/kHz) f + IDD					μAdc
(Dynamic plus Quiescent,			10			IT = (3.4 μA/kHz) f + IDD
Per Package)			15			IT = (5.1 μA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)

#Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

** The formulas given are for the typical characteristics only at 25_C. ²T o calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL ± 50) Vfk

where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.001.

MC14522B MC14526B	MOTOROLA CMOS LOGIC DATA
2

SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

Characteristic	Symbol	VDD	Min	Typ #	Max	Unit
Output Rise and Fall Time	tTLH,					ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns	tTHL	5.0	Ð	100	200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns	(Figures 4, 5)	10	Ð	50	100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns		15	Ð	40	80
Propagation Delay Time (Inhibit Used as Negative	tPLH,					ns
Edge Clock)	tPHL
Clock or Inhibit to Q	(Figures 4, 5, 6)
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns		5.0	Ð	550	1100
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns		10	Ð	225	450
tPLH, tPHL = (0.5 ns/pF) CL + 135 ns		15	Ð	160	320
Clock or Inhibit to ª0º
tPLH, tPHL = (1.7 ns/pF) CL + 155 ns		5.0	Ð	240	480
tPLH, tPHL = (0.66 ns/pF) CL + 87 ns		10	Ð	130	260
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns		15	Ð	100	200
Propagation Delay Time	tPLH,	5.0	Ð	260	520	ns
Pn to Q	tPHL	10	Ð	120	240
	(Figures 4, 7)	15	Ð	100	200

Propagation Delay Time	tPHL	5.0	Ð	250	500	ns
Reset to Q		10	Ð	110	220
	(Figure 8)	15	Ð	80	160

Propagation Delay Time	tPHL,	5.0	Ð	220	440	ns
Preset Enable to ª0º	tPLH	10	Ð	100	200
	(Figures 4, 9)	15	Ð	80	160

Clock or Inhibit Pulse Width	tw	5.0	250	125	Ð	ns
		10	100	50	Ð
	(Figures 5, 6)	15	80	40	Ð

Clock Pulse Frequency (with PE = low)	fmax	5.0	Ð	2.0	1.5	MHz
		10	Ð	5.0	3.0
	(Figures 4, 5, 6)	15	Ð	6.6	4.0

Clock or Inhibit Rise and Fall Time	tr,	5.0	Ð	Ð	15	μs
	tf	10	Ð	Ð	5
	(Figures 5, 6)	15	Ð	Ð	4

Setup Time	tsu	5.0	90	40	Ð	ns
Pn to Preset Enable		10	50	15	Ð
	(Figure 10)	15	40	10	Ð

Hold Time	th	5.0	30	± 15	Ð	ns
Preset Enable to Pn		10	30	± 5	Ð
	(Figure 10)	15	30	0	Ð

Preset Enable Pulse Width	tw	5.0	250	125	Ð	ns
		10	100	50	Ð
	(Figure 10)	15	80	40	Ð

Reset Pulse Width	tw	5.0	350	175	Ð	ns
		10	250	125	Ð
	(Figure 8)	15	200	100	Ð

Reset Removal Time	trem	5.0	10	± 110	Ð	ns
		10	20	± 30	Ð
	(Figure 8)	15	30	± 20	Ð

* The formulas given are for the typical characteristics only at 25_C.

#Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

MOTOROLA CMOS LOGIC DATA	MC14522B MC14526B
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