MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Precision Timer/Driver
MC14415 quad timer/driver is constructed with complementary MOS enhancement mode devices. The output pulse width of each digital timer is a function of the input clock frequency. Once the proper input sequence is detected the output buffer is set (turned on), and after 100 clock pulses are counted, the output buffer is reset (turned off).
The MC14415 was designed specifically for application in high speed line printers to provide the critical timing of the hammer drivers, but may be used in many applications requiring precision pulse widths.
•Four Precision Digital Time Delays
•Schmitt Trigger Clock Conditioning
•NPN Bipolar Output Drivers
•Timing Disable Capability Using Inhibit Output
•Positive or Negative Edge Strobing on the Inputs
•Synchronous Polynomial Counters Used for Delay Counting
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Rating |
Symbol |
Value |
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Unit |
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DC Supply Voltage MC14415FL, FP,DW |
VDD |
± 0.5 to + |
18.0 |
V |
MC14415VL, VP |
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± 0.5 to + 6.0 |
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Input or Output Voltage (DC or Transient) |
Vin, Vout |
± 0.5 to VDD + 0.5 |
V |
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Input Current (DC or Transient), per Pin |
Iin |
± 10 |
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mA |
Output Current (DC or Transient), per Pin |
Iout |
± 20 |
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mA |
Power Dissipation, per Package² |
PD |
500 |
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mW |
Storage Temperature |
Tstg |
± 65 to + |
150 |
_C |
Lead Temperature (8±Second Soldering) |
TL |
260 |
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_C |
* Maximum Ratings are those values beyond which damage to the device may occur. ²Temperature Derating:
Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C Ceramic ªLº Packages: ± 12 mW/C From 100_C To 125_C
BLOCK DIAGRAM
SET A |
3 |
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SET B |
4 |
INPUT |
SET C |
5 |
LOGIC |
SET D |
6 |
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STROBE 2 |
9 |
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STROBE 1 |
7 |
COMMON |
INPUT DISABLE 10 |
LOGIC |
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OUTPUT SET |
2 |
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CLOCK |
1 |
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OUTPUT INHIBIT 15 
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14 |
OUTPUT A |
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DIVIDE±BY± |
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OUTPUT |
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13 |
OUTPUT B |
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100 |
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BUFFERS |
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12 |
OUTPUT C |
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COUNTERS |
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11 OUTPUT D |
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CLOCK |
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VDD = PIN 16 |
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CONDITIONING |
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CIRCUIT |
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VSS = PIN 8 |
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MC14415
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC |
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CASE 648 |
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DW SUFFIX |
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SOIC |
CASE 751G |
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ORDERING INFORMATION |
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MC14415FP (3.0 V±18 V) |
Plastic |
MC14415VP (3.0 V±6.0 V) |
Plastic |
MC14415FL (3.0 V±18 V) |
Ceramic |
MC14415VL (3.0 V±6.0 V) |
Ceramic |
MC14415DW (3.0 V±18 V) |
SOIC |
TA = ± 55° to 125°C for all packages.
PIN ASSIGNMENT
CLOCK |
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1 |
16 |
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VDD |
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SET |
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2 |
15 |
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INH |
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SET A |
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3 |
14 |
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OUT A |
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SET B |
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4 |
13 |
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OUT B |
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SET C |
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5 |
12 |
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OUT C |
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SET D |
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6 |
11 |
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OUT D |
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1 |
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7 |
10 |
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ST |
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DIS |
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VSS |
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8 |
9 |
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ST2 |
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REV 3 1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
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VDD |
± 55_C |
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25_C |
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125_C |
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Characteristic |
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Symbol |
Vdc |
Min |
Max |
Min |
Typ # |
Max |
Min |
Max |
Unit |
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Output Voltage |
ª0º Leve |
VOL |
5.0 |
Ð |
0.01 |
Ð |
0 |
0.01 |
Ð |
0.05 |
Vdc |
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(No Load) |
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10 |
Ð |
0.01 |
Ð |
0 |
0.01 |
Ð |
0.05 |
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15 |
Ð |
Ð |
Ð |
Ð |
Ð |
Ð |
Ð |
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ª1º Leve |
VOH |
5.0 |
Ð |
Ð |
3.0 |
4.14 |
Ð |
Ð |
Ð |
Vdc |
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10 |
Ð |
Ð |
8.0 |
9.09 |
Ð |
Ð |
Ð |
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15 |
Ð |
Ð |
Ð |
14.12 |
Ð |
Ð |
Ð |
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Noise Immunity |
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VNL |
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Vdc |
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( |
Vout v 1.5 Vdc) |
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5.0 |
1.5 |
Ð |
1.5 |
2.25 |
Ð |
1.4 |
Ð |
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( |
Vout v 3.0 Vdc) |
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10 |
3.0 |
Ð |
3.0 |
4.50 |
Ð |
2.9 |
Ð |
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( |
Vout v 4.5 Vdc) |
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15 |
Ð |
Ð |
Ð |
6.75 |
Ð |
Ð |
Ð |
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( |
Vout v 1.5 Vdc) |
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VNH |
5.0 |
1.4 |
Ð |
1.5 |
2.25 |
Ð |
1.5 |
Ð |
Vdc |
( |
Vout v 3.0 Vdc) |
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10 |
2.9 |
Ð |
3.0 |
4.50 |
Ð |
3.0 |
Ð |
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( |
Vout v 4.5 Vdc) |
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15 |
Ð |
Ð |
Ð |
6.75 |
Ð |
Ð |
Ð |
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Output Drive Voltage (NPN Driver) |
VOH |
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Vdc |
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(IOH = 0 mA) |
Source |
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5.0 |
Ð |
Ð |
3.0 |
4.14 |
Ð |
Ð |
Ð |
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(IOH = 5.0 mA) |
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Ð |
Ð |
2.7 |
3.44 |
Ð |
Ð |
Ð |
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(IOH = 10 mA) |
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Ð |
Ð |
2.5 |
3.30 |
Ð |
Ð |
Ð |
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(IOH = 15 mA) |
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Ð |
Ð |
2.2 |
3.08 |
Ð |
Ð |
Ð |
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(IOH = 0 mA) |
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10 |
Ð |
Ð |
8.0 |
9.09 |
Ð |
Ð |
Ð |
Vdc |
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(IOH = 5.0 mA) |
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Ð |
Ð |
7.7 |
8.45 |
Ð |
Ð |
Ð |
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(IOH = 10 mA) |
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Ð |
Ð |
7.5 |
8.30 |
Ð |
Ð |
Ð |
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(IOH = 15 mA) |
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Ð |
Ð |
7.1 |
8.14 |
Ð |
Ð |
Ð |
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(IOH = 0 mA) |
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15 |
Ð |
Ð |
Ð |
14.12 |
Ð |
Ð |
Ð |
Vdc |
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(IOH = 5.0 mA) |
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Ð |
Ð |
Ð |
13.81 |
Ð |
Ð |
Ð |
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(IOH = 10 mA) |
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Ð |
Ð |
Ð |
13.70 |
Ð |
Ð |
Ð |
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(IOH = 15 mA) |
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Ð |
Ð |
Ð |
13.61 |
Ð |
Ð |
Ð |
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Output Drive Current |
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IOL |
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mAdc |
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(VOL = 0.4 Vdc) |
Sink |
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5.0 |
0.23 |
Ð |
0.2 |
0.78 |
Ð |
0.16 |
Ð |
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(VOL = 0.5 Vdc) |
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10 |
0.60 |
Ð |
0.5 |
2.0 |
Ð |
0.40 |
Ð |
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(VOL = 1.5 Vdc) |
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15 |
Ð |
Ð |
Ð |
7.8 |
Ð |
Ð |
Ð |
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Input Leakage Current |
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Iin |
15 |
Ð |
± 0.3 |
Ð |
± 0.00001 |
± 0.3 |
Ð |
± 1.0 |
μAdc |
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Input Capacitance |
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Cin |
Ð |
Ð |
Ð |
Ð |
5.0 |
Ð |
Ð |
Ð |
pF |
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(Vin = 0) |
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Quiescent Dissipation |
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PQ |
5.0 |
Ð |
0.25 |
Ð |
0.00005 |
0.25 |
Ð |
3.5 |
mW |
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10 |
Ð |
1.0 |
Ð |
0.00022 |
1.0 |
Ð |
14 |
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15 |
Ð |
Ð |
Ð |
0.00050 |
Ð |
Ð |
Ð |
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Power Dissipation** |
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PD |
5.0 |
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PD (56 mW/MHz) f + PQ |
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mW |
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(Dynamic plus Quiescent) |
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10 |
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PD (225 mW/MHz) f + PQ |
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(CL = 15 pF) |
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15 |
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PD (510 mW/MHz) f + PQ |
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#Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MOTOROLA CMOS LOGIC DATA |
MC14415 |
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291 |
SWITCHING CHARACTERISTICS* (CL = 15 pF, TA = 25_C)
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VDD |
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Characteristic |
Symbol |
Vdc |
Min |
Typ # |
Max |
Unit |
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Output Rise Time |
tTLH |
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ns |
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tTLH = (2.0 ns/pF) CL + 10 ns |
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5.0 |
Ð |
40 |
85 |
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tTLH = (1.25 ns/pF) CL + 6 ns |
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10 |
Ð |
25 |
60 |
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tTLH = (1.10 ns/pF) CL + 3 ns |
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15 |
Ð |
20 |
Ð |
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Output Fall Time |
tTHL |
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ns |
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tTHL = (1.5 ns/pF) CL + 47 ns |
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5.0 |
Ð |
70 |
150 |
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tTHL = (0.75 ns/pF) CL + 24 ns |
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10 |
Ð |
35 |
80 |
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tTHL = (0.55 ns/pF) CL + 17 ns |
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15 |
Ð |
25 |
Ð |
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Turn±Off Delay Time |
tPLH |
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ns |
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tPLH = (2.7 ns/pF) CL + 560 ns |
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5.0 |
Ð |
600 |
1200 |
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tPLH = (1.2 ns/pF) CL + 282 ns |
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10 |
Ð |
300 |
600 |
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tPLH = (0.91 ns/pF) CL + 286 ns |
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15 |
Ð |
150 |
Ð |
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Turn±On Delay Time |
tPHL |
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ns |
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tPHL = (2.4 ns/pF) CL + 564 ns |
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5.0 |
Ð |
600 |
1200 |
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tPHL = (1.0 ns/pF) CL + 285 ns |
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10 |
Ð |
300 |
600 |
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tPHL = (0.75 ns/pF) CL + 289 ns |
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15 |
Ð |
150 |
Ð |
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Turn±On Delay Time |
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to Output) |
tPHL |
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ns |
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(Inhibit |
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5.0 |
Ð |
300 |
550 |
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10 |
Ð |
225 |
425 |
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15 |
Ð |
110 |
Ð |
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Turn±Off Delay Time |
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to Output) |
tPLH |
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ns |
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(Inhibit |
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5.0 |
Ð |
300 |
550 |
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10 |
Ð |
225 |
425 |
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15 |
Ð |
110 |
Ð |
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Input Pulse Coincidence (Figure 3) |
PCmin |
5.0 |
500 |
450 |
Ð |
ns |
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10 |
450 |
350 |
Ð |
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15 |
Ð |
Ð |
Ð |
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Input Pulse Width (Figure 1) |
tWH |
5.0 |
500 |
450 |
Ð |
ns |
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10 |
450 |
350 |
Ð |
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15 |
Ð |
Ð |
Ð |
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Input Clock Frequency |
fcl |
5.0 |
Ð |
0.7 |
Ð |
MHz |
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10 |
Ð |
1.0 |
Ð |
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15 |
Ð |
1.5 |
Ð |
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Clock Input Rise and Fall Times (Figure 1) |
tTLH, tTHL |
5.0 |
Ð |
Ð |
15 |
μs |
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10 |
Ð |
Ð |
5.0 |
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15 |
Ð |
Ð |
4.0 |
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* The formulas given are for the typical characteristics only at 25_C.
#Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.
20 ns |
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20 ns |
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INPUT |
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50% |
90% |
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VDD |
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10% |
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VSS |
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tPLH |
tWH |
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VOH |
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OUTPUT |
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90% |
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50% |
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10% |
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VOL |
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tTLH |
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tTHL |
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CLOCK |
1 |
2 |
100 |
50% |
VDD |
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VSS |
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tPHL |
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OUTPUT |
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VOH |
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VOL |
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Figure 1. Switching Characteristics Ð Waveform Relationships |
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MC14415 |
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MOTOROLA CMOS LOGIC DATA |
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292 |
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