MC14106B
Hex Schmitt Trigger
The MC14106B hex Schmitt Trigger is constructed with MOS P±channel and N±channel enhancement mode devices in a single monolithic structure. These devices find primary use where low power dissipation and/or high noise immunity is desired. The MC14106B may be used in place of the MC14069UB hex inverter for enhanced noise immunity or to ªsquare upº slowly changing waveforms.
•Increased Hysteresis Voltage Over the MC14584B
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low±power TTL Loads or One Low±power Schottky TTL Load Over the Rated Temperature Range
•Pin±for±Pin Replacement for CD40106B and MM74C14
•Can Be Used to Replace the MC14584B or MC14069UB
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol |
Parameter |
Value |
Unit |
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VDD |
DC Supply Voltage Range |
± 0.5 to +18.0 |
V |
Vin, Vout |
Input or Output Voltage Range |
± 0.5 to VDD + 0.5 |
V |
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(DC or Transient) |
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Iin, Iout |
Input or Output Current |
± 10 |
mA |
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(DC or Transient) per Pin |
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PD |
Power Dissipation, |
500 |
mW |
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per Package (Note 2.) |
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TA |
Ambient Temperature Range |
± 55 to +125 |
°C |
Tstg |
Storage Temperature Range |
± 65 to +150 |
°C |
TL |
Lead Temperature |
260 |
°C |
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(8±Second Soldering) |
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1.Maximum Ratings are those values beyond which damage to the device may occur.
2.Temperature Derating:
Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
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MARKING |
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DIAGRAMS |
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14 |
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PDIP±14 |
MC14106BCP |
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P SUFFIX |
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AWLYYWW |
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CASE 646 |
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1 |
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14 |
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SOIC±14 |
14106B |
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D SUFFIX |
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AWLYWW |
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CASE 751A |
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1 |
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14 |
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TSSOP±14 |
14 |
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DT SUFFIX |
106B |
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CASE 948G |
ALYW |
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1 |
A |
= Assembly Location |
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WL or L = Wafer Lot |
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YY or Y |
= Year |
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WW or W = Work Week |
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ORDERING INFORMATION |
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Device |
Package |
Shipping |
MC14106BCP |
PDIP±14 |
2000/Box |
MC14106BD |
SOIC±14 |
55/Rail |
MC14106BDR2 |
SOIC±14 |
2500/Tape & Reel |
MC14106BDT |
TSSOP±14 |
96/Rail |
MC14106BDTR2 |
TSSOP±14 |
2500/Tape & Reel |
Semiconductor Components Industries, LLC, 2000 |
1 |
Publication Order Number: |
March, 2000 ± Rev. 3 |
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MC14106B/D |
MC14106B
LOGIC DIAGRAM
1 |
2 |
3 |
4 |
5 |
6 |
9 |
8 |
11 |
10 |
13 |
12 |
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VDD = PIN 14 |
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VSS = PIN 7 |
EQUIVALENT CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
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2
MC14106B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
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VDD |
± 55_C |
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25_C |
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125_C |
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Characteristic |
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Symbol |
Vdc |
Min |
Max |
Min |
Typ (3.) |
Max |
Min |
Max |
Unit |
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Output Voltage |
ª0º Level |
VOL |
5.0 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
Vdc |
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Vin = VDD |
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10 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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15 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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ª1º Level |
VOH |
5.0 |
4.95 |
Ð |
4.95 |
5.0 |
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Ð |
4.95 |
Ð |
Vdc |
Vin = 0 |
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10 |
9.95 |
Ð |
9.95 |
10 |
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Ð |
9.95 |
Ð |
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15 |
14.95 |
Ð |
14.95 |
15 |
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Ð |
14.95 |
Ð |
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Hysteresis Voltage |
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V (6.) |
5.0 |
0.3 |
2.0 |
0.3 |
1.1 |
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2.0 |
0.3 |
2.0 |
Vdc |
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H |
10 |
1.2 |
3.4 |
1.2 |
1.7 |
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3.4 |
1.2 |
3.4 |
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15 |
1.6 |
5.0 |
1.6 |
2.1 |
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5.0 |
1.6 |
5.0 |
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Threshold Voltage |
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Positive±Going |
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VT+ |
5.0 |
2.2 |
3.6 |
2.2 |
2.9 |
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3.6 |
2.2 |
3.6 |
Vdc |
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10 |
4.6 |
7.1 |
4.6 |
5.9 |
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7.1 |
4.6 |
7.1 |
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15 |
6.8 |
10.8 |
6.8 |
8.8 |
10.8 |
6.8 |
10.8 |
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Negative±Going |
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VT± |
5.0 |
0.9 |
2.8 |
0.9 |
1.9 |
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2.8 |
0.9 |
2.8 |
Vdc |
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10 |
2.5 |
5.2 |
2.5 |
3.9 |
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5.2 |
2.5 |
5.2 |
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15 |
4.0 |
7.4 |
4.0 |
5.8 |
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7.4 |
4.0 |
7.4 |
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Output Drive Current |
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IOH |
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mAdc |
(VOH = 2.5 Vdc) |
Source |
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5.0 |
± 3.0 |
Ð |
± 2.4 |
± 4.2 |
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Ð |
± 1.7 |
Ð |
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(VOH = 4.6 Vdc) |
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5.0 |
± 0.64 |
Ð |
± 0.51 |
± 0.88 |
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Ð |
± 0.36 |
Ð |
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(VOH = 9.5 Vdc) |
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10 |
± 1.6 |
Ð |
± 1.3 |
± 2.25 |
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Ð |
± 0.9 |
Ð |
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(VOH = 13.5 Vdc) |
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15 |
± 4.2 |
Ð |
± 3.4 |
± 8.8 |
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Ð |
± 2.4 |
Ð |
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(VOL = 0.4 Vdc) |
Sink |
IOL |
5.0 |
0.64 |
Ð |
0.51 |
0.88 |
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Ð |
0.36 |
Ð |
mAdc |
(VOL = 0.5 Vdc) |
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10 |
1.6 |
Ð |
1.3 |
2.25 |
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Ð |
0.9 |
Ð |
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(VOL = 1.5 Vdc) |
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15 |
4.2 |
Ð |
3.4 |
8.8 |
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Ð |
2.4 |
Ð |
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Input Current |
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Iin |
15 |
Ð |
± 0.1 |
Ð |
± 0.00001 |
± 0.1 |
Ð |
± 1.0 |
μAdc |
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Input Capacitance |
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Cin |
Ð |
Ð |
Ð |
Ð |
5.0 |
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7.5 |
Ð |
Ð |
pF |
(Vin = 0) |
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Quiescent Current |
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IDD |
5.0 |
Ð |
0.25 |
Ð |
0.0005 |
0.25 |
Ð |
7.5 |
μAdc |
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(Per Package) |
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10 |
Ð |
0.5 |
Ð |
0.0010 |
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0.5 |
Ð |
15 |
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15 |
Ð |
1.0 |
Ð |
0.0015 |
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1.0 |
Ð |
30 |
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Total Supply Current (4.) (5.) |
I |
5.0 |
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I = (1.8 μA/kHz) f + I |
DD |
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μAdc |
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T |
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T |
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(Dynamic plus Quiescent, |
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10 |
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IT = (3.6 μA/kHz) f + IDD |
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Per Package) |
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15 |
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IT = (5.4 μA/kHz) f + IDD |
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(CL = 50 pF on all outputs, all |
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buffers switching) |
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3.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.
4.The formulas given are for the typical characteristics only at 25_C.
5.To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL ± 50) Vfk
where IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.001. 6. VH = VT+ ± VT± (But maximum variation of VH is specified as less that VT+ max ± VT± min).
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