Motorola MC14082BD, MC14082BCL, MC14082BCP, MC14081BCL, MC14081BCP Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

B-Suffix Series CMOS Gates

The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired.

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•All Outputs Buffered

•Capable of Driving Two Low±power TTL Loads or One Low±power Schottky TTL Load Over the Rated Temperature Range.

•Double Diode Protection on All Inputs Except: Triple Diode Protection on MC14011B and MC14081B

•Pin±for±Pin Replacements for Corresponding CD4000 Series B Suffix Devices (Exceptions: MC14068B and MC14078B)

L SUFFIX	P SUFFIX	D SUFFIX
CERAMIC	PLASTIC	SOIC
CASE 632	CASE 646	CASE 751A

ORDERING INFORMATION

MC14XXXBCP	Plastic
MC14XXXBCL	Ceramic
MC14XXXBD	SOIC

TA = ± 55° to 125°C for all packages.

MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol	Parameter	Value		Unit
VDD	DC Supply Voltage	± 0.5 to +	18.0	V
Vin, Vout	Input or Output Voltage (DC or Transient)	± 0.5 to VDD + 0.5		V
lin, lout	Input or Output Current (DC or Transient),	± 10		mA
	per Pin
PD	Power Dissipation, per Package²	500		mW
Tstg	Storage Temperature	± 65 to +	150	_C
TL	Lead Temperature (8±Second Soldering)	260		_C

* Maximum Ratings are those values beyond which damage to the device may occur. ²Temperature Derating:

Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C Ceramic ªLº Packages: ± 12 mW/C From 100_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and

Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

MC14001B

Quad 2-Input NOR Gate

MC14002B

Dual 4-Input NOR Gate

MC14011B

Quad 2-Input NAND Gate

MC14012B

Dual 4-Input NAND Gate

MC14023B

Triple 3-Input NAND Gate

MC14025B

Triple 3-Input NOR Gate

MC14068B

8-Input NAND Gate

MC14071B

Quad 2-Input OR Gate

MC14072B

Dual 4-Input OR Gate

MC14073B

Triple 3-Input AND Gate

MC14075B

Triple 3-Input OR Gate

MC14078B

8-Input NOR Gate

MC14081B

Quad 2-Input AND Gate

MC14082B

Dual 4-Input AND Gate

REV 3 1/94

Motorola, Inc. 1995

NOR

MC14001B

Quad 2±Input NOR Gate

1

3

2

INPUT2	5
	4

	6
	8	10
	9

12

11

13

MC14025B

Triple 3±Input NOR Gate

	1
	2	9
INPUT3	8
	5
	3
	4	6
	11
	12	10
	13

MC14002B

Dual 4±Input NOR Gate

		2
		3	1
	INPUT	4
		5
	4	9
		10
			13
		11
		12

NC = 6, 8

MC14078B 8±Input NOR Gate

		2
		3
	INPUT	4
		5	13
		9
	8
		10
		11	NC = 6, 8
		12

LOGIC DIAGRAMS

		NAND		OR		AND
		MC14011B		MC14071B		MC14081B
	Quad 2±Input NAND Gate		Quad 2±Input OR Gate		Quad 2±Input AND Gate
	1	3	1	3	1	3
	2		2		2
	5	4	5	4	5	4
	6		6		6
	8	10	8	10	8	10
	9		9		9
	12	11	12	11	12	11
	13		13		13
		MC14023B		MC14075B		MC14073B
	Triple 3±Input NAND Gate		Triple 3±Input OR Gate		Triple 3±Input AND Gate
	1		1		1
	2	9	2	9	2	9
	8		8		8
	3		3		3
	4	6	4	6	4	6
	5		5		5
	11		11		11
	12	10	12	10	12	10
	13		13		13
		MC14012B		MC14072B		MC14082B
	Dual 4±Input NAND Gate		Dual 4±Input OR Gate		Dual 4±Input AND Gate
	2		2		2
	3	1	3	1	3	1
	4		4		4
	5		5		5
	9		9		9
	10	13	10	13	10	13
	11		11		11
	12	NC = 6, 8	12	NC = 6, 8	12	NC = 6, 8
		MC14068B
		8±Input NAND Gate
	2			VDD = PIN 14
	3			VSS = PIN 7
				FOR ALL DEVICES
	4
	5	13
	9
	10
	11	NC = 6, 8
	12

MC14001B	MOTOROLA CMOS LOGIC DATA
8

PIN ASSIGNMENTS

	MC14001B				MC14002B					MC14011B				MC14012B
Quad 2±Input NOR Gate				Dual 4±Input NOR Gate				Quad 2±Input NAND Gate					Dual 4±Input NAND Gate
IN 1A			VDD	OUTA			VDD
	1	14			1	14
								IN 1A		1	14	VDD	OUTA	1	14	VDD
IN 2A	2	13	IN 2D	IN 1A	2	13	OUTB	IN 2A		2	13	IN 2D	IN 1A	2	13	OUTB
OUTA	3	12	IN 1D	IN 2A	3	12	IN 4B	OUTA		3	12	IN 1D	IN 2A	3	12	IN 4B
OUTB	4	11	OUTD	IN 3A	4	11	IN 3B	OUTB		4	11	OUTD	IN 3A	4	11	IN 3B
IN 1B	5	10	OUTC	IN 4A	5	10	IN 2B	IN 1B		5	10	OUTC	IN 4A	5	10	IN 2B
IN 2B	6	9	IN 2C	NC	6	9	IN 1B	IN 2B		6	9	IN 2C	NC	6	9	IN 1B
VSS	7	8	IN 1C	VSS	7	8	NC	VSS		7	8	IN 1C	VSS	7	8	NC

	MC14023B					MC14025B				MC14068B					MC14071B
Triple 3±Input NAND Gate				Triple 3±Input NOR Gate					8±Input NAND Gate				Quad 2±Input OR Gate
IN 1A	1	14	VDD	IN 1A		1	14	VDD	NC	1	14	VDD	IN 1A		1	14	VDD
IN 2A	2	13	IN 3C	IN 2A		2	13	IN 3C	IN 1	2	13	OUT	IN 2A		2	13	IN 2D
IN 1B	3	12	IN 2C	IN 1B		3	12	IN 2C	IN 2	3	12	IN 8	OUTA		3	12	IN 1D
IN 2B	4	11	IN 1C	IN 2B		4	11	IN 1C	IN 3	4	11	IN 7	OUTB		4	11	OUTD
IN 3B	5	10	OUTC	IN 3B		5	10	OUTC	IN 4	5	10	IN 6	IN 1B		5	10	OUTC
OUTB	6	9	OUTA	OUTB		6	9	OUTA	NC	6	9	IN 5	IN 2B		6	9	IN 2C
VSS	7	8	IN 3A	VSS		7	8	IN 3A	VSS	7	8	NC	VSS		7	8	IN 1C

	MC14072B					MC14073B				MC14075B					MC14078B
Dual 4±Input OR Gate				Triple 3±Input AND Gate					Triple 3±Input OR Gate				8±Input NOR Gate
OUTA	1	14	VDD	IN 1A		1	14	VDD	IN 1A	1	14	VDD	NC		1	14	VDD
IN 1A	2	13	OUTB	IN 2A		2	13	IN 3C	IN 2A	2	13	IN 3C	IN 1		2	13	OUT
IN 2A	3	12	IN 4B	IN 1B		3	12	IN 2C	IN 1B	3	12	IN 2C	IN 2		3	12	IN 8
IN 3A	4	11	IN 3B	IN 2B		4	11	IN 1C	IN 2B	4	11	IN 1C	IN 3		4	11	IN 7
IN 4A	5	10	IN 2B	IN 3B		5	10	OUTC	IN 3B	5	10	OUTC	IN 4		5	10	IN 6
NC	6	9	IN 1B	OUTB		6	9	OUTA	OUTB	6	9	OUTA	NC		6	9	IN 5
VSS	7	8	NC	VSS		7	8	IN 3A	VSS	7	8	IN 3A	VSS		7	8	NC

		MC14081B				MC14082B
Quad 2±Input AND Gate					Dual 4±Input AND Gate
IN 1A		1	14	VDD	OUTA	1	14	VDD
IN 2A		2	13	IN 2D	IN 1A	2	13	OUTB
OUTA		3	12	IN 1D	IN 2A	3	12	IN 4B
OUTB		4	11	OUTD	IN 3A	4	11	IN 3B
IN 1B		5	10	OUTC	IN 4A	5	10	IN 2B
IN 2B		6	9	IN 2C	NC	6	9	IN 1B
VSS		7	8	IN 1C	VSS	7	8	NC	NC = NO CONNECTION

MOTOROLA CMOS LOGIC DATA	MC14001B
	9

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

			VDD	± 55_C			25_C		125_C
Characteristic		Symbol	Vdc	Min	Max	Min	Typ #	Max	Min	Max	Unit
Output Voltage	ª0º Level	VOL	5.0	Ð	0.05	Ð	0	0.05	Ð	0.05	Vdc
Vin = VDD or 0			10	Ð	0.05	Ð	0	0.05	Ð	0.05
			15	Ð	0.05	Ð	0	0.05	Ð	0.05
	ª1º Level	VOH	5.0	4.95	Ð	4.95	5.0	Ð	4.95	Ð	Vdc
Vin = 0 or VDD			10	9.95	Ð	9.95	10	Ð	9.95	Ð
			15	14.95	Ð	14.95	15	Ð	14.95	Ð
Input Voltage	ª0º Level	VIL									Vdc
(VO = 4.5 or 0.5 Vdc)			5.0	Ð	1.5	Ð	2.25	1.5	Ð	1.5
(VO = 9.0 or 1.0 Vdc)			10	Ð	3.0	Ð	4.50	3.0	Ð	3.0
(VO = 13.5 or 1.5 Vdc)			15	Ð	4.0	Ð	6.75	4.0	Ð	4.0
(VO = 0.5 or 4.5 Vdc)	ª1º Level	VIH	5.0	3.5	Ð	3.5	2.75	Ð	3.5	Ð	Vdc
(VO = 1.0 or 9.0 Vdc)			10	7.0	Ð	7.0	5.50	Ð	7.0	Ð
(VO = 1.5 or 13.5 Vdc)			15	11	Ð	11	8.25	Ð	11	Ð
Output Drive Current		IOH									mAdc
(VOH = 2.5 Vdc)	Source		5.0	± 3.0	Ð	± 2.4	± 4.2	Ð	± 1.7	Ð
(VOH = 4.6 Vdc)			5.0	± 0.64	Ð	± 0.51	± 0.88	Ð	± 0.36	Ð
(VOH = 9.5 Vdc)			10	± 1.6	Ð	± 1.3	± 2.25	Ð	± 0.9	Ð
(VOH = 13.5 Vdc)			15	± 4.2	Ð	± 3.4	± 8.8	Ð	± 2.4	Ð
(VOL = 0.4 Vdc)	Sink	IOL	5.0	0.64	Ð	0.51	0.88	Ð	0.36	Ð	mAdc
(VOL = 0.5 Vdc)			10	1.6	Ð	1.3	2.25	Ð	0.9	Ð
(VOL = 1.5 Vdc)			15	4.2	Ð	3.4	8.8	Ð	2.4	Ð
Input Current		Iin	15	Ð	± 0.1	Ð	± 0.00001	± 0.1	Ð	± 1.0	μAdc
Input Capacitance		Cin	Ð	Ð	Ð	Ð	5.0	7.5	Ð	Ð	pF
(Vin = 0)
Quiescent Current		IDD	5.0	Ð	0.25	Ð	0.0005	0.25	Ð	7.5	μAdc
(Per Package)			10	Ð	0.5	Ð	0.0010	0.5	Ð	15
			15	Ð	1.0	Ð	0.0015	1.0	Ð	30
Total Supply Current**²		IT	5.0			IT = (0.3 μA/kHz) f + IDD/N					μAdc
(Dynamic plus Quiescent,			10			IT = (0.6 μA/kHz) f + IDD/N
Per Gate, CL = 50 pF)			15			IT = (0.9 μA/kHz) f + IDD/N

#Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

** The formulas given are for the typical characteristics only at 25_C.

²T o calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL ± 50) Vfk

where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package.

MC14001B	MOTOROLA CMOS LOGIC DATA
10