MOTOROLA MC14099BDWR2, MC14099BF, MC14099BFEL, MC14099BFL1, MC14099BCP Datasheet

MC14099B

8-Bit Addressable Latches

The MC14099B is an 8±bit addressable latch. Data is entered in serial form when the appropriate latch is addressed (via address pins A0, A1, A2) and write disable is in the low state. For the MC14099B the input is a unidirectional write only port.

The data is presented in parallel at the output of the eight latches independently of the state of Write Disable, Write/Read or Chip Enable.

A Master Reset capability is available on both parts.

•Serial Data Input

•Parallel Output

•Master Reset

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low±power TTL Loads or One Low±Power Schottky TTL Load over the Rated Temperature Range

•MC14099B pin for pin compatible with CD4099B

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol	Parameter	Value	Unit
VDD	DC Supply Voltage Range	± 0.5 to +18.0	V
Vin, Vout	Input or Output Voltage Range	± 0.5 to VDD + 0.5	V
	(DC or Transient)
Iin, Iout	Input or Output Current	± 10	mA
	(DC or Transient) per Pin
PD	Power Dissipation,	500	mW
	per Package (Note 3.)
TA	Ambient Temperature Range	± 55 to +125	°C
Tstg	Storage Temperature Range	± 65 to +150	°C
TL	Lead Temperature	260	°C
	(8±Second Soldering)

2.Maximum Ratings are those values beyond which damage to the device may occur.

3.Temperature Derating:

Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

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		MARKING
		DIAGRAMS
		16
	PDIP±16	MC14099BCP
	P SUFFIX
		AWLYYWW
	CASE 648
		1
		16
	SOIC±16	14099B
	DW SUFFIX
	CASE 751G	AWLYYWW
		1
		16
	SOEIAJ±16	MC14099B
	F SUFFIX
		AWLYWW
	CASE 966
		1
A	= Assembly Location
WL or L = Wafer Lot
YY or Y	= Year
WW or W = Work Week
ORDERING INFORMATION
Device	Package	Shipping
MC14099BCP	PDIP±16	2000/Box
MC14099BDW	SOIC±16	2350/Box
MC14099BDWR2	SOIC±16	1000/Tape & Reel
MC14099BF	SOEIAJ±16	See Note 1.
MC14099BFEL	SOEIAJ±16	See Note 1.

1.For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 3		MC14099B/D

MC14099B

PIN ASSIGNMENT

Q7		1	16	VDD			MC14099B
RESET		2	15	Q6
DATA		3	14	Q5	WRITE DISABLE			4		9	Q0
					DATA			3		10	Q1
WRITE										11
		4	13	Q4		5					Q2
DISABLE					A0			8	8	12	Q3
						6				13
					A1		DECODER		LATCHES		Q4
A0		5	12	Q3		7				14
											Q5
					A2					15	Q6
								2		1
A1		6	11	Q2	RESET		VDD = 16				Q7
A2		7	10	Q1			VSS = 8
VSS		8	9	Q0

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD

± 55_C

25_C

125_C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ (4.)

Max

Min

Max

Unit

Output Voltage

ª0º Level

VOL

5.0

Ð

0.05

Ð

0

0.05

Ð

0.05

Vdc

Vin = VDD or 0

10

Ð

0.05

Ð

0

0.05

Ð

0.05

15

Ð

0.05

Ð

0

0.05

Ð

0.05

ª1º Level

VOH

5.0

4.95

Ð

4.95

5.0

Ð

4.95

Ð

Vdc

Vin = 0 or VDD

10

9.95

Ð

9.95

10

Ð

9.95

Ð

15

14.95

Ð

14.95

15

Ð

14.95

Ð

Input Voltage

ª0º Level

VIL

Vdc

(VO = 4.5 or 0.5 Vdc)

5.0

Ð

1.5

Ð

2.25

1.5

Ð

1.5

(VO = 9.0 or 1.0 Vdc)

10

Ð

3.0

Ð

4.50

3.0

Ð

3.0

(VO = 13.5 or 1.5 Vdc)

15

Ð

4.0

Ð

6.75

4.0

Ð

4.0

(VO = 0.5 or 4.5 Vdc)

ª1º Level

VIH

5.0

3.5

Ð

3.5

2.75

Ð

3.5

Ð

Vdc

(VO = 1.0 or 9.0 Vdc)

10

7.0

Ð

7.0

5.50

Ð

7.0

Ð

(VO = 1.5 or 13.5 Vdc)

15

11

Ð

11

8.25

Ð

11

Ð

Output Drive Current

IOH

mAdc

(VOH = 2.5 Vdc)

Source

5.0

± 3.0

Ð

± 2.4

± 4.2

Ð

± 1.7

Ð

(VOH = 4.6 Vdc)

5.0

± 0.64

Ð

± 0.51

± 0.88

Ð

± 0.36

Ð

(VOH = 9.5 Vdc)

10

± 1.6

Ð

± 1.3

± 2.25

Ð

± 0.9

Ð

(VOH = 13.5 Vdc)

15

± 4.2

Ð

± 3.4

± 8.8

Ð

± 2.4

Ð

(VOL = 0.4 Vdc)

Sink

IOL

5.0

0.64

Ð

0.51

0.88

Ð

0.36

Ð

mAdc

(VOL = 0.5 Vdc)

10

1.6

Ð

1.3

2.25

Ð

0.9

Ð

(VOL = 1.5 Vdc)

15

4.2

Ð

3.4

8.8

Ð

2.4

Ð

Input Current

Iin

15

Ð

± 0.1

Ð

± 0.00001

± 0.1

Ð

± 1.0

μAdc

Input Capacitance (Vin = 0)

Cin

Ð

Ð

Ð

Ð

5.0

7.5

Ð

Ð

pF

Input Capacitance

Cin

Ð

Ð

Ð

Ð

15

22.5

Ð

Ð

pF

MC14599B Ð Data (pin 3)

(Vin = 0)

Quiescent Current

IDD

5.0

Ð

5.0

Ð

0.005

5.0

Ð

150

μAdc

(Per Package)

10

Ð

10

Ð

0.010

10

Ð

300

15

Ð

20

Ð

0.015

20

Ð

600

Total Supply Current (5.) (6.)

I

5.0

I = (1.5 μA/kHz) f + I

DD

μAdc

T

T

(Dynamic plus Quiescent,

10

IT = (3.0 μA/kHz) f + IDD

Per Package)

15

IT = (4.5 μA/kHz) f + IDD

(CL = 50 pF on all outputs, all

buffers switching)

4.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

5.The formulas given are for the typical characteristics only at 25_C.

6.To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL ± 50) Vfk

where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.004.

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MC14099B

SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)

				VDD		Typ (8.)
Characteristic			Symbol	Vdc	Min		Max	Unit
Output Rise and Fall Time			tTLH,					ns
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns			tTHL	5.0	Ð	100	200
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns				10	Ð	50	100
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns				15	Ð	40	80
Propagation Delay Time			tPHL,					ns
Data to Output Q			tPLH	5.0	Ð	200	400
				10	Ð	75	150
				15	Ð	50	100
Write Disable to Output Q				5.0	Ð	200	400	ns
				10	Ð	80	160
				15	Ð	60	120
Reset to Output Q				5.0	Ð	175	350	ns
				10	Ð	80	160
				15	Ð	65	130
CE to Output Q (MC14599B only)				5.0	Ð	225	450	ns
				10	Ð	100	200
				15	Ð	75	150
Propagation Delay Time, MC14599B only			tPHL,					ns
			tPLH
Chip Enable, Write/Read		to Data		5.0	Ð	200	400
				10	Ð	80	160
				15	Ð	65	130
Address to Data				5.0	Ð	200	400	ns
				10	Ð	90	180
				15	Ð	75	150
Pulse Widths			tw(H)					ns
Reset			tw(L)	5.0	150	75	Ð
				10	75	40	Ð
				15	50	25	Ð
Write Disable				5.0	320	160	Ð	ns
				10	160	80	Ð
				15	120	60	Ð
Set Up Time			tsu					ns
Data to Write Disable				5.0	100	50	Ð
				10	50	25	Ð
				15	35	20	Ð
Hold Time			th					ns
Write Disable to Data				5.0	150	75	Ð
				10	75	40	Ð
				15	50	25	Ð
Set Up Time			tsu	5.0	100	45	Ð	ns
Address to Write Disable				10	80	30	Ð
				15	40	10	Ð
Removal Time			trem	5.0	0	± 80	Ð	ns
Write Disable to Address				10	0	± 40	Ð
				15	0	± 40	Ð

7.The formulas given are for the typical characteristics only at 25_C.

8.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

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