MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Full Adder
The MC14008B 4±bit full adder is constructed with MOS P±channel and N±channel enhancement mode devices in a single monolithic structure. This device consists of four full adders with fast internal look±ahead carry output. It is useful in binary addition and other arithmetic applications. The fast parallel carry output bit allows high±speed operation when used with other adders in a system.
•Look±Ahead Carry Output
•Diode Protection on All Inputs
•All Outputs Buffered
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low±power TTL Loads or One Low±power Schottky TTL Load Over the Rated Temperature Range
•Pin±for±Pin Replacement for CD4008B
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol |
Parameter |
Value |
|
Unit |
|
|
|
|
|
VDD |
DC Supply Voltage |
± 0.5 to + |
18.0 |
V |
Vin, Vout |
Input or Output Voltage (DC or Transient) |
± 0.5 to VDD + 0.5 |
V |
|
lin, lout |
Input or Output Current (DC or Transient), |
± 10 |
|
mA |
|
per Pin |
|
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PD |
Power Dissipation, per Package² |
500 |
|
mW |
Tstg |
Storage Temperature |
± 65 to + |
150 |
_C |
TL |
Lead Temperature (8±Second Soldering) |
260 |
|
_C |
* Maximum Ratings are those values beyond which damage to the device may occur. ²Temperature Derating:
Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C
Ceramic ªLº Packages: ± 12 mW/C From 100_C To 125_C
BLOCK DIAGRAM
MC14008B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP |
Plastic |
MC14XXXBCL |
Ceramic |
MC14XXXBD |
SOIC |
TA = ± 55° to 125°C for all packages.
TRUTH TABLE
(One Stage)
Cin |
B |
A |
Cout |
S |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
|
|
|
|
|
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
|
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|
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|
HIGH±SPEED |
|
14 |
Cout |
PIN ASSIGNMENT |
||||
|
PARALLEL CARRY |
|
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B4 |
15 |
ADDER |
|
|
A4 |
1 |
16 |
VDD |
|
13 |
S4 |
B3 |
2 |
15 |
B4 |
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A4 |
1 |
4 |
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A3 |
3 |
14 |
Cout |
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C4 |
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B2 |
4 |
13 |
S4 |
||
B3 |
2 |
ADDER |
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12 |
S3 |
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A2 |
5 |
12 |
S3 |
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A3 |
3 |
3 |
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C3 |
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B1 |
6 |
11 |
S2 |
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B2 |
4 |
ADDER |
11 |
S2 |
A1 |
7 |
10 |
S1 |
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A2 |
5 |
2 |
VSS |
8 |
9 |
Cin |
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C2 |
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B1 |
6 |
ADDER |
10 |
S1 |
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A1 |
7 |
1 |
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Cin |
9 |
|
VDD = PIN 16 |
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VSS = PIN 8 |
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REV 3 1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
|
|
|
VDD |
± 55_C |
|
25_C |
|
125_C |
|
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Characteristic |
|
Symbol |
Vdc |
Min |
Max |
Min |
Typ # |
Max |
Min |
Max |
Unit |
|
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Output Voltage |
ª0º Leve |
VOL |
5.0 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
Vdc |
Vin = VDD or 0 |
|
|
10 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
|
|
|
|
15 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
|
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Vin = 0 or VDD |
ª1º Leve |
VOH |
5.0 |
4.95 |
Ð |
4.95 |
5.0 |
Ð |
4.95 |
Ð |
Vdc |
|
|
|
10 |
9.95 |
Ð |
9.95 |
10 |
Ð |
9.95 |
Ð |
|
|
|
|
15 |
14.95 |
Ð |
14.95 |
15 |
Ð |
14.95 |
Ð |
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Input Voltage |
ª0º Leve |
VIL |
|
|
|
|
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Vdc |
(VO = 4.5 or 0.5 Vdc) |
|
|
5.0 |
Ð |
1.5 |
Ð |
2.25 |
1.5 |
Ð |
1.5 |
|
(VO = 9.0 or 1.0 Vdc) |
|
|
10 |
Ð |
3.0 |
Ð |
4.50 |
3.0 |
Ð |
3.0 |
|
(VO = 13.5 or 1.5 Vdc) |
|
|
15 |
Ð |
4.0 |
Ð |
6.75 |
4.0 |
Ð |
4.0 |
|
(VO = 0.5 or 4.5 Vdc) |
ª1º Leve |
VIH |
5.0 |
3.5 |
Ð |
3.5 |
2.75 |
Ð |
3.5 |
Ð |
Vdc |
(VO = 1.0 or 9.0 Vdc) |
|
|
10 |
7.0 |
Ð |
7.0 |
5.50 |
Ð |
7.0 |
Ð |
|
(VO = 1.5 or 13.5 Vdc) |
|
|
15 |
11 |
Ð |
11 |
8.25 |
Ð |
11 |
Ð |
|
Output Drive Current |
|
IOH |
|
|
|
|
|
|
|
|
mAdc |
(VOH = 2.5 Vdc) |
Source |
|
5.0 |
± 3.0 |
Ð |
± 2.4 |
± 4.2 |
Ð |
± 1.7 |
Ð |
|
(VOH = 4.6 Vdc) |
|
|
5.0 |
± 0.64 |
Ð |
± 0.51 |
± 0.88 |
Ð |
± 0.36 |
Ð |
|
(VOH = 9.5 Vdc) |
|
|
10 |
± 1.6 |
Ð |
± 1.3 |
± 2.25 |
Ð |
± 0.9 |
Ð |
|
(VOH = 13.5 Vdc) |
|
|
15 |
± 4.2 |
Ð |
± 3.4 |
± 8.8 |
Ð |
± 2.4 |
Ð |
|
(VOL = 0.4 Vdc) |
Sink |
IOL |
5.0 |
0.64 |
Ð |
0.51 |
0.88 |
Ð |
0.36 |
Ð |
mAdc |
(VOL = 0.5 Vdc) |
|
|
10 |
1.6 |
Ð |
1.3 |
2.25 |
Ð |
0.9 |
Ð |
|
(VOL = 1.5 Vdc) |
|
|
15 |
4.2 |
Ð |
3.4 |
8.8 |
Ð |
2.4 |
Ð |
|
Input Current |
|
Iin |
15 |
Ð |
± 0.1 |
Ð |
± 0.00001 |
± 0.1 |
Ð |
± 1.0 |
μAdc |
Input Capacitance |
|
Cin |
Ð |
Ð |
Ð |
Ð |
5.0 |
7.5 |
Ð |
Ð |
pF |
(Vin = 0) |
|
|
|
|
|
|
|
|
|
|
|
Quiescent Current |
|
IDD |
5.0 |
Ð |
5.0 |
Ð |
0.005 |
5.0 |
Ð |
150 |
μAdc |
(Per Package) |
|
|
10 |
Ð |
10 |
Ð |
0.010 |
10 |
Ð |
300 |
|
|
|
|
15 |
Ð |
20 |
Ð |
0.015 |
20 |
Ð |
600 |
|
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Total Supply Current**² |
|
IT |
5.0 |
|
|
IT = (1.7 μA/kHz) f + IDD |
|
|
μAdc |
||
(Dynamic plus Quiescent, |
|
10 |
|
|
IT = (3.4 μA/kHz) f + IDD |
|
|
|
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Per Package) |
|
|
15 |
|
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IT = (5.0 μA/kHz) f + IDD |
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(CL = 50 pF on all outputs, all |
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buffers switching) |
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#Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C.
²T o calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL ± 50) Vfk
where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.005.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14008B |
MOTOROLA CMOS LOGIC DATA |
38 |
|
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
|
|
|
VDD |
|
|
|
|
Characteristic |
|
Symbol |
Vdc |
Min |
Typ # |
Max |
Unit |
|
|
|
|
|
|
|
|
Output Rise and Fall Time |
|
tTLH, |
|
Ð |
|
|
ns |
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns |
tTHL |
5.0 |
100 |
200 |
|
||
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns |
|
10 |
Ð |
50 |
100 |
|
|
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns |
|
15 |
Ð |
40 |
80 |
|
|
Propagation Delay Time |
|
tPLH, tPHL |
|
|
|
|
ns |
Sum in to Sum Out |
|
|
|
|
|
|
|
tPLH, tPHL = (1.7 ns/pF) CL + |
315 ns |
|
5.0 |
Ð |
400 |
800 |
|
tPLH, tPHL = (0.66 ns/pF) CL + 127 ns |
|
10 |
Ð |
160 |
320 |
|
|
tPLH, tPHL = (0.5 ns/pF) CL + |
90 ns |
|
15 |
Ð |
115 |
230 |
|
Sum In to Carry Out |
|
|
|
|
|
|
|
tPLH, tPHL = (1.7 ns/pF) CL + |
220 ns |
|
5.0 |
Ð |
305 |
610 |
|
tPLH, tPHL = (0.66 ns/pF) CL + 112 ns |
|
10 |
Ð |
145 |
290 |
|
|
tPLH, tPHL = (0.5 ns/pF) CL + |
85 ns |
|
15 |
Ð |
110 |
220 |
|
Carry In to Sum Out |
|
|
|
|
|
|
|
tPLH, tPHL = (1.7 ns/pF) CL + |
290 ns |
|
5.0 |
Ð |
375 |
750 |
|
tPLH, tPHL = (0.66 ns/pF) CL + 122 ns |
|
10 |
Ð |
155 |
310 |
|
|
tPLH, tPHL = (0.5 ns/pF) CL + |
90 ns |
|
15 |
Ð |
115 |
230 |
|
Carry In to Carry Out |
|
|
|
Ð |
|
|
|
tPLH, tPHL = (1.7 ns/pF) CL + |
85 ns |
|
5.0 |
170 |
340 |
|
|
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns |
|
10 |
Ð |
75 |
150 |
|
|
|
Ð |
|
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tPLH, tPHL = (0.5 ns/pF) CL + |
30 ns |
|
15 |
55 |
110 |
|
|
|
|
|
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.
VDD = ± VGS |
Vout |
VDD = VGS |
Vout |
|||
|
16 |
|
|
16 |
|
|
B4 |
S4 |
|
B4 |
S4 |
|
|
A4 |
|
|
A4 |
|
|
|
B3 |
S3 |
|
B3 |
S3 |
|
|
A3 |
|
|
A3 |
|
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B2 |
S2 |
|
B2 |
S2 |
|
|
A2 |
|
|
A2 |
|
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|
B1 |
S1 |
IOH |
B1 |
S1 |
IOL |
|
A1 |
|
|
A1 |
|
|
|
Cin |
Cout |
EXTERNAL |
Cin |
Cout |
EXTERNAL |
|
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|
|||
8 |
VSS |
POWER |
8 |
VSS |
POWER |
|
SUPPLY |
SUPPLY |
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Figure 1. Typical Source Current |
Figure 2. Typical Sink Current |
Characteristics Test Circuit |
Characteristics Test Circuit |
MOTOROLA CMOS LOGIC DATA |
MC14008B |
|
39 |