Motorola MC14050BD, MC14050BCL, MC14050BCP, MC14049BD, MC14049BCL Datasheet
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting Hex Buffer are constructed with MOS P±Channel and N±Channel enhancement mode devices in a single monolithic structure. These complementary MOS devices find primary use where low power dissipation and/or high noise immunity is desired. These devices provide logic level conversion using only one supply voltage, VDD.
The input±signal high level (VIH) can exceed the VDD supply voltage for logic level conversions. Two TTL/DTL loads can be driven when the devices are used as a CMOS±to±TTL/DTL converter (VDD = 5.0 V, VOL v 0.4 V,
IOL ≥ 3.2 mA).
Note that pins 13 and 16 are not connected internally on these devices; consequently connections to these terminals will not affect circuit operation.
•High Source and Sink Currents
•High±to±Low Level Converter
•Supply Voltage Range = 3.0 V to 18 V
•VIN can exceed VDD
•Meets JEDEC B Specifications
•Improved ESD Protection On All Inputs
MAXIMUM RATINGS1 (Voltages Referenced to VSS)
Characteristic |
Symbol |
Value |
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Unit |
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DC Supply Voltage |
VDD |
± 0.5 to + |
18.0 |
Vdc |
Input Voltage (DC or Transient) |
VIN |
± 0.5 to + |
18.0 |
Vdc |
Output Voltage (DC or Transient) |
Vout |
± 0.5 to VDD + 0.5 |
Vdc |
|
Input Current (DC or Transient), per Pin |
Iin |
± 10 |
|
mA |
Output Current (DC or Transient), per Pin |
Iout |
+ 45 |
|
mA |
Power Dissipation, per Package2 |
PD |
825 |
|
mW |
(Plastic/Ceramic) |
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(SOIC) |
|
740 |
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Storage Temperature |
Tstg |
± 65 to + |
150 |
_C |
Lead Temperature (8 ± Second Soldering) |
TL |
260 |
|
_C |
1Maximum Ratings are those values beyond which damage to the device may occur. 2Temperature Derating: See Figure 3.
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MC14049B |
LOGIC DIAGRAM |
MC14050B |
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3 |
2 |
3 |
2 |
MC14049B
MC14050B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP |
Plastic |
MC14XXXBCL |
Ceramic |
MC14XXXBD |
SOIC |
TA = ± 55° to 125°C for all packages.
PIN ASSIGNMENT
VDD |
|
1 |
16 |
NC |
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OUTA |
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2 |
15 |
OUTF |
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INA |
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3 |
14 |
INF |
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OUTB |
|
4 |
13 |
NC |
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INB |
|
5 |
12 |
OUTE |
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OUTC |
|
6 |
11 |
INE |
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INC |
|
7 |
10 |
OUTD |
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VSS |
|
8 |
9 |
IND |
|
5 |
4 |
5 |
4 |
7 |
6 |
7 |
6 |
9 |
10 |
9 |
10 |
11 |
12 |
11 |
12 |
14 |
15 |
14 |
15 |
NC = PIN 13, 16 VSS = PIN 8
NC = PIN 13, 16 VSS = PIN 8
REV 3 1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
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VDD |
± 55_C |
|
+ 25_C |
|
+ 125_C |
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Characteristic |
|
Symbol |
Vdc |
Min |
Max |
Min |
Typ1 |
Max |
Min |
Max |
Unit |
|
Output Voltage |
ª0º Leve |
VOL |
5.0 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
Vdc |
|
Vin = VDD |
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10 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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15 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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ª1º Leve |
VOH |
5.0 |
4.95 |
Ð |
4.95 |
5.0 |
Ð |
4.95 |
Ð |
Vdc |
|
Vin = 0 |
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|
10 |
9.95 |
Ð |
9.95 |
10 |
Ð |
9.95 |
Ð |
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15 |
14.95 |
Ð |
14.95 |
15 |
Ð |
14.95 |
Ð |
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Input Voltage |
ª0º Leve |
VIL |
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Vdc |
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(VO = 4.5 Vdc) |
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|
5.0 |
Ð |
1.5 |
Ð |
2.25 |
1.5 |
Ð |
1.5 |
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(VO = 9.0 Vdc) |
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10 |
Ð |
3.0 |
Ð |
4.50 |
3.0 |
Ð |
3.0 |
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(VO = 13.5 Vdc) |
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15 |
Ð |
4.0 |
Ð |
6.75 |
4.0 |
Ð |
4.0 |
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(VO = 0.5 Vdc) |
ª1º Leve |
VIH |
5.0 |
3.5 |
Ð |
3.5 |
2.75 |
Ð |
3.5 |
Ð |
Vdc |
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(VO = 1.0 Vdc) |
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10 |
7.0 |
Ð |
7.0 |
5.50 |
Ð |
7.0 |
Ð |
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(VO = 1.5 Vdc) |
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15 |
11 |
Ð |
11 |
8.25 |
Ð |
11 |
Ð |
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Output Drive Current |
|
IOH |
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|
mAdc |
|
(VOH = 2.5 Vdc) |
Source |
|
5.0 |
± 1.6 |
Ð |
± 1.25 |
± 2.5 |
Ð |
± 1.0 |
Ð |
|
|
(VOH = 9.5 Vdc) |
|
|
10 |
± 1.6 |
Ð |
± 1.30 |
± 2.6 |
Ð |
± 1.0 |
Ð |
|
|
(VOH = 13.5 Vdc) |
|
|
15 |
± 4.7 |
Ð |
± 3.75 |
± 10 |
Ð |
± 3.0 |
Ð |
|
|
(VOL = 0.4 Vdc) |
Sink |
IOL |
5.0 |
3.75 |
Ð |
3.2 |
6.0 |
Ð |
2.6 |
Ð |
mAdc |
|
(VOL = 0.5 Vdc) |
|
|
10 |
10 |
Ð |
8.0 |
16 |
Ð |
6.6 |
Ð |
|
|
(VOL = 1.5 Vdc) |
|
|
15 |
30 |
Ð |
24 |
40 |
|
19 |
Ð |
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|
Input Current |
|
Iin |
15 |
Ð |
± 0.1 |
Ð |
±0.00001 |
± 0.1 |
Ð |
± 1.0 |
μAdc |
|
Input Capacitance (Vin = 0) |
Cin |
Ð |
Ð |
Ð |
Ð |
10 |
20 |
Ð |
Ð |
pF |
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Quiescent Current (Per Package) |
IDD |
5.0 |
Ð |
1.0 |
Ð |
0.002 |
1.0 |
Ð |
30 |
μAdc |
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10 |
Ð |
2.0 |
Ð |
0.004 |
2.0 |
Ð |
60 |
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15 |
Ð |
4.0 |
Ð |
0.006 |
4.0 |
Ð |
120 |
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Total Supply Current 2,3 |
|
I |
5.0 |
|
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I = (1.8 μA/kHz) f + I |
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μAdc |
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T |
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T |
|
DD |
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(Dynamic plus Quiescent, |
|
10 |
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IT = (3.5 μA/kHz) f + IDD |
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per package) |
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|
15 |
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IT = (5.3 μA/kHz) f + IDD |
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(CL = 50 pF on all outputs, all |
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buffers switching |
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1Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.
2The formulas given are for the typical characteristics only at + 25_C
3To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL ± 50) Vfk
Where: IT is in μA (per Package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency and k = 0.002.
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the VSS pin only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum rated voltages to this high-impedance circuit. For proper operation, the ranges VSS v Vin v 18 V and VSS v Vout v VDD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14049B MC14050B |
MOTOROLA CMOS LOGIC DATA |
2 |
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