MOTOROLA MC14503BFR1, MC14503BD, MC14503BF, MC14503BFEL, MC14503BFL2 Datasheet

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MOTOROLA MC14503BFR1, MC14503BD, MC14503BF, MC14503BFEL, MC14503BFL2 Datasheet

MC14503B

Hex Non-Inverting 3-State

Buffer

The MC14503B is a hex non±inverting buffer with 3±state outputs, and a high current source and sink capability. The 3±state outputs make it useful in common bussing applications. Two disable controls are provided. A high level on the Disable A input causes the outputs of buffers 1 through 4 to go into a high impedance state and a high level on the Disable B input causes the outputs of buffers 5 and 6 to go into a high impedance state.

3±State Outputs

TTL Compatible Ð Will Drive One TTL Load Over Full Temperature Range

Supply Voltage Range = 3.0 Vdc to 18 Vdc

Two Disable Controls for Added Versatility

Pin for Pin Replacement for MM80C97 and 340097

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol

Parameter

Value

Unit

 

 

 

 

VDD

DC Supply Voltage Range

± 0.5 to +18.0

V

Vin, Vout

Input or Output Voltage Range

± 0.5 to VDD + 0.5

V

 

(DC or Transient)

 

 

 

 

 

 

Iin

Input Current

± 10

mA

 

(DC or Transient) per Pin

 

 

 

 

 

 

Iout

Output Current

± 25

mA

 

(DC or Transient) per Pin

 

 

 

 

 

 

PD

Power Dissipation,

500

mW

 

per Package (Note 3.)

 

 

 

 

 

 

TA

Ambient Temperature Range

± 55 to +125

°C

Tstg

Storage Temperature Range

± 65 to +150

°C

TL

Lead Temperature

260

°C

 

(8±Second Soldering)

 

 

 

 

 

 

2.Maximum Ratings are those values beyond which damage to the device may occur.

3.Temperature Derating:

Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

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MARKING

 

 

DIAGRAMS

 

 

16

 

PDIP±16

MC14503BCP

 

P SUFFIX

 

AWLYYWW

 

CASE 648

 

 

 

 

1

 

 

16

 

SOIC±16

14503B

 

D SUFFIX

 

AWLYWW

 

CASE 751B

 

 

 

 

1

 

 

16

 

SOEIAJ±16

MC14503B

 

F SUFFIX

 

AWLYWW

 

CASE 966

 

 

 

 

1

A

= Assembly Location

WL or L = Wafer Lot

 

YY or Y

= Year

 

WW or W = Work Week

ORDERING INFORMATION

Device

Package

Shipping

MC14503BCP

PDIP±16

2000/Box

MC14503BD

SOIC±16

48/Rail

MC14503BDR2

SOIC±16

2500/Tape & Reel

MC14503BF

SOEIAJ±16

See Note 1.

MC14503BFEL

SOEIAJ±16

See Note 1.

1.For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

Semiconductor Components Industries, LLC, 2000

1

Publication Order Number:

March, 2000 ± Rev. 3

 

MC14503B/D

MC14503B

PIN ASSIGNMENT

DIS A

 

1

16

VDD

 

 

IN 1

 

2

15

DIS B

 

OUT 1

 

3

14

IN 6

 

IN 2

 

4

13

OUT 6

 

OUT 2

 

5

12

IN 5

 

IN 3

 

6

11

OUT 5

 

OUT 3

 

7

10

IN 4

 

VSS

 

8

9

OUT 4

 

 

 

TRUTH TABLE

 

 

LOGIC DIAGRAM

 

 

 

Appropriate

 

DISABLE B

15

 

 

 

Disable

 

 

 

 

 

 

 

 

Inn

Input

Outn

IN 5

12

11

OUT 5

0

0

0

 

 

 

14

13

 

1

0

1

IN 6

OUT 6

 

 

X

1

High

IN 1

2

3

OUT 1

 

Impedance

 

 

 

 

 

 

 

X = Don't Care

 

IN 2

4

5

OUT 2

 

 

 

 

 

 

IN 3

6

7

OUT 3

 

 

 

 

 

 

 

 

IN 4

10

9

OUT 4

 

 

 

 

 

 

 

 

DISABLE A

1

 

 

 

 

 

 

 

 

VDD = PIN 16

VSS = PIN 8

CIRCUIT DIAGRAM

ONE OF TWO/FOUR BUFFERS

VDD

* INn

OUTn

 

* DISABLE

INPUT

VSS

TO OTHER BUFFERS

* Diode protection on all inputs (not shown)

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MC14503B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

 

 

 

VDD

± 55_C

 

25_C

 

 

125_C

 

 

 

 

 

 

 

 

 

 

 

 

 

Characteristic

 

Symbol

Vdc

Min

Max

Min

Typ (4.)

Max

Min

Max

Unit

Output Voltage

ª0º Level

VOL

5.0

Ð

0.05

Ð

0

0.05

Ð

0.05

Vdc

Vin = 0

 

 

10

Ð

0.05

Ð

0

0.05

Ð

0.05

 

 

 

 

15

Ð

0.05

Ð

0

0.05

Ð

0.05

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ª1º Level

VOH

5.0

4.95

Ð

4.95

5.0

 

Ð

4.95

Ð

Vdc

Vin = VDD

 

 

10

9.95

Ð

9.95

10

 

Ð

9.95

Ð

 

 

 

 

15

14.95

Ð

14.95

15

 

Ð

14.95

Ð

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Voltage

ª0º Level

VIL

 

 

 

 

 

 

 

 

 

Vdc

(VO = 3.6 or 1.4 Vdc)

 

 

5.0

Ð

1.5

Ð

2.25

 

1.5

Ð

1.5

 

(VO = 7.2 or 2.8 Vdc)

 

 

10

Ð

3.0

Ð

4.50

 

3.0

Ð

3.0

 

(VO = 11.5 or 3.5 Vdc)

 

 

15

Ð

4.0

Ð

6.75

 

4.0

Ð

4.0

 

(VO = 1.4 or 3.6 Vdc)

ª1º Level

VIH

5.0

3.5

Ð

3.5

2.75

 

Ð

3.5

Ð

Vdc

 

 

 

 

(VO = 2.8 or 7.2 Vdc)

 

 

10

7.0

Ð

7.0

5.50

 

Ð

7.0

Ð

 

(VO = 3.5 or 11.5 Vdc)

 

 

15

11

Ð

11

8.25

 

Ð

11

Ð

 

Output Drive Current

 

IOH

 

 

 

 

 

 

 

 

 

mAdc

(VOH = 2.5 Vdc)

Source

 

4.5

± 4.3

Ð

± 3.6

± 5.0

 

Ð

± 2.5

Ð

 

(VOH = 2.5 Vdc)

 

 

5.0

± 5.8

Ð

± 4.8

± 6.1

 

Ð

± 3.0

Ð

 

(VOH = 4.6 Vdc)

 

 

5.0

± 1.2

Ð

± 1.02

± 1.4

 

Ð

± 0.7

Ð

 

(VOH = 9.5 Vdc)

 

 

10

± 3.1

Ð

± 2.6

± 3.7

 

Ð

± 1.8

Ð

 

(VOH = 13.5 Vdc)

 

 

15

± 8.2

Ð

± 6.8

± 14.1

 

Ð

± 4.8

Ð

 

(VOL = 0.4 Vdc)

Sink

IOL

4.5

2.2

Ð

1.8

2.1

 

Ð

1.2

Ð

mAdc

(VOL = 0.4 Vdc)

 

 

5.0

2.6

Ð

2.1

2.3

 

Ð

1.3

Ð

 

(VOL = 0.5 Vdc)

 

 

10

6.5

Ð

5.5

6.2

 

Ð

3.8

Ð

 

(VOL = 1.5 Vdc)

 

 

15

19.2

Ð

16.1

25

 

Ð

11.2

Ð

 

Input Current

 

Iin

15

Ð

± 0.1

Ð

± 0.00001

± 0.1

Ð

± 1.0

μAdc

Input Capacitance

 

Cin

Ð

Ð

Ð

Ð

5.0

 

7.5

Ð

Ð

pF

(Vin = 0)

 

 

 

 

 

 

 

 

 

 

 

 

Quiescent Current

 

IQ

5.0

Ð

1.0

Ð

0.002

 

1.0

Ð

30

μAdc

(Per Package)

 

 

10

Ð

2.0

Ð

0.004

 

2.0

Ð

60

 

 

 

 

15

Ð

4.0

Ð

0.006

 

4.0

Ð

120

 

 

 

 

 

 

 

 

 

 

 

 

 

Total Supply Current (5.) (6.)

I

5.0

 

 

I = (2.5 μA/kHz) f + I

DD

 

 

μAdc

 

 

T

 

 

 

T

 

 

 

 

 

(Dynamic plus Quiescent,

 

10

 

 

IT = (6.0 μA/kHz) f + IDD

 

 

 

Per Package)

 

 

15

 

 

IT = (10 μA/kHz) f + IDD

 

 

 

(CL = 50 pF on all outputs)

 

 

 

 

 

 

 

 

 

 

 

(All outputs switching,

 

 

 

 

 

 

 

 

 

 

 

 

50% Duty Cycle)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Three±State Output Leakage

ITL

15

Ð

± 0.1

Ð

± 0.0001

± 0.1

Ð

± 3.0

μAdc

Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

5.The formulas given are for the typical characteristics only at 25_C.

6.To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL ± 50) Vfk

where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.006.

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