MOTOROLA MC14050BFEL, MC14050BFL1, MC14050BFL2, MC14050BFR1, MC14050BFR2 Datasheet

MC14049B, MC14050B

Hex Buffer

The MC14049B Hex Inverter/Buffer and MC14050B Noninverting Hex Buffer are constructed with MOS P±Channel and N±Channel enhancement mode devices in a single monolithic structure. These complementary MOS devices find primary use where low power dissipation and/or high noise immunity is desired. These devices provide logic level conversion using only one supply voltage, VDD.

The input±signal high level (VIH) can exceed the VDD supply voltage for logic level conversions. Two TTL/DTL loads can be driven when the devices are used as a CMOS±to±TTL/DTL converter (VDD

=5.0 V, VOL v 0.4 V, IOL ≥ 3.2 mA).

Note that pins 13 and 16 are not connected internally on these

devices; consequently connections to these terminals will not affect circuit operation.

•High Source and Sink Currents

•High±to±Low Level Converter

•Supply Voltage Range = 3.0 V to 18 V

•VIN can exceed VDD

•Meets JEDEC B Specifications

•Improved ESD Protection On All Inputs

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol	Parameter	Value	Unit
VDD	DC Supply Voltage Range	± 0.5 to +18.0	V
Vin	Input Voltage Range	± 0.5 to +18.0	V
	(DC or Transient)
Vout	Output Voltage Range	± 0.5 to VDD + 0.5	V
	(DC or Transient)
Iin	Input Current	± 10	mA
	(DC or Transient) per Pin
Iout	Output Current	± 45	mA
	(DC or Transient) per Pin
PD	Power Dissipation,		mW
	per Package (Note 3.)
	(Plastic)	825
	(SOIC)	740
TA	Ambient Temperature Range	± 55 to +125	°C
Tstg	Storage Temperature Range	± 65 to +150	°C
TL	Lead Temperature	260	°C
	(8±Second Soldering)

2.Maximum Ratings are those values beyond which damage to the device may occur.

3.Temperature Derating: See Figure 3.

This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the VSS pin only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum rated voltages to this high±impedance circuit. For proper operation, the

ranges VSS ≤ Vin ≤ 18 V and VSS ≤ Vout ≤ VDD are recommended.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

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			MARKING
		DIAGRAMS
		16
	PDIP±16	MC140XXBCP
	P SUFFIX
			AWLYYWW
	CASE 648
		1
		16
	SOIC±16		140XXB
	D SUFFIX
			AWLYWW
	CASE 751B
		1	16
	TSSOP±16		14
	DT SUFFIX		0XXB
	CASE 948F		ALYW
		16	1
	SOEIAJ±16		MC140XXB
	F SUFFIX
			AWLYWW
	CASE 966
		1
XX	= Specific Device Code
A	= Assembly Location
WL or L = Wafer Lot
YY or Y	= Year
WW or W = Work Week
ORDERING INFORMATION
Device	Package		Shipping
MC14049BCP	PDIP±16		2000/Box
MC14049BD	SOIC±16		2400/Box
MC14049BDR2	SOIC±16	2500/Tape & Reel
MC14049BF	SOEIAJ±16		See Note 1.
MC14050BCP	PDIP±16		2000/Box
MC14050BD	SOIC±16		2400/Box
MC14050BDR2	SOIC±16	2500/Tape & Reel
MC14050BDTEL	TSSOP±16	2000/Tape & Reel
MC14050BF	SOEIAJ±16		See Note 1.
MC14050BFEL	SOEIAJ±16		See Note 1.

1.For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 3		MC14049B/D

MC14049B, MC14050B

PIN ASSIGNMENT

VDD		1	16	NC
OUTA		2	15	OUTF
INA		3	14	INF
OUTB		4	13	NC
INB		5	12	OUTE
OUTC		6	11	INE
INC		7	10	OUTD
VSS		8	9	IND

	MC14049B	LOGIC DIAGRAM	MC14050B
3	2	3	2
5	4	5	4
7	6	7	6
9	10	9	10
11	12	11	12
14	15	14	15

NC = PIN 13, 16

VSS = PIN 8

VDD = PIN 1

NC = PIN 13, 16

VSS = PIN 8

VDD = PIN 1

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MC14049B, MC14050B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD

± 55_C

+ 25_C

+ 125_C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ (4.)

Max

Min

Max

Unit

Output Voltage

ª0º Level

VOL

5.0

Ð

0.05

Ð

0

0.05

Ð

0.05

Vdc

Vin = VDD

10

Ð

0.05

Ð

0

0.05

Ð

0.05

15

Ð

0.05

Ð

0

0.05

Ð

0.05

ª1º Level

VOH

5.0

4.95

Ð

4.95

5.0

Ð

4.95

Ð

Vdc

Vin = 0

10

9.95

Ð

9.95

10

Ð

9.95

Ð

15

14.95

Ð

14.95

15

Ð

14.95

Ð

Input Voltage

ª0º Level

VIL

Vdc

(VO = 4.5 Vdc)

5.0

Ð

1.5

Ð

2.25

1.5

Ð

1.5

(VO = 9.0 Vdc)

10

Ð

3.0

Ð

4.50

3.0

Ð

3.0

(VO = 13.5 Vdc)

15

Ð

4.0

Ð

6.75

4.0

Ð

4.0

(VO = 0.5 Vdc)

ª1º Level

VIH

5.0

3.5

Ð

3.5

2.75

Ð

3.5

Ð

Vdc

(VO = 1.0 Vdc)

10

7.0

Ð

7.0

5.50

Ð

7.0

Ð

(VO = 1.5 Vdc)

15

11

Ð

11

8.25

Ð

11

Ð

Output Drive Current

IOH

mAdc

(VOH = 2.5 Vdc)

Source

5.0

± 1.6

Ð

± 1.25

± 2.5

Ð

± 1.0

Ð

(VOH = 9.5 Vdc)

10

± 1.6

Ð

± 1.30

± 2.6

Ð

± 1.0

Ð

(VOH = 13.5 Vdc)

15

± 4.7

Ð

± 3.75

± 10

Ð

± 3.0

Ð

(VOL = 0.4 Vdc)

Sink

IOL

5.0

3.75

Ð

3.2

6.0

Ð

2.6

Ð

mAdc

(VOL = 0.5 Vdc)

10

10

Ð

8.0

16

Ð

6.6

Ð

(VOL = 1.5 Vdc)

15

30

Ð

24

40

19

Ð

Input Current

Iin

15

Ð

± 0.1

Ð

±0.00001

± 0.1

Ð

± 1.0

μAdc

Input Capacitance (Vin = 0)

Cin

Ð

Ð

Ð

Ð

10

20

Ð

Ð

pF

Quiescent Current (Per Package)

IDD

5.0

Ð

1.0

Ð

0.002

1.0

Ð

30

μAdc

10

Ð

2.0

Ð

0.004

2.0

Ð

60

15

Ð

4.0

Ð

0.006

4.0

Ð

120

Total Supply Current (5.) (6.)

I

5.0

I = (1.8 μA/kHz) f + I

DD

μAdc

T

T

(Dynamic plus Quiescent,

10

IT = (3.5 μA/kHz) f + IDD

per package)

15

IT = (5.3 μA/kHz) f + IDD

(CL = 50 pF on all outputs, all

buffers switching

4.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

5.The formulas given are for the typical characteristics only at + 25_C

6.To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL ± 50) Vfk

Where: IT is in μA (per Package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency and k = 0.002.

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