MOTOROLA MC14021BFEL, MC14021BFL1, MC14021BFL2, MC14021BFR1, MC14021BFR2 Datasheet

MC14014B, MC14021B

8-Bit Static Shift Register

The MC14014B and MC14021B 8±bit static shift registers are constructed with MOS P±channel and N±channel enhancement mode devices in a single monolithic structure. These shift registers find primary use in parallel±to±serial data conversion, synchronous and asynchronous parallel input, serial output data queueing; and other general purpose register applications requiring low power and/or high noise immunity.

•Synchronous Parallel Input/Serial Output (MC14014B)

•Asynchronous Parallel Input/Serial Output (MC14021B)

•Synchronous Serial Input/Serial Output

•Full Static Operation

•ªQº Outputs from Sixth, Seventh, and Eighth Stages

•Double Diode Input Protection

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low±power TTL Loads or One Low±power Schottky TTL Load Over the Rated Temperature Range

•MC14014B Pin±for±Pin Replacement for CD4014B

•MC14021B Pin±for±Pin Replacement for CD4021B

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol	Parameter	Value	Unit
VDD	DC Supply Voltage Range	± 0.5 to +18.0	V
Vin, Vout	Input or Output Voltage Range	± 0.5 to VDD + 0.5	V
	(DC or Transient)
Iin, Iout	Input or Output Current	± 10	mA
	(DC or Transient) per Pin
PD	Power Dissipation,	500	mW
	per Package (Note 3.)
TA	Ambient Temperature Range	± 55 to +125	°C
Tstg	Storage Temperature Range	± 65 to +150	°C
TL	Lead Temperature	260	°C
	(8±Second Soldering)

2.Maximum Ratings are those values beyond which damage to the device may occur.

3.Temperature Derating:

Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

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		MARKING
		DIAGRAMS
		16
	PDIP±16	MC140XXBCP
	P SUFFIX
		AWLYYWW
	CASE 648
		1
		16
	SOIC±16	140XXB
	D SUFFIX
		AWLYWW
	CASE 751B
		1
		16
	SOEIAJ±16	MC140XXB
	F SUFFIX
		AWLYWW
	CASE 966
		1
XX	= Specific Device Code
A	= Assembly Location
WL or L = Wafer Lot
YY or Y	= Year
WW or W = Work Week
ORDERING INFORMATION
Device	Package	Shipping
MC14014BCP	PDIP±16	2000/Box
MC14014BD	SOIC±16	48/Rail
MC14014BDR2	SOIC±16	2500/Tape & Reel
MC14014BF	SOEIAJ±16	See Note 1.
MC14014BFEL	SOEIAJ±16	See Note 1.
MC14021BCP	PDIP±16	2000/Box
MC14021BD	SOIC±16	48/Rail
MC14021BDR2	SOIC±16	2500/Tape & Reel
MC14021BF	SOEIAJ±16	See Note 1.
MC14021BFEL	SOEIAJ±16	See Note 1.

1.For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 3		MC14014B/D

9

P/S

11

DS

10

CLOCK

MC14014B, MC14021B

TRUTH TABLE

SERIAL OPERATION:

			Q6	Q7	Q8
t	Clock DS	P/S	t=n+6	t=n+7	t=n+8
n	0	0	0	?	?
n+1	1	0	1	0	?
n+2	0	0	0	1	0
n+3	1	0	1	0	1
	X	0	Q6	Q7	Q8

PARALLEL OPERATION:

Clock
MC14014B	MC14021B	DS	P/S	Pn	*Qn
	X	X	1	0	0
	X	X	1	1	1

*Q6, Q7, & Q8 are available externally X = Don't Care

PIN ASSIGNMENT

P8		1	16	VDD
Q6		2	15	P7
Q8		3	14	P6
P4		4	13	P5
P3		5	12	Q7
P2		6	11	DS
P1		7	10	C
VSS		8	9	P/S

LOGIC DIAGRAM

P1	P2	P3	P6	P7	P8
7	6	5	14	15	1

D

Q

D

Q

D

Q

D Q

D Q

D

C

C

C

C

Q

C

Q

C

Q

VDD = PIN 16

P4

= PIN 4

2

12

3

VSS = PIN 8

P5

= PIN 13

Q6

Q7

Q8

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MC14014B, MC14021B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

			VDD	± 55_C			25_C		125_C
Characteristic		Symbol	Vdc	Min	Max	Min	Typ (4.)	Max	Min	Max	Unit
Output Voltage	ª0º Level	VOL	5.0	Ð	0.05	Ð	0	0.05	Ð	0.05	Vdc
Vin = VDD or 0			10	Ð	0.05	Ð	0	0.05	Ð	0.05
			15	Ð	0.05	Ð	0	0.05	Ð	0.05
Vin = 0 or VDD	ª1º Level	VOH	5.0	4.95	Ð	4.95	5.0	Ð	4.95	Ð	Vdc
			10	9.95	Ð	9.95	10	Ð	9.95	Ð
			15	14.95	Ð	14.95	15	Ð	14.95	Ð
Input Voltage	ª0º Level	VIL									Vdc
(VO = 4.5 or 0.5 Vdc)			5.0	Ð	1.5	Ð	2.25	1.5	Ð	1.5
(VO = 9.0 or 1.0 Vdc)			10	Ð	3.0	Ð	4.50	3.0	Ð	3.0
(VO = 13.5 or 1.5 Vdc)			15	Ð	4.0	Ð	6.75	4.0	Ð	4.0
(VO = 0.5 or 4.5 Vdc)	ª1º Level	VIH	5.0	3.5	Ð	3.5	2.75	Ð	3.5	Ð	Vdc
(VO = 1.0 or 9.0 Vdc)			10	7.0	Ð	7.0	5.50	Ð	7.0	Ð
(VO = 1.5 or 13.5 Vdc)			15	11	Ð	11	8.25	Ð	11	Ð
Output Drive Current		IOH									mAdc
(VOH = 2.5 Vdc)	Source		5.0	± 3.0	Ð	± 2.4	± 4.2	Ð	± 1.7	Ð
(VOH = 4.6 Vdc)			5.0	± 0.64	Ð	± 0.51	± 0.88	Ð	± 0.36	Ð
(VOH = 9.5 Vdc)			10	± 1.6	Ð	± 1.3	± 2.25	Ð	± 0.9	Ð
(VOH = 13.5 Vdc)			15	± 4.2	Ð	± 3.4	± 8.8	Ð	± 2.4	Ð
(VOL = 0.4 Vdc)	Sink	IOL	5.0	0.64	Ð	0.51	0.88	Ð	0.36	Ð	mAdc
(VOL = 0.5 Vdc)			10	1.6	Ð	1.3	2.25	Ð	0.9	Ð
(VOL = 1.5 Vdc)			15	4.2	Ð	3.4	8.8	Ð	2.4	Ð
Input Current		Iin	15	Ð	± 0.1	Ð	± 0.00001	± 0.1	Ð	± 1.0	μAdc
Input Capacitance		Cin	Ð	Ð	Ð	Ð	5.0	7.5	Ð	Ð	pF
(Vin = 0)
Quiescent Current		IDD	5.0	Ð	5.0	Ð	0.005	5.0	Ð	150	μAdc
(Per Package)			10	Ð	10	Ð	0.010	10	Ð	300
			15	Ð	15	Ð	0.015	15	Ð	600
Total Supply Current (5.) (6.)		I	5.0			I = (0.75 μA/kHz) f + I					μAdc
		T				T		DD
(Dynamic plus Quiescent,			10			IT = (1.50 μA/kHz) f + IDD
Per Package)			15			IT = (2.25 μA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)

4.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

5.The formulas given are for the typical characteristics only at 25_C.

6.To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL ± 50) Vfk

where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.0015.

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