Motorola MC12202M, MC12202D, MC12202DT Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Serial Input PLL Frequency

Synthesizer

The MC12202 is a 1.1GHz Bipolar monolithic serial input phase locked loop (PLL) synthesizer with pulse±swallow function. It is designed to provide the high frequency local oscillator signal of an RF transceiver in handheld communication applications.

Motorola's advanced Bipolar MOSAIC V technology is utilized for low power operation at a minimum supply voltage of 2.7V. The device is designed for operation over 2.7 to 5.5V supply range for input frequencies up to 1.1GHz with a typical current drain of 6.5mA. The low power consumption makes the MC12202 ideal for handheld battery operated applications such as cellular or cordless telephones, wireless LAN or personal communication services. A dual modulus prescaler is integrated to provide either a 64/65 or 128/129 divide ratio.

For additional applications information, two InterActiveApNote documents containing software (based on a Microsoft Excel spreadsheet) and an Application Note are available. Please order DK305/D and DK306/D from the Motorola Literature Distribution Center.

•Low Power Supply Current of 5.8mA Typical for ICC and 0.7mA Typical for IP

•Supply Voltage of 2.7 to 5.5V

•Dual Modulus Prescaler With Selectable Divide Ratios of 64/65 or 128/129

•On±Chip Reference Oscillator/Buffer

•Programmable Reference Divider Consisting of a Binary 14±Bit Programmable Reference Counter

•Programmable Divider Consisting of a Binary 7±Bit Swallow Counter and an 11±Bit Programmable Counter

•Phase/Frequency Detector With Phase Conversion Function

•Balanced Charge Pump Outputs

•Dual Internal Charge Pumps for Bypassing the First Stage of the Loop Filter to Decrease Lock Time

•Outputs for External Charge Pump

•Operating Temperature Range of ±40°C to +85°C

•Space Efficient Plastic Surface Mount SOIC or TSSOP Packages

•The MC12202 Is Pin Compatible With the Fujitsu MB1502 or MB1511

MAXIMUM RATINGS*

MC12202

MECL PLL COMPONENTS

Serial Input PLL

Frequency Synthesizer

16

1

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B±05

16

1

M SUFFIX

PLASTIC SOIC PACKAGE

CASE 966±01

20

1

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E±02

Symbol	Parameter	Value	Unit
VCC	Power Supply Voltage, Pin 4 (Pin 5 in 20±lead package)	±0.5 to +6.0	VDC
VP	Power Supply Voltage, Pin 3 (Pin 4 in 20±lead package)	VCC to +6.0	VDC
Tstg	Storage Temperature Range	±65 to +150	°C

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

MOSAIC V, Mfax and InterActiveApNote are trademarks of Motorola, Inc.

1/97

Motorola, Inc. 1997

1

REV 4

MC12202

	φR		φP		fOUT		BISW		FC		LE	DATA			CLK
	16		15		14		13		12		11		10		9

Pinout: 16±Lead Packages (Top View)

			1		2		3		4		5		6		7		8
		OSCin OSCout					VP		VCC		Do		GND		LD		fIN
	φR		NC		φP		fOUT		BISW		FC		LE		DATA		NC		CLK
	20		19		18		17		16		15		14		13		12		11

Pinout: 20±Lead Package (Top View)

	1		2		3		4		5		6		7		8		9		10
OSCin			NC	OSCout			VP		VCC		Do		GND		LD		NC		fIN

PIN NAMES

	Pin		I/O	Function	16±Lead Pkg	20±Lead Pkg
					Pin No.	Pin No.
	OSCin		I	Oscillator input. A crystal is connected between OSCin and OSCout. An external	1	1
				source can be AC coupled into this input
	OSCout		O	Oscillator output. Pin should be left open if external source is used	2	3
	VP		Ð	Power supply for charge pumps (VP should be greater than or equal to VCC) VP	3	4
				provides power to the Do, BISW and φP outputs
	VCC		Ð	Power supply voltage input. Bypass capacitors should be placed as close as	4	5
				possible to this pin and be connected directly to the ground plane.
	Do		O	Internal charge pump output. Do remains on at all times	5	6
	GND		Ð	Ground	6	7
	LD		O	Lock detect, phase comparator output	7	8
	fIN		I	Prescaler input. The VCO signal is AC±coupled into this pin	8	10
	CLK		I	Clock input. Rising edge of the clock shifts data into the shift registers	9	11
	DATA		I	Binary serial data input	10	13
	LE		I	Load enable input (with internal pull up resistor). When LE is HIGH or OPEN, data	11	14
				stored in the shift register is transferred into the appropriate latch (depending on
				the level of control bit). Also, when LE is HIGH or OPEN, the output of the second
				internal charge pump is connected to the BISW pin
	FC		I	Phase control select (with internal pull up resistor). When FC is LOW, the	12	15
				characteristics of the phase comparator and charge pump are reversed. FC also
				selects fp or fr on the fOUT pin
	BISW		O	Analog switch output. When LE is HIGH or OPEN (ªanalog switch is ONº) the	13	16
				output of the second charge pump is connected to the BISW pin. When LE is LOW,
				BISW is high impedance
	fOUT		O	Phase comparator input signal. When FC is HIGH, fOUT=fr, programmable	14	17
				reference divider output; when FC is LOW, fOUT=fp, programmable divider output
	φP		O	Output for external charge pump. Standard CMOS output level	15	18
	φR		O	Output for external charge pump. Standard CMOS output level	16	20
	NC		Ð	No connect	Ð	2, 9, 12, 19
	MOTOROLA			2		HIPERCOMM
					BR1334 Ð Rev 4

							MC12202
			15±BIT SHIFT REGISTER
				15
			15±BIT LATCH
			14		1
			PROGRAMMABLE REFERENCE DIVIDER
OSCin	CRYSTAL		14±BIT REFERENCE COUNTER		fr		LD
OSCout	OSCILLATOR
							φP
					PHASE/FREQUENCY
					DETECTOR		φR
					CHARGE		Do
FC						PUMP 1
LE		LE
	CONTROL
DATA	BIT	DATA			CHARGE
			18±BIT SHIFT REGISTER				BISW
						PUMP 2
			7	11
CLK					DIVIDER		fOUT
			7±BIT	11±BIT LATCH	OUTPUT MUX
			LATCH
			7	11
		PRESCALER	PROGRAMMABLE DIVIDER
	fIN
		64/65 or 128/129
			7±BIT	11±BIT	fp
			SWALLOW	PROGRAMMABLE
			A±COUNTER	N±COUNTER

CONTROL LOGIC

Figure 1. MC12202 Block Diagram

HIPERCOMM

3

MOTOROLA

BR1334 Ð Rev 4

MC12202

DATA ENTRY FORMAT

The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14±bit programmable reference divider plus the prescaler setting bit, and the 18±bit programmable divider. A rising edge of the clock shifts one bit of serial data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred into the latch when load enable pin is HIGH or OPEN.

Control bit:	ªHº = data is transferred into 15±bit latch of programmable reference divider
	ªLº = data is transferred into 18±bit latch of programmable divider

WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will affect the VCO.

PROGRAMMABLE REFERENCE DIVIDER

16±bit serial data format for the programmable reference counter, ªR±counterº, and prescaler select bit (SW) is shown below. If the control bit is HIGH, data is transferred from the 15±bit shift register into the 15±bit latch which specifies the R divide ratio (8 to 16383) and the prescaler divide ratio (SW=0 for 128/129, SW=1 for 64/65). An R divide ratio less than 8 is prohibited.

For Control bit (C) = HIGH:

SETTING BIT FOR PRESCALER DIVIDE RATIO (FIRST BIT)

CONTROL BIT (LAST BIT)

MSB

LSB

S

R

R

R

R

R

R

R

R

R

R

R

R

R

R

C

W

14

13

12

11

10

9

8

7

6

5

4

3

2

1

SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE

REFERENCE COUNTER (R±COUNTER)

DIVIDE RATIO OF PROGRAMMABLE REFERENCE (R) COUNTER

Divide	R	R	R	R	R	R	R	R	R	R	R	R	R	R
Ratio R	14	13	12	11	10	9	8	7	6	5	4	3	2	1
8	0	0	0	0	0	0	0	0	0	0	1	0	0	0
9	0	0	0	0	0	0	0	0	0	0	1	0	0	1
•	•	•	•	•	•	•	•	•	•	•	•	•	•	•
16383	1	1	1	1	1	1	1	1	1	1	1	1	1	1

PRESCALER SELECT BIT

Prescaler Divide Ratio P	SW
128/129	0
64/65	1

MOTOROLA	4	HIPERCOMM
		BR1334 Ð Rev 4