Motorola MC14051BCL, MC14053BCL, MC14051BCP, MC14051BD, MC14052BCL Datasheet
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers are digitally±controlled analog switches. The MC14051B effectively implements an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a Triple SPDT. All three devices feature low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved.
•Triple Diode Protection on Control Inputs
•Switch Function is Break Before Make
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Analog Voltage Range (VDD ± VEE) = 3.0 to 18 V Note: VEE must be v VSS
•Linearized Transfer Characteristics
•Low±noise ± 12 nV/√ Cycle, f ≥ 1.0 kHz Typical
•Pin±for±Pin Replacement for CD4051, CD4052, and CD4053
•For 4PDT Switch, See MC14551B
•For Lower RON, Use the HC4051, HC4052, or HC4053 High±Speed CMOS Devices
MAXIMUM RATINGS*
Symbol |
Parameter |
Value |
Unit |
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VDD |
DC Supply Voltage (Referenced to VEE, |
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VSS ≥ VEE) |
± 0.5 to + 18.0 |
V |
Vin, Vout |
Input or Output Voltage (DC or Transient) |
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(Referenced to VSS for Control Inputs and |
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VEE for Switch I/O) |
± 0.5 to VDD + 0.5 |
V |
Iin |
Input Current (DC or Transient), |
± 10 |
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per Control Pin |
mA |
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Isw |
Switch Through Current |
± 25 |
mA |
PD |
Power Dissipation. per Package² |
500 |
mW |
Tstg |
Storage Temperature |
± 65 to + 150 |
_C |
TL |
Lead Temperature (8±Second Soldering) |
260 |
_C |
* Maximum Ratings are those values beyond which damage to the device may occur. ²Temperature Derating:ªP and D/DWº Packages: ± 7.0 mW/ C From 65_C To 125_C
Ceramic ªLº Packages: ± 12 mW/C From 100_C To 125_C
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MC14051B |
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MC14052B |
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8±Channel Analog |
Dual 4±Channel Analog |
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Multiplexer/Demultiplexer |
Multiplexer/Demultiplexer |
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6 |
INHIBIT |
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6 |
INHIBIT |
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CONTROLS |
11 |
A |
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CONTROLS |
10 |
A |
X |
13 |
10 |
B |
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9 |
B |
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9 |
C |
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12 |
X0 |
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13 |
X0 |
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14 |
X1 |
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COMMONS |
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14 |
X1 |
X |
3 |
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15 |
X2 |
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OUT/IN |
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15 |
X2 |
SWITCHES |
11 |
X3 |
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COMMON |
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SWITCHES |
12 |
X3 |
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IN/OUT |
1 |
Y0 |
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OUT/IN |
Y |
3 |
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IN/OUT |
1 |
X4 |
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5 |
Y1 |
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5 |
X5 |
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2 |
Y2 |
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2 |
X6 |
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4 |
Y3 |
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4 |
X7 |
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MC14051B
MC14052B
MC14053B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP |
Plastic |
MC14XXXBCL |
Ceramic |
MC14XXXBD |
SOIC |
TA = ± 55° to 125°C for all packages.
MC14053B
Triple 2±Channel Analog
Multiplexer/Demultiplexer
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6 |
INHIBIT |
X |
14 |
CONTROLS |
11 |
A |
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10 |
B |
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9 |
C |
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15 COMMONS |
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12 |
X0 |
Y |
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SWITCHES |
13 |
X1 |
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OUT/IN |
2 |
Y0 |
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IN/OUT |
1 |
Y1 |
Z |
4 |
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5 |
Z0 |
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3 |
Z1 |
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VDD = PIN 16 VSS = PIN 8 VEE = PIN 7
VDD = PIN 16 VSS = PIN 8 VEE = PIN 7
VDD = PIN 16 VSS = PIN 8 VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.
REV 3 1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS
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± 55_C |
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25_C |
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125_C |
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Characteristic |
Symbol |
VDD |
Test Conditions |
Min |
Max |
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Min |
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Typ # |
Max |
Min |
Max |
Unit |
SUPPLY REQUIREMENTS (Voltages Referenced to VEE) |
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Power Supply Voltage |
VDD |
Ð |
VDD ± 3.0 ≥ VSS ≥ VEE |
3.0 |
18 |
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3.0 |
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Ð |
18 |
3.0 |
18 |
V |
Range |
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Quiescent Current Per |
IDD |
5.0 |
Control Inputs: |
Ð |
5.0 |
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Ð |
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0.005 |
5.0 |
Ð |
150 |
μA |
Package |
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10 |
Vin = VSS or VDD, |
Ð |
10 |
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Ð |
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0.010 |
10 |
Ð |
300 |
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15 |
Switch I/O: VEE vVI/O |
Ð |
20 |
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Ð |
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0.015 |
20 |
Ð |
600 |
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v VDD, and |
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Vswitch v 500 mV** |
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Total Supply Current |
ID(AV) |
5.0 |
TA = 25_C only (The |
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(0.07 |
μA/kHz) f + IDD |
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μA |
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(Dynamic Plus |
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10 |
channel component, |
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Typical |
(0.20 |
μA/kHz) f + IDD |
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Quiescent, Per Package |
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15 |
(Vin ± Vout)/Ron, is |
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(0.36 |
μA/kHz) f + IDD |
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not included.) |
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CONTROL INPUTS Ð INHIBIT, A, B, C (Voltages Referenced to VSS) |
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Low±Level Input Voltage |
VIL |
5.0 |
Ron = per spec, |
Ð |
1.5 |
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Ð |
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2.25 |
1.5 |
Ð |
1.5 |
V |
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10 |
Ioff = per spec |
Ð |
3.0 |
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4.50 |
3.0 |
Ð |
3.0 |
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15 |
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Ð |
4.0 |
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6.75 |
4.0 |
Ð |
4.0 |
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High±Level Input Voltage |
VIH |
5.0 |
Ron = per spec, |
3.5 |
Ð |
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3.5 |
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2.75 |
Ð |
3.5 |
Ð |
V |
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10 |
Ioff = per spec |
7.0 |
Ð |
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7.0 |
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5.50 |
Ð |
7.0 |
Ð |
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15 |
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11 |
Ð |
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11 |
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8.25 |
Ð |
11 |
Ð |
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Input Leakage Current |
Iin |
15 |
Vin = 0 or VDD |
Ð |
± 0.1 |
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± 0.00001 |
± 0.1 |
Ð |
1.0 |
μA |
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Input Capacitance |
Cin |
Ð |
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Ð |
Ð |
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5.0 |
7.5 |
Ð |
Ð |
pF |
SWITCHES IN/OUT AND COMMONS OUT/IN Ð X, Y, Z (Voltages Referenced to VEE) |
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Recommended |
VI/O |
Ð |
Channel On or Off |
0 |
VDD |
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0 |
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VDD |
0 |
VDD |
VPP |
Peak±to±Peak Voltage |
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Into or Out of the Switch |
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Recommended Static or |
Vswitch |
Ð |
Channel On |
0 |
600 |
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0 |
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Ð |
600 |
0 |
300 |
mV |
Dynamic Voltage Across |
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the Switch** (Figure 5) |
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Output Offset Voltage |
VOO |
Ð |
Vin = 0 V, No Load |
Ð |
Ð |
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Ð |
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10 |
Ð |
Ð |
Ð |
μV |
ON Resistance |
Ron |
5.0 |
Vswitch v 500 mV**, |
Ð |
800 |
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Ð |
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250 |
1050 |
Ð |
1200 |
Ω |
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10 |
Vin = VIL or VIH |
Ð |
400 |
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120 |
500 |
Ð |
520 |
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15 |
(Control), and Vin = |
Ð |
220 |
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80 |
280 |
Ð |
300 |
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0 to VDD (Switch) |
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ON Resistance Between |
Ron |
5.0 |
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Ð |
70 |
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Ð |
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25 |
70 |
Ð |
135 |
Ω |
Any Two Channels in the |
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10 |
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Ð |
50 |
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Ð |
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10 |
50 |
Ð |
95 |
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Same Package |
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15 |
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Ð |
45 |
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Ð |
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10 |
45 |
Ð |
65 |
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Off±Channel Leakage |
Ioff |
15 |
Vin = VIL or VIH |
Ð |
± 100 |
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± 0.05 |
± 100 |
Ð |
± 1000 |
nA |
Current (Figure 10) |
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(Control) Channel to |
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Channel or Any One |
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Channel |
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Capacitance, Switch I/O |
CI/O |
Ð |
Inhibit = VDD |
Ð |
Ð |
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10 |
Ð |
Ð |
Ð |
pF |
Capacitance, Common O/I |
CO/I |
Ð |
Inhibit = VDD |
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pF |
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(MC14051B) |
Ð |
Ð |
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60 |
Ð |
Ð |
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(MC14052B) |
Ð |
Ð |
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32 |
Ð |
Ð |
Ð |
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(MC14053B) |
Ð |
Ð |
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17 |
Ð |
Ð |
Ð |
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Capacitance, Feedthrough |
CI/O |
Ð |
Pins Not Adjacent |
Ð |
Ð |
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0.15 |
Ð |
Ð |
Ð |
pF |
(Channel Off) |
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Pins Adjacent |
Ð |
Ð |
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0.47 |
Ð |
Ð |
Ð |
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#Data labeled ªTypº is not to be used for design purposes, but is intended as an indication of the IC's potential performance.
*For voltage drops across the switch ( Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.)
MC14051B MC14052B MC14053B |
MOTOROLA CMOS LOGIC DATA |
2 |
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ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C) (VEE v VSS unless otherwise indicated)
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VDD ± VEE |
Typ # |
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Characteristic |
Symbol |
Vdc |
All Types |
Max |
Unit |
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Propagation Delay Times (Figure 6) |
tPLH, tPHL |
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ns |
Switch Input to Switch Output (RL = 10 kΩ) |
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MC14051 |
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tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns |
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5.0 |
35 |
90 |
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tPLH, tPHL = (0.08 ns/pF) CL + 11 ns |
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10 |
15 |
40 |
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tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns |
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15 |
12 |
30 |
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MC14052 |
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ns |
tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns |
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5.0 |
30 |
75 |
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tPLH, tPHL = (0.08 ns/pF) CL + 8.0 ns |
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10 |
12 |
30 |
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tPLH, tPHL = (0.06 ns/pF) CL + 7.0 ns |
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15 |
10 |
25 |
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MC14053 |
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ns |
tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns |
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5.0 |
25 |
65 |
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tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns |
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10 |
8.0 |
20 |
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tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns |
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15 |
6.0 |
15 |
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Inhibit to Output (RL = 10 kΩ, VEE = VSS) |
tPHZ, tPLZ, |
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ns |
Output ª1º or ª0º to High Impedance, or |
tPZH, tPZL |
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High Impedance to ª1º or ª0º Level |
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MC14051B |
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5.0 |
350 |
700 |
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10 |
170 |
340 |
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15 |
140 |
280 |
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MC14052B |
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5.0 |
300 |
600 |
ns |
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10 |
155 |
310 |
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15 |
125 |
250 |
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MC14053B |
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5.0 |
275 |
550 |
ns |
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10 |
140 |
280 |
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15 |
110 |
220 |
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Control Input to Output (RL = 10 kΩ, VEE = VSS) |
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tPLH, tPHL |
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ns |
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MC14051B |
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5.0 |
360 |
720 |
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10 |
160 |
320 |
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15 |
120 |
240 |
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MC14052B |
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5.0 |
325 |
650 |
ns |
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10 |
130 |
260 |
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15 |
90 |
180 |
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MC14053B |
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5.0 |
300 |
600 |
ns |
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10 |
120 |
240 |
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15 |
80 |
160 |
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Second Harmonic Distortion |
Ð |
10 |
0.07 |
Ð |
% |
(RL = 10KΩ, f = 1 kHz) Vin = 5 VPP |
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Bandwidth (Figure 7) |
BW |
10 |
17 |
Ð |
MHz |
(RL = 1 kΩ, Vin = 1/2 (VDD±VEE) p±p, CL = 50pF |
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20 Log (Vout/Vin) = ± 3 dB) |
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Off Channel Feedthrough Attenuation (Figure 7) |
Ð |
10 |
± 50 |
Ð |
dB |
RL = 1KΩ, Vin = 1/2 (VDD ± VEE) p±p |
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fin = 4.5 MHz Ð MC14051B |
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fin = 30 MHz Ð MC14052B |
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fin = 55 MHz Ð MC14053B |
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Channel Separation (Figure 8) |
Ð |
10 |
± 50 |
Ð |
dB |
(RL = 1 kΩ, Vin = 1/2 (VDD±VEE) p±p, |
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fin = 3.0 MHz |
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Crosstalk, Control Input to Common O/I (Figure 9) |
Ð |
10 |
75 |
Ð |
mV |
(R1 = 1 kΩ, RL = 10 kΩ |
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Control tTLH = tTHL = 20 ns, Inhibit = VSS) |
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* The formulas given are for the typical characteristics only at 25_C.
#Data labelled ªTypº is not lo be used for design purposes but In intended as an indication of the IC's potential performance.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs must be left open.
MOTOROLA CMOS LOGIC DATA |
MC14051B MC14052B MC14053B |
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3 |
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