MOTOROLA MC14069UBFEL, MC14069UBFL1, MC14069UBFL2, MC14069UBFR1, MC14069UBD Datasheet

MC14069UB

Hex Inverter

The MC14069UB hex inverter is constructed with MOS P±channel and N±channel enhancement mode devices in a single monolithic structure. These inverters find primary use where low power dissipation and/or high noise immunity is desired. Each of the six inverters is a single stage to minimize propagation delays.

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low±Power TTL Loads or One Low±Power Schottky TTL Load Over the Rated Temperature Range

•Triple Diode Protection on All Inputs

•Pin±for±Pin Replacement for CD4069UB

•Meets JEDEC UB Specifications

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol	Parameter	Value	Unit
VDD	DC Supply Voltage Range	± 0.5 to +18.0	V
Vin, Vout	Input or Output Voltage Range	± 0.5 to VDD + 0.5	V
	(DC or Transient)
Iin, Iout	Input or Output Current	± 10	mA
	(DC or Transient) per Pin
PD	Power Dissipation,	500	mW
	per Package (Note 3.)
TA	Ambient Temperature Range	± 55 to +125	°C
Tstg	Storage Temperature Range	± 65 to +150	°C
TL	Lead Temperature	260	°C
	(8±Second Soldering)

2.Maximum Ratings are those values beyond which damage to the device may occur.

3.Temperature Derating:

Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

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		MARKING
		DIAGRAMS
		14
	PDIP±14	MC14069UBCP
	P SUFFIX
		AWLYYWW
	CASE 646
		1
		14
	SOIC±14	14069U
	D SUFFIX
		AWLYWW
	CASE 751A
		1
		14
	TSSOP±14	14
	DT SUFFIX	069U
	CASE 948G	ALYW
		1
		14
	SOEIAJ±14	MC14069U
	F SUFFIX
		AWLYWW
	CASE 965
		1
A	= Assembly Location
WL or L = Wafer Lot
YY or Y	= Year
WW or W = Work Week
ORDERING INFORMATION
Device	Package	Shipping
MC14069UBCP	PDIP±14	2000/Box
MC14069UBD	SOIC±14	2750/Box
MC14069UBDR2	SOIC±14	2500/Tape & Reel

MC14069UBDT TSSOP±14 96/Rail

MC14069UBDTEL TSSOP±14 2000/Tape & Reel

MC14069UBDTR2 TSSOP±14 2500/Tape & Reel

MC14069UBF	SOEIAJ±14	See Note 1.
MC14069UBFEL	SOEIAJ±14	See Note 1.

1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
March, 2000 ± Rev. 3		MC14069UB/D

MC14069UB

PIN ASSIGNMENT

IN 1	1	14	VDD
OUT 1	2	13	IN 6
IN 2	3	12	OUT 6
OUT 2	4	11	IN 5
IN 3	5	10	OUT 5
OUT 3	6	9	IN 4
VSS	7	8	OUT 4

	LOGIC DIAGRAM		CIRCUIT SCHEMATIC
			(1/6 OF CIRCUIT SHOWN)
1	2		VDD
3	4	VDD = PIN 14
		VSS = PIN 7
5	6		INPUT*	OUTPUT
9	8
11	10		VSS
13	12		*Double diode protection on all
			inputs not shown.

		VDD	20 ns			20 ns
						VDD
		14 OUTPUT		90%
PULSE			INPUT	50%
GENERATOR	INPUT			10%		VSS
			tPHL
						tPLH
	7	VSS	CL		90%	V
			OUTPUT			OH
					50%
					10%	VOL
				tTHL		tTLH

Figure 1. Switching Time Test Circuit and Waveforms

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MC14069UB

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Symbo

VDD

± 55_C

25_C

125_C

Characteristic

l

Vdc

Min

Max

Min

Typ (4.)

Max

Min

Max

Unit

Output Voltage

ª0º Level

VOL

5.0

Ð

0.05

Ð

0

0.05

Ð

0.05

Vdc

Vin = VDD

10

Ð

0.05

Ð

0

0.05

Ð

0.05

15

Ð

0.05

Ð

0

0.05

Ð

0.05

Vin = 0

ª1º Level

VOH

5.0

4.95

Ð

4.95

5.0

Ð

4.95

Ð

Vdc

10

9.95

Ð

9.95

10

Ð

9.95

Ð

15

14.95

Ð

14.95

15

Ð

14.95

Ð

Input Voltage

ª0º Level

VIL

Vdc

(VO = 4.5 Vdc)

5.0

Ð

1.0

Ð

2.25

1.0

Ð

1.0

(VO = 9.0 Vdc)

10

Ð

2.0

Ð

4.50

2.0

Ð

2.0

(VO = 13.5 Vdc)

15

Ð

2.5

Ð

6.75

2.5

Ð

2.5

(VO = 0.5 Vdc)

ª1º Level

VIH

5.0

4.0

Ð

4.0

2.75

Ð

4.0

Ð

Vdc

(VO = 1.0 Vdc)

10

8.0

Ð

8.0

5.50

Ð

8.0

Ð

(VO = 1.5 Vdc)

15

12.5

Ð

12.5

8.25

Ð

12.5

Ð

Output Drive Current

IOH

mAdc

(VOH = 2.5 Vdc)

Source

5.0

± 3.0

Ð

± 2.4

± 4.2

Ð

± 1.7

Ð

(VOH = 4.6 Vdc)

5.0

± 0.64

Ð

± 0.51

± 0.88

Ð

± 0.36

Ð

(VOH = 9.5 Vdc)

10

± 1.6

Ð

± 1.3

± 2.25

Ð

± 0.9

Ð

(VOH = 13.5 Vdc)

15

± 4.2

Ð

± 3.4

± 8.8

Ð

± 2.4

Ð

(VOL = 0.4 Vdc)

Sink

IOL

5.0

0.64

Ð

0.51

0.88

Ð

0.36

Ð

mAdc

(VOL = 0.5 Vdc)

10

1.6

Ð

1.3

2.25

Ð

0.9

Ð

(VOL = 1.5 Vdc)

15

4.2

Ð

3.4

8.8

Ð

2.4

Ð

Input Current

Iin

15

Ð

± 0.1

Ð

± 0.00001

± 0.1

Ð

± 1.0

μAdc

Input Capacitance

Cin

Ð

Ð

Ð

Ð

5.0

7.5

Ð

Ð

pF

(Vin = 0)

Quiescent Current

IDD

5.0

Ð

0.25

Ð

0.0005

0.25

Ð

7.5

μAdc

(Per Package)

10

Ð

0.5

Ð

0.0010

0.5

Ð

15

15

Ð

1.0

Ð

0.0015

1.0

Ð

30

Total Supply Current (5.) (6.)

I

5.0

I = (0.3 μA/kHz) f + I

DD

/6

μAdc

T

T

(Dynamic plus Quiescent,

10

IT = (0.6 μA/kHz) f + IDD/6

Per Gate) (CL = 50 pF)

15

IT = (0.9 μA/kHz) f + IDD/6

Output Rise and Fall Times (5.)

t

TLH

,

ns

(CL = 50 pF)

tTHL

5.0

Ð

Ð

Ð

100

200

Ð

Ð

tTLH, tTHL = (1.35 ns/pF) CL + 33 ns

10

Ð

Ð

Ð

50

100

Ð

Ð

tTLH, tTHL = (0.60 ns/pF) CL + 20 ns

15

Ð

Ð

Ð

40

80

Ð

Ð

tTLH, tTHL = (0.40 ns/pF) CL + 20 ns

Propagation Delay Times (5.)

t

,

ns

PLH

(CL = 50 pF)

tPHL

tPLH, tPHL = (0.90 ns/pF) CL + 20 ns

5.0

Ð

Ð

Ð

65

125

Ð

Ð

tPLH, tPHL = (0.36 ns/pF) CL + 22 ns

10

Ð

Ð

Ð

40

75

Ð

Ð

tPLH, tPHL = (0.26 ns/pF) CL + 17 ns

15

Ð

Ð

Ð

30

55

Ð

Ð

4.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.

5.The formulas given are for the typical characteristics only at 25_C.

6.To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL ± 50) Vfk

where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.002.

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