Motorola MC14077BD, MC14077BCL, MC14070BCL, MC14070BCP, MC14070BD Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

		MC14070B
	CMOS SSI	MC14077B
	Quad Exclusive ªORº and ªNORº Gates
	The MC14070B quad exclusive OR gate and the MC14077B quad
	exclusive NOR gate are constructed with MOS P±channel and N±channel
	enhancement mode devices in a single monolithic structure. These	L SUFFIX
	complementary MOS logic gates find primary use where low power
		CERAMIC
	dissipation and/or high noise immunity is desired.	CASE 632

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•All Outputs Buffered

• Capable of Driving Two Low±Power TTL Loads or One Low±Power	P SUFFIX
Schottky TTL Load Over the Rated Temperature Range	PLASTIC
• Double Diode Protection on All Inputs	CASE 646

•MC14070B Ð Replacement for CD4030B and CD4070B Types

•MC14077B Ð Replacement for CD4077B Type

	MAXIMUM RATINGS* (Voltages Referenced to VSS)							D SUFFIX
								SOIC
	Symbol		Parameter		Value	Unit		CASE 751A
	VDD	DC Supply Voltage			± 0.5 to + 18.0	V	ORDERING INFORMATION
	Vin, Vout	Input or Output Voltage (DC or Transient)			± 0.5 to VDD + 0.5	V	MC14XXXBCP	Plastic
	Iin, Iout	Input or Output Current (DC or Transient),			± 10	mA	MC14XXXBCL	Ceramic
							MC14XXXBD	SOIC
		per Pin					TA = ± 55° to 125°C for all packages.
	PD	Power Dissipation, per Package²			500	mW
	Tstg	Storage Temperature			± 65 to + 150	_C
	TL	Lead Temperature (8±Second Soldering)			260	_C	MC14070B	MC14077B
	* Maximum Ratings are those values beyond which damage to the device may occur.						QUAD Exclusive OR	QUAD Exclusive NOR
							Gate	Gate
	²Temperature Derating:
	Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C						1	1
				_	_		3	3
	Ceramic ªLº Packages: ± 12 mW/C From 100 C To 125 C						2	2
			20 ns		20 ns		5	5
		V				VDD	4	4
				90%			6	6
		DD
				50%			8	8
		I	Vin	10%		VSS	10	10
		DD			1/f		9	9
	Vin	*					12	12
				50% DUTY CYCLE
							11	11
			CL				13	13
							VDD = PIN 14
			* Inverted output on MC14077B only.
							VSS = PIN 7
							(BOTH DEVICES)

Figure 1. Power Dissipation Test Circuit and Waveform

	VDD	20 ns		20 ns	PIN ASSIGNMENT
				VDD
PULSE			90%		IN 1A	1	14	VDD
	*	INPUT	50%
GENERATOR	#		10%	VSS	IN 2A	2	13	IN 2D
		tPHL
	CL			tPLH	OUTA	3	12	IN 1D
	VSS	OUTPUT	90%	VOH
			50%		OUTB	4	11	OUTD
			10%	VOL
		tTHL			IN 1B	5	10	OUTC
* Inverted output on MC14077B only.				tTLH
					IN 2B	6	9	IN 2C
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.

VSS			7	8 IN 1C
Figure 2. Switching Time Test Circuit and Waveforms

REV 3 1/94

Motorola, Inc. 1995

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD

± 55_C

25_C

125_C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ #

Max

Min

Max

Unit

Output Voltage

ª0º Leve

VOL

5.0

Ð

0.05

Ð

0

0.05

Ð

0.05

Vdc

Vin = VDD or 0

10

Ð

0.05

Ð

0

0.05

Ð

0.05

15

Ð

0.05

Ð

0

0.05

Ð

0.05

ª1º Leve

VOH

5.0

4.95

Ð

4.95

5.0

Ð

4.95

Ð

Vdc

Vin = 0 or VDD

10

9.95

Ð

9.95

10

Ð

9.95

Ð

15

14.95

Ð

14.95

15

Ð

14.95

Ð

Input Voltage

ª0º Leve

VIL

Vdc

(VO = 4.5 or 0.5 Vdc)

5.0

Ð

1.5

Ð

2.25

1.5

Ð

1.5

(VO = 9.0 or 1.0 Vdc)

10

Ð

3.0

Ð

4.50

3.0

Ð

3.0

(VO = 13.5 or 1.5 Vdc)

15

Ð

4.0

Ð

6.75

4.0

Ð

4.0

(VO = 0.5 or 4.5 Vdc)

ª1º Leve

VIH

5.0

3.5

Ð

3.5

2.75

Ð

3.5

Ð

Vdc

(VO = 1.0 or 9.0 Vdc)

10

7.0

Ð

7.0

5.50

Ð

7.0

Ð

(VO = 1.5 or 13.5 Vdc)

15

11

Ð

11

8.25

Ð

11

Ð

Output Drive Current

IOH

mAdc

(VOH = 2.5 Vdc)

Source

5.0

± 3.0

Ð

± 2.4

± 4.2

Ð

± 1.7

Ð

(VOH = 4.6 Vdc)

5.0

± 0.64

Ð

± 0.51

± 0.88

Ð

± 0.36

Ð

(VOH = 9.5 Vdc)

10

± 1.6

Ð

± 1.3

± 2.25

Ð

± 0.9

Ð

(VOH = 13.5 Vdc)

15

± 4.2

Ð

± 3.4

± 8.8

Ð

± 2.4

Ð

(VOL = 0.4 Vdc)

Sink

IOL

5.0

0.64

Ð

0.51

0.88

Ð

0.36

Ð

mAdc

(VOL = 0.5 Vdc)

10

1.6

Ð

1.3

2.25

Ð

0.9

Ð

(VOL = 1.5 Vdc)

15

4.2

Ð

3.4

8.8

Ð

2.4

Ð

Input Current

Iin

15

Ð

± 0.1

Ð

± 0.00001

± 0.1

Ð

± 1.0

μAdc

Input Capacitance

Cin

Ð

Ð

Ð

Ð

5.0

7.5

Ð

Ð

pF

(Vin = 0)

Quiescent Current

IDD

5.0

Ð

0.25

Ð

0.0005

0.25

Ð

7.5

μAdc

(Per Package)

10

Ð

0.5

Ð

0.0010

0.5

Ð

15

15

Ð

1.0

Ð

0.0015

1.0

Ð

30

Total Supply Current**²

IT

5.0

IT = (0.3 μA/kHz) f + IDD

μAdc

(Dynamic plus Quiescent,

10

IT = (0.6 μA/kHz) f + IDD

Per Package)

15

IT = (0.9 μA/kHz) f + IDD

(CL = 50 pF on all outputs, all

buffers switching)

Output Rise and Fall Times**

tTLH,

ns

(CL = 50 pF)

tTHL

tTLH, tTHL = (1.35 ns/pF) CL + 33 ns

5.0

Ð

Ð

Ð

100

200

Ð

Ð

tTLH, tTHL = (0.60 ns/pF) CL + 20 ns

10

Ð

Ð

Ð

50

100

Ð

Ð

tTLH, tTHL = (0.40 ns/pF) CL + 20 ns

15

Ð

Ð

Ð

40

80

Ð

Ð

Propagation Delay Times**

tPLH,

ns

(CL = 50 pF)

tPHL

tPLH, tPHL = (0.90 ns/pF) CL + 130ns

5.0

Ð

Ð

Ð

175

350

Ð

Ð

tPLH, tPHL = (0.36 ns/pF) CL + 57 ns

10

Ð

Ð

Ð

75

150

Ð

Ð

tPLH, tPHL = (0.26 ns/pF) CL + 37 ns

15

Ð

Ð

Ð

55

110

Ð

Ð

#Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C.

²T o calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL ± 50) Vfk

where: IT is in μH (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.002.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance

circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

MC14070B MC14077B	MOTOROLA CMOS LOGIC DATA
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