MOTOROLA MC14511BDWR2, MC14511BF, MC14511BFEL, MC14511BFR1, MC14511BCP Datasheet
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MC14511B
BCD-To-Seven Segment
Latch/Decoder/Driver
The MC14511B BCD±to±seven segment latch/decoder/driver is constructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the functions of a 4±bit storage latch, an 8421 BCD±to±seven segment decoder, and an output drive capability. Lamp test (LT), blanking (BI), and latch enable (LE) inputs are used to test the display, to turn±off or pulse modulate the brightness of the display, and to store a BCD code, respectively. It can be used with seven±segment light±emitting diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses.
•Low Logic Circuit Power Dissipation
•High±Current Sourcing Outputs (Up to 25 mA)
•Latch Storage of Code
•Blanking Input
•Lamp Test Provision
•Readout Blanking on all Illegal Input Combinations
•Lamp Intensity Modulation Capability
•Time Share (Multiplexing) Facility
•Supply Voltage Range = 3.0 V to 18 V
•Capable of Driving Two Low±power TTL Loads, One Low±power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range
•Chip Complexity: 216 FETs or 54 Equivalent Gates
•Triple Diode Protection on all Inputs
MAXIMUM RATINGS (Voltages Referenced to V ) (2.) |
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SS |
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Symbol |
Parameter |
Value |
Unit |
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VDD |
DC Supply Voltage Range |
± 0.5 to +18.0 |
V |
Vin |
Input Voltage Range, All Inputs |
± 0.5 to VDD + 0.5 |
V |
I |
DC Current Drain per Input Pin |
10 |
mA |
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PD |
Power Dissipation, |
500 |
mW |
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per Package (3.) |
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TA |
Operating Temperature Range |
± 55 to +125 |
°C |
Tstg |
Storage Temperature Range |
± 65 to +150 |
°C |
IOHmax |
Maximum Output Drive Current |
25 |
mA |
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(Source) per Output |
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POHmax |
Maximum Continuous Output |
50 |
mA |
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Power (Source) per Output (4.) |
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2.Maximum Ratings are those values beyond which damage to the device may occur.
3.Temperature Derating:
Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C
4.POHmax = IOH (VDD ± VOH)
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MARKING |
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DIAGRAMS |
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16 |
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PDIP±16 |
MC14511BCP |
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P SUFFIX |
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AWLYYWW |
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CASE 648 |
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1 |
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16 |
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SOIC±16 |
14511B |
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D SUFFIX |
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AWLYWW |
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CASE 751B |
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1 |
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16 |
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SOIC±16 |
14511B |
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DW SUFFIX |
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CASE 751G |
AWLYYWW |
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1 |
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16 |
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SOEIAJ±16 |
MC14511B |
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F SUFFIX |
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AWLYWW |
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CASE 966 |
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1 |
A |
= Assembly Location |
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WL or L = Wafer Lot |
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YY or Y |
= Year |
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WW or W = Work Week |
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ORDERING INFORMATION |
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Device |
Package |
Shipping |
MC14511BCP |
PDIP±16 |
2000/Box |
MC14511BD |
SOIC±16 |
48/Rail |
MC14511BDW |
SOIC±16 |
47/Rail |
MC14511BDWR2 |
SOIC±16 |
1000/Tape & Reel |
MC14511BF |
SOEIAJ±16 |
See Note 1. |
MC14511BFEL |
SOEIAJ±16 |
See Note 1. |
1.For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
Semiconductor Components Industries, LLC, 2000 |
1 |
Publication Order Number: |
March, 2000 ± Rev. 3 |
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MC14511B/D |
MC14511B
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high±impedance circuit. A
destructive high current mode may occur if Vin and Vout are not constrained to the range VSS v (Vin or Vout) v VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to VSS and are at a logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
PIN ASSIGNMENT
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B |
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1 |
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16 |
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VDD |
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C |
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2 |
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15 |
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f |
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a |
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g |
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LT |
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3 |
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14 |
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f |
g b |
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BI |
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4 |
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13 |
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a |
e |
c |
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LE |
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5 |
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12 |
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b |
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d |
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D |
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6 |
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11 |
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c |
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A |
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7 |
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10 |
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d |
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VSS |
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8 |
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9 |
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e |
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DISPLAY |
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0 |
1 |
2 |
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3 |
4 |
5 |
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6 |
7 |
8 |
9 |
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TRUTH TABLE
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Inputs |
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Outputs |
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LE |
BI |
LT |
D |
C |
B |
A |
a |
b |
c |
d |
e |
f |
g |
Display |
X |
X |
0 |
X X X X |
1 1 1 1 1 1 1 |
8 |
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X |
0 |
1 |
X |
X |
X |
X |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Blank |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
2 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
3 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
4 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
5 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
6 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
7 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
8 |
0 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
9 |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Blank |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Blank |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Blank |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Blank |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Blank |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Blank |
1 |
1 |
1 |
X |
X |
X |
X |
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* |
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* |
X = Don't Care
* Depends upon the BCD code previously applied when LE = 0
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2
MC14511B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
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VDD |
± 55_C |
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25_C |
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125_C |
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Characteristic |
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Symbol |
Vdc |
Min |
Max |
Min |
Typ (5.) |
Max |
Min |
Max |
Unit |
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Output Voltage |
ª0º Level |
VOL |
5.0 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
Vdc |
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Vin = VDD or 0 |
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10 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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15 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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ª1º Level |
VOH |
5.0 |
4.1 |
Ð |
4.1 |
4.57 |
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Ð |
4.1 |
Ð |
Vdc |
Vin = 0 or VDD |
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10 |
9.1 |
Ð |
9.1 |
9.58 |
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9.1 |
Ð |
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15 |
14.1 |
Ð |
14.1 |
14.59 |
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14.1 |
Ð |
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Input Voltage # |
ª0º Level |
VIL |
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Vdc |
(VO = 3.8 or 0.5 Vdc) |
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5.0 |
Ð |
1.5 |
Ð |
2.25 |
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1.5 |
Ð |
1.5 |
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(VO = 8.8 or 1.0 Vdc) |
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10 |
Ð |
3.0 |
Ð |
4.50 |
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3.0 |
Ð |
3.0 |
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(VO = 13.8 or 1.5 Vdc) |
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15 |
Ð |
4.0 |
Ð |
6.75 |
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4.0 |
Ð |
4.0 |
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ª1º Level |
VIH |
5.0 |
3.5 |
Ð |
3.5 |
2.75 |
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Ð |
3.5 |
Ð |
Vdc |
(VO = 0.5 or 3.8 Vdc) |
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(VO = 1.0 or 8.8 Vdc) |
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10 |
7.0 |
Ð |
7.0 |
5.50 |
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Ð |
7.0 |
Ð |
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(VO = 1.5 or 13.8 Vdc) |
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15 |
11 |
Ð |
11 |
8.25 |
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Ð |
11 |
Ð |
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Output Drive Voltage |
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VOH |
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Vdc |
(IOH = 0 mA) |
Source |
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5.0 |
4.1 |
Ð |
4.1 |
4.57 |
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Ð |
4.1 |
Ð |
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(IOH = 5.0 mA) |
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Ð |
Ð |
Ð |
4.24 |
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Ð |
Ð |
Ð |
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(IOH = 10 mA) |
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3.9 |
Ð |
3.9 |
4.12 |
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Ð |
3.5 |
Ð |
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(IOH = 15 mA) |
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Ð |
Ð |
Ð |
3.94 |
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Ð |
Ð |
Ð |
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(IOH = 20 mA) |
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3.4 |
Ð |
3.4 |
3.70 |
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Ð |
3.0 |
Ð |
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(IOH = 25 mA) |
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Ð |
Ð |
Ð |
3.54 |
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Ð |
Ð |
Ð |
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(IOH = 0 mA) |
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10 |
9.1 |
Ð |
9.1 |
9.58 |
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Ð |
9.1 |
Ð |
Vdc |
(IOH = 5.0 mA) |
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Ð |
Ð |
Ð |
9.26 |
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Ð |
Ð |
Ð |
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(IOH = 10 mA) |
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9.0 |
Ð |
9.0 |
9.17 |
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Ð |
8.6 |
Ð |
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(IOH = 15 mA) |
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Ð |
Ð |
Ð |
9.04 |
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Ð |
Ð |
Ð |
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(IOH = 20 mA) |
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8.6 |
Ð |
8.6 |
8.90 |
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Ð |
8.2 |
Ð |
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(IOH = 25 mA) |
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Ð |
Ð |
Ð |
8.70 |
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Ð |
Ð |
Ð |
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(IOH = 0 mA) |
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15 |
14.1 |
Ð |
14.1 |
14.59 |
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Ð |
14.1 |
Ð |
Vdc |
(IOH = 5.0 mA) |
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Ð |
Ð |
Ð |
14.27 |
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Ð |
Ð |
Ð |
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(IOH = 10 mA) |
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14 |
Ð |
14 |
14.18 |
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Ð |
13.6 |
Ð |
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(IOH = 15 mA) |
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Ð |
Ð |
Ð |
14.07 |
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Ð |
Ð |
Ð |
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(IOH = 20 mA) |
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13.6 |
Ð |
13.6 |
13.95 |
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Ð |
13.2 |
Ð |
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(IOH = 25 mA) |
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Ð |
Ð |
Ð |
13.70 |
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Ð |
Ð |
Ð |
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Output Drive Current |
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IOL |
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mAdc |
(VOL = 0.4 V) |
Sink |
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5.0 |
0.64 |
Ð |
0.51 |
0.88 |
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Ð |
0.36 |
Ð |
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(VOL = 0.5 V) |
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10 |
1.6 |
Ð |
1.3 |
2.25 |
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Ð |
0.9 |
Ð |
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(VOL = 1.5 V) |
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15 |
4.2 |
Ð |
3.4 |
8.8 |
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Ð |
2.4 |
Ð |
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Input Current |
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Iin |
15 |
Ð |
± 0.1 |
Ð |
± 0.00001 |
± 0.1 |
Ð |
± 1.0 |
μAdc |
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Input Capacitance |
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Cin |
Ð |
Ð |
Ð |
Ð |
5.0 |
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7.5 |
Ð |
Ð |
pF |
Quiescent Current |
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IDD |
5.0 |
Ð |
5.0 |
Ð |
0.005 |
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5.0 |
Ð |
150 |
μAdc |
(Per Package) Vin = 0 or VDD, |
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10 |
Ð |
10 |
Ð |
0.010 |
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10 |
Ð |
300 |
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Iout = 0 μA |
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15 |
Ð |
20 |
Ð |
0.015 |
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20 |
Ð |
600 |
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Total Supply Current (6.) (7.) |
I |
5.0 |
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I = (1.9 μA/kHz) f + I |
DD |
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μAdc |
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T |
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T |
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(Dynamic plus Quiescent, |
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10 |
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IT = (3.8 μA/kHz) f + IDD |
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Per Package) |
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15 |
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IT = (5.7 μA/kHz) f + IDD |
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(CL = 50 pF on all outputs, all |
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buffers switching) |
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5.Noise immunity specified for worst±case input combination. Noise Margin for both ª1º and ª0º level =
1.0Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5Vdc min @ VDD = 15 Vdc
6.The formulas given are for the typical characteristics only at 25_C.
7.To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10±3 (CL ± 50) VDDf
where: IT is in μA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
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3
MC14511B
SWITCHING CHARACTERISTICS (8.) (CL = 50 pF, TA = 25_C)
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VDD |
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Characteristic |
Symbol |
Vdc |
Min |
Typ |
Max |
Unit |
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Output Rise Time |
tTLH |
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ns |
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tTLH = (0.40 ns/pF) CL + 20 ns |
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5.0 |
Ð |
40 |
80 |
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tTLH = (0.25 ns/pF) CL + 17.5 ns |
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10 |
Ð |
30 |
60 |
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tTLH = (0.20 ns/pF) CL + 15 ns |
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15 |
Ð |
25 |
50 |
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Output Fall Time |
tTHL |
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ns |
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tTHL = (1.5 ns/pF) CL + 50 ns |
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5.0 |
Ð |
125 |
250 |
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tTHL = (0.75 ns/pF) CL + 37.5 ns |
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10 |
Ð |
75 |
150 |
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tTHL = (0.55 ns/pF) CL + 37.5 ns |
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15 |
Ð |
65 |
130 |
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Data Propagation Delay Time |
tPLH |
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ns |
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tPLH = (0.40 ns/pF) CL + 620 ns |
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5.0 |
Ð |
640 |
1280 |
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tPLH = (0.25 ns/pF) CL + 237.5 ns |
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10 |
Ð |
250 |
500 |
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tPLH = (0.20 ns/pF) CL + 165 ns |
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15 |
Ð |
175 |
350 |
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tPHL = (1.3 ns/pF) CL + 655 ns |
tPHL |
5.0 |
Ð |
720 |
1440 |
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tPHL = (0.60 ns/pF) CL + 260 ns |
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10 |
Ð |
290 |
580 |
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tPHL = (0.35 ns/pF) CL + 182.5 ns |
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15 |
Ð |
200 |
400 |
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Propagation Delay Time |
tPLH |
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ns |
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Blank |
5.0 |
Ð |
600 |
750 |
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tPLH = (0.30 ns/pF) CL + 585 ns |
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|
||||||
|
|
tPLH = (0.25 ns/pF) CL + 187.5 ns |
|
I0 |
Ð |
200 |
300 |
|
||
|
|
tPLH = (0.15 ns/pF) CL + 142.5 ns |
|
15 |
Ð |
150 |
220 |
|
||
|
|
tPHL = (0.85 ns/pF) CL + 442.5 ns |
tPHL |
5.0 |
Ð |
485 |
970 |
|
||
|
|
tPHL = (0.45 ns/pF) CL + 177.5 ns |
|
10 |
Ð |
200 |
400 |
|
||
|
|
tPHL = (0.35 ns/pF) CL + 142.5 ns |
|
15 |
Ð |
160 |
320 |
|
||
|
|
|
|
Propagation Delay Time |
tPLH |
|
|
|
|
ns |
|
Lamp Test |
|
|
|
|
|||||
|
|
tPLH = (0.45 ns/pF) CL + 290.5 ns |
|
5.0 |
Ð |
313 |
625 |
|
||
|
|
tPLH = (0.25 ns/pF) CL + 112.5 ns |
|
10 |
Ð |
125 |
250 |
|
||
|
|
tPLH = (0.20 ns/pF) CL + 80 ns |
|
15 |
Ð |
90 |
180 |
|
||
|
|
tPHL = (1.3 ns/pF) CL + 248 ns |
tPHL |
5.0 |
Ð |
313 |
625 |
|
||
|
|
tPHL = (0.45 ns/pF) CL + 102.5 ns |
|
10 |
Ð |
125 |
250 |
|
||
|
|
tPHL = (0.35 ns/pF) CL + 72.5 ns |
|
15 |
Ð |
90 |
180 |
|
||
|
Setup Time |
tsu |
5.0 |
100 |
Ð |
Ð |
ns |
|||
|
|
|
|
|
|
10 |
40 |
Ð |
Ð |
|
|
|
|
|
|
|
15 |
30 |
Ð |
Ð |
|
|
|
|
|
|
|
|
|
|||
|
Hold Time |
th |
5.0 |
60 |
Ð |
Ð |
ns |
|||
|
|
|
|
|
|
10 |
40 |
Ð |
Ð |
|
|
|
|
|
|
|
15 |
30 |
Ð |
Ð |
|
|
|
|
|
|
|
|
|
|||
|
Latch Enable Pulse Width |
tWL |
5.0 |
520 |
260 |
Ð |
ns |
|||
|
|
|
|
|
|
10 |
220 |
110 |
Ð |
|
|
|
|
|
|
|
15 |
130 |
65 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|
8. The formulas given are for the typical characteristics only.
http://onsemi.com
4
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