MOTOROLA MC14024BFL1, MC14024BFL2, MC14024BFR1, MC14024BFR2, MC14024BF Datasheet
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MC14024B
7-Stage Ripple Counter
The MC14024B is a 7±stage ripple counter with short propagation delays and high maximum clock rates. The Reset input has standard noise immunity, however the Clock input has increased noise immunity due to Hysteresis. The output of each counter stage is buffered.
•Diode Protection on All Inputs
•Output Transitions Occur on the Falling Edge of the Clock Pulse
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low±power TTL Loads or One Low±power Schottky TTL Load Over the Rated Temperature Range
•Pin±for±Pin Replacement for CD4024B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note NO TAG)
Symbol |
Parameter |
Value |
Unit |
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VDD |
DC Supply Voltage Range |
± 0.5 to +18.0 |
V |
Vin, Vout |
Input or Output Voltage Range |
± 0.5 to VDD + 0.5 |
V |
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(DC or Transient) |
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Iin, Iout |
Input or Output Current |
± 10 |
mA |
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(DC or Transient) per Pin |
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PD |
Power Dissipation, |
500 |
mW |
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per Package (Note NO TAG) |
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TA |
Ambient Temperature Range |
± 55 to +125 |
°C |
Tstg |
Storage Temperature Range |
± 65 to +150 |
°C |
TL |
Lead Temperature |
260 |
°C |
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(8±Second Soldering) |
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2.Maximum Ratings are those values beyond which damage to the device may occur.
3.Temperature Derating:
Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
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MARKING |
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DIAGRAMS |
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14 |
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PDIP±14 |
MC14024BCP |
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P SUFFIX |
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AWLYYWW |
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CASE 646 |
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1 |
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14 |
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SOIC±14 |
14024B |
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D SUFFIX |
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AWLYWW |
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CASE 751A |
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1 |
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14 |
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SOEIAJ±14 |
MC14024B |
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F SUFFIX |
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AWLYWW |
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CASE 965 |
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1 |
A |
= Assembly Location |
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WL or L = Wafer Lot |
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YY or Y |
= Year |
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WW or W = Work Week |
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ORDERING INFORMATION |
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Device |
Package |
Shipping |
MC14024BCP |
PDIP±14 |
2000/Box |
MC14024BD |
SOIC±14 |
2750/Box |
MC14024BDR2 |
SOIC±14 |
2500/Tape & Reel |
MC14024BF |
SOEIAJ±14 |
See Note 1. |
MC14024BFEL |
SOEIAJ±14 |
See Note 1. |
1.For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
Semiconductor Components Industries, LLC, 2000 |
1 |
Publication Order Number: |
March, 2000 ± Rev. 3 |
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MC14024B/D |
MC14024B
TRUTH TABLE
Clock |
Reset |
State |
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0 |
0 |
No Change |
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0 |
1 |
All Outputs Low |
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1 |
0 |
No Change |
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1 |
1 |
All Outputs Low |
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0 |
No Change |
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1 |
All Outputs Low |
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0 |
Advance One Count |
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1 |
All Outputs Low |
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PIN ASSIGNMENT
CLOCK |
1 |
14 |
VDD |
RESET |
2 |
13 |
NC |
Q7 |
3 |
12 |
Q1 |
Q6 |
4 |
11 |
Q2 |
Q5 |
5 |
10 |
NC |
Q4 |
6 |
9 |
Q3 |
VSS |
7 |
8 |
NC |
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VDD = PIN 14 |
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VSS = PIN 7
NC = NO CONNECTION
LOGIC DIAGRAM
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1 |
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CLOCK |
C |
Q |
C |
Q |
C |
Q |
C |
Q |
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R |
Q |
R |
Q |
R |
Q |
R |
Q |
RESET |
2 |
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12 |
11 |
4 |
3 |
Q1 |
Q2 |
Q6 |
Q7 |
Q3 = PIN 9
Q4 = PIN 6
Q5 = PIN 5
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MC14024B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
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VDD |
± 55_C |
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25_C |
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125_C |
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Characteristic |
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Symbol |
Vdc |
Min |
Max |
Min |
Typ (4.) |
Max |
Min |
Max |
Unit |
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Output Voltage |
ª0º Level |
VOL |
5.0 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
Vdc |
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Vin = VDD or 0 |
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10 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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15 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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Vin = 0 or VDD |
ª1º Level |
VOH |
5.0 |
4.95 |
Ð |
4.95 |
5.0 |
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Ð |
4.95 |
Ð |
Vdc |
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10 |
9.95 |
Ð |
9.95 |
10 |
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Ð |
9.95 |
Ð |
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15 |
14.95 |
Ð |
14.95 |
15 |
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Ð |
14.95 |
Ð |
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Input Voltage |
ª0º Level |
VIL |
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Vdc |
(VO = 4.5 or 0.5 Vdc) |
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5.0 |
Ð |
1.5 |
Ð |
2.25 |
1.5 |
Ð |
1.5 |
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(VO = 9.0 or 1.0 Vdc) |
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10 |
Ð |
3.0 |
Ð |
4.50 |
3.0 |
Ð |
3.0 |
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(VO = 13.5 or 1.5 Vdc) |
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15 |
Ð |
4.0 |
Ð |
6.75 |
4.0 |
Ð |
4.0 |
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(VO = 0.5 or 4.5 Vdc) |
ª1º Level |
VIH |
5.0 |
3.5 |
Ð |
3.5 |
2.75 |
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Ð |
3.5 |
Ð |
Vdc |
(VO = 1.0 or 9.0 Vdc) |
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10 |
7.0 |
Ð |
7.0 |
5.50 |
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Ð |
7.0 |
Ð |
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(VO = 1.5 or 13.5 Vdc) |
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15 |
11 |
Ð |
11 |
8.25 |
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Ð |
11 |
Ð |
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Output Drive Current |
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IOH |
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mAdc |
(VOH = 2.5 Vdc) |
Source |
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5.0 |
± 3.0 |
Ð |
± 2.4 |
± 4.2 |
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Ð |
± 1.7 |
Ð |
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(VOH = 4.6 Vdc) |
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5.0 |
± 0.64 |
Ð |
± 0.51 |
± 0.88 |
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Ð |
± 0.36 |
Ð |
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(VOH = 9.5 Vdc) |
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10 |
± 1.6 |
Ð |
± 1.3 |
± 2.25 |
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Ð |
± 0.9 |
Ð |
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(VOH = 13.5 Vdc) |
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15 |
± 4.2 |
Ð |
± 3.4 |
± 8.8 |
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Ð |
± 2.4 |
Ð |
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(VOL = 0.4 Vdc) |
Sink |
IOL |
5.0 |
0.64 |
Ð |
0.51 |
0.88 |
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Ð |
0.36 |
Ð |
mAdc |
(VOL = 0.5 Vdc) |
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10 |
1.6 |
Ð |
1.3 |
2.25 |
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Ð |
0.9 |
Ð |
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(VOL = 1.5 Vdc) |
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15 |
4.2 |
Ð |
3.4 |
8.8 |
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Ð |
2.4 |
Ð |
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Input Current |
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Iin |
15 |
Ð |
± 0.1 |
Ð |
± 0.00001 |
± 0.1 |
Ð |
± 1.0 |
μAdc |
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Input Capacitance |
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Cin |
Ð |
Ð |
Ð |
Ð |
5.0 |
7.5 |
Ð |
Ð |
pF |
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(Vin = 0) |
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Quiescent Current |
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IDD |
5.0 |
Ð |
5.0 |
Ð |
0.005 |
5.0 |
Ð |
150 |
μAdc |
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(Per Package) |
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10 |
Ð |
10 |
Ð |
0.010 |
10 |
Ð |
300 |
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15 |
Ð |
20 |
Ð |
0.015 |
20 |
Ð |
600 |
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Total Supply Current (5.) (6.) |
I |
5.0 |
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I = (0.31 μA/kHz) f + I |
DD |
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μAdc |
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T |
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T |
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(Dynamic plus Quiescent, |
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10 |
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IT = (0.60 μA/kHz) f + IDD |
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Per Package) |
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15 |
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IT = (1.89 μA/kHz) f + IDD |
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(CL = 50 pF on all outputs, all |
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buffers switching) |
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4.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.
5.The formulas given are for the typical characteristics only at 25_C.
6.To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL ± 50) Vfk
where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.001.
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