MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 3-Input •NOR" Gate
Plus Inverter
The MC14000UB dual 3±input NOR gate plus inverter is constructed with MOS P±channel and N±channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired.
•Diode Protection on All Inputs
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Logic Swing Independent of Fanout
•Pin±for±Pin Replacement for CD4000UB
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol |
Parameter |
Value |
|
Unit |
|
|
|
|
|
VDD |
DC Supply Voltage |
± 0.5 to + |
18.0 |
V |
Vin, Vout |
Input or Output Voltage (DC or Transient) |
± 0.5 to VDD + 0.5 |
V |
|
lin, lout |
Input or Output Current (DC or Transient), |
± 10 |
|
mA |
|
per Pin |
|
|
|
|
|
|
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|
PD |
Power Dissipation, per Package² |
500 |
|
mW |
Tstg |
Storage Temperature |
± 65 to + |
150 |
_C |
TL |
Lead Temperature (8±Second Soldering) |
260 |
|
_C |
* Maximum Ratings are those values beyond which damage to the device may occur. ²Temperature Derating:
Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C Ceramic ªLº Packages: ± 12 mW/C From 100_C To 125_C
|
CIRCUIT SCHEMATIC |
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||||
VDD |
14 |
11 |
12 |
13 |
8 |
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3 |
|
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4 |
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9 |
5 |
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VSS |
7 |
6 |
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|
10 |
MC14000UB
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXUBCP |
Plastic |
MC14XXXUBCL |
Ceramic |
MC14XXXUBD |
SOIC |
TA = ± 55° to 125°C for all packages.
|
LOGIC DIAGRAM |
3 |
|
4 |
6 |
5
11
12 
10
13
8 |
9 |
VDD = PIN 14
VSS = PIN 7
PIN ASSIGNMENT
NC |
1 |
14 |
VDD |
NC |
2 |
13 |
IN 3B |
IN 1A |
3 |
12 |
IN 2B |
IN 2A |
4 |
11 |
IN 1B |
IN 3A |
5 |
10 |
OUTB |
OUTA |
6 |
9 |
OUTC |
VSS |
7 |
8 |
IN 1C |
NC = NO CONNECTION
REV 3 1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
|
|
|
VDD |
± 55_C |
|
25_C |
|
+ 125_C |
|
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Characteristic |
|
Symbol |
Vdc |
Min |
Max |
Min |
Typ # |
Max |
Min |
Max |
Unit |
|
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|
Output Voltage |
ª0º Level |
VOL |
5.0 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
Vdc |
Vin = VDD or 0 |
|
|
10 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
|
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|
|
15 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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|
ª1º Level |
VOH |
5.0 |
4.95 |
Ð |
4.95 |
5.0 |
Ð |
4.95 |
Ð |
Vdc |
Vin = 0 or VDD |
|
|
10 |
9.95 |
Ð |
9.95 |
10 |
Ð |
9.95 |
Ð |
|
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|
15 |
14.95 |
Ð |
14.95 |
15 |
Ð |
14.95 |
Ð |
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Input Voltage |
ª0º Level |
VIL |
|
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|
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Vdc |
(VO = 4.5 Vdc) |
|
|
5.0 |
Ð |
1.0 |
Ð |
2.25 |
1.0 |
Ð |
1.0 |
|
(VO = 9.0 Vdc) |
|
|
10 |
Ð |
2.0 |
Ð |
4.50 |
2.0 |
Ð |
2.0 |
|
(VO = 13.5 Vdc) |
|
|
15 |
Ð |
2.5 |
Ð |
6.75 |
2.5 |
Ð |
2.5 |
|
(VO = 0.5 Vdc) |
ª1º Level |
VIH |
5.0 |
4.0 |
Ð |
4.0 |
2.75 |
Ð |
4.0 |
Ð |
Vdc |
|
|
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|||||||||
(VO = 1.0 Vdc) |
|
|
10 |
8.0 |
Ð |
8.0 |
5.50 |
Ð |
8.0 |
Ð |
|
(VO = 1.5 Vdc) |
|
|
15 |
12.5 |
Ð |
12.5 |
8.25 |
Ð |
12.5 |
Ð |
|
Output Drive Current |
|
IOH |
|
|
|
|
|
|
|
|
mAdc |
(VOH = 2.5 Vdc) |
Source |
|
5.0 |
± 1.2 |
Ð |
± 1.0 |
± 1.7 |
Ð |
± 0.7 |
Ð |
|
(VOH = 4.6 Vdc) |
|
|
5.0 |
± 0.25 |
Ð |
± 0.2 |
± 0.36 |
Ð |
± 0.14 |
Ð |
|
(VOH = 9.5 Vdc) |
|
|
10 |
± 0.62 |
Ð |
± 0.5 |
± 0.9 |
Ð |
± 0.35 |
Ð |
|
(VOH = 13.5 Vdc) |
|
|
15 |
± 1.8 |
Ð |
± 1.5 |
± 3.5 |
Ð |
± 1.1 |
Ð |
|
(VOL = 0.4 Vdc) |
Sink |
IOL |
5.0 |
0.64 |
Ð |
0.51 |
0.88 |
Ð |
0.36 |
Ð |
mAdc |
(VOL = 0.5 Vdc) |
|
|
10 |
1.6 |
Ð |
1.3 |
2.25 |
Ð |
0.9 |
Ð |
|
(VOL = 1.5 Vdc) |
|
|
15 |
4.2 |
Ð |
3.4 |
8.8 |
Ð |
2.4 |
Ð |
|
Input Current |
|
Iin |
15 |
Ð |
± 0.1 |
Ð |
± 0.00001 |
± 0.1 |
Ð |
± 1.0 |
μAdc |
Input Capacitance |
|
Cin |
Ð |
Ð |
Ð |
Ð |
5.0 |
7.5 |
Ð |
Ð |
pF |
(Vin = 0) |
|
|
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|
Quiescent Current |
|
IDD |
5.0 |
Ð |
0.25 |
Ð |
0.0005 |
0.25 |
Ð |
7.5 |
μAdc |
(Per Package) |
|
|
10 |
Ð |
0.5 |
Ð |
0.0010 |
0.5 |
Ð |
15 |
|
|
|
|
15 |
Ð |
1.0 |
Ð |
0.0015 |
1.0 |
Ð |
30 |
|
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|
Total Supply Current**² |
|
IT |
5.0 |
|
|
IT = (0.3 μA/kHz) f + IDD/N |
|
|
μAdc |
||
(Dynamic plus Quiescent, |
|
10 |
|
|
IT = (0.6 μA/kHz) f + IDD/N |
|
|
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|||
Per Gate, CL = 50 pF) |
|
|
15 |
|
|
IT = (0.8 μA/kHz) f + IDD/N |
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#Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C.
²T o calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL ± 50) Vfk
where: IT is in μH (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MOTOROLA CMOS LOGIC DATA |
MC14000UB |
|
3 |
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