MC14029B
Binary/Decade Up/Down
Counter
The MC14029B Binary/Decade up/down counter is constructed with MOS P±channel and N±channel enhancement mode devices in a single monolithic structure. The counter consists of type D flip±flop stages with a gating structure to provide toggle flip±flop capability. The counter can be used in either Binary or BCD operation. This complementary MOS counter finds primary use in up/down and difference counting and frequency synthesizer applications where low power dissipation and/or high noise immunity is desired. It is also useful in A/D and D/A conversion and for magnitude and sign generation.
•Diode Protection on All Inputs
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Internally Synchronous for High Speed
•Logic Edge±Clocked Design Ð Count Occurs on Positive Going Edge of Clock
•Asynchronous Preset Enable Operation
•Capable of Driving Two Low±power TTL Loads or One Low±power Schottky TTL Load Over the Rated Temperature Range
•Pin for Pin Replacement for CD4029B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol |
Parameter |
Value |
Unit |
|
|
|
|
VDD |
DC Supply Voltage Range |
± 0.5 to +18.0 |
V |
Vin, Vout |
Input or Output Voltage Range |
± 0.5 to VDD + 0.5 |
V |
|
(DC or Transient) |
|
|
|
|
|
|
Iin, Iout |
Input or Output Current |
± 10 |
mA |
|
(DC or Transient) per Pin |
|
|
|
|
|
|
PD |
Power Dissipation, |
500 |
mW |
|
per Package (Note 3.) |
|
|
|
|
|
|
TA |
Ambient Temperature Range |
± 55 to +125 |
°C |
Tstg |
Storage Temperature Range |
± 65 to +150 |
°C |
TL |
Lead Temperature |
260 |
°C |
|
(8±Second Soldering) |
|
|
|
|
|
|
2.Maximum Ratings are those values beyond which damage to the device may occur.
3.Temperature Derating:
Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
|
|
MARKING |
|
|
DIAGRAMS |
|
|
16 |
|
PDIP±16 |
MC14029BCP |
|
P SUFFIX |
|
|
AWLYYWW |
|
|
CASE 648 |
|
|
|
|
|
|
1 |
|
|
16 |
|
SOIC±16 |
14029B |
|
D SUFFIX |
|
|
AWLYWW |
|
|
CASE 751B |
|
|
|
|
|
|
1 |
|
|
16 |
|
SOEIAJ±16 |
MC14029B |
|
F SUFFIX |
|
|
AWLYWW |
|
|
CASE 966 |
|
|
|
|
|
|
1 |
A |
= Assembly Location |
|
WL or L = Wafer Lot |
|
|
YY or Y |
= Year |
|
WW or W = Work Week |
||
ORDERING INFORMATION |
||
Device |
Package |
Shipping |
MC14029BCP |
PDIP±16 |
2000/Box |
MC14029BD |
SOIC±16 |
2400/Box |
MC14029BDR2 |
SOIC±16 |
2500/Tape & Reel |
MC14029BF |
SOEIAJ±16 |
See Note 1. |
MC14029BFEL |
SOEIAJ±16 |
See Note 1. |
1.For ordering information on the EIAJ version of the SOIC packages, please contact your local
ON Semiconductor representative.
Semiconductor Components Industries, LLC, 2000 |
1 |
Publication Order Number: |
March, 2000 ± Rev. 3 |
|
MC14029B/D |
MC14029B
PIN ASSIGNMENT
|
|
|
TRUTH TABLE |
|
|
|
PE |
|
1 |
16 |
VDD |
|||
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
Q3 |
|
2 |
15 |
CLK |
||
|
|
|
|
Preset |
|
|
|
P3 |
|
3 |
14 |
Q2 |
||
|
|
|
|
Enable |
|
|
|
|
||||||
|
Carry In |
Up/Down |
Action |
|||||||||||
|
|
|
P0 |
|
4 |
13 |
P2 |
|||||||
1 |
|
X |
0 |
No Count |
|
|
|
|||||||
|
|
|
|
|
|
|
5 |
12 |
P1 |
|||||
|
|
|
|
|
|
|
|
|
|
|||||
0 |
|
1 |
0 |
Count Up |
|
|
Cin |
|
|
|||||
|
|
|
|
|
||||||||||
0 |
|
0 |
0 |
Count Down |
|
|
Q0 |
|
6 |
11 |
Q1 |
|||
|
|
|
|
|
|
|
7 |
10 |
U/D |
|||||
|
|
|
|
|
|
|
|
|
|
|
||||
|
X |
X |
1 |
Preset |
|
Cout |
|
|
|
|||||
|
|
|
|
|
||||||||||
X = Don't Care |
|
|
|
|
VSS |
|
8 |
9 |
B/D |
|||||
|
|
|
|
|
||||||||||
|
|
|
|
|
||||||||||
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
|
|
|
VDD |
± 55_C |
|
25_C |
|
|
125_C |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
Characteristic |
|
Symbol |
Vdc |
Min |
Max |
Min |
Typ (4.) |
Max |
Min |
Max |
Unit |
|
Output Voltage |
ª0º Level |
VOL |
5.0 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
Vdc |
|
Vin = VDD or 0 |
|
|
10 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
|
|
|
|
|
15 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ª1º Level |
VOH |
5.0 |
4.95 |
Ð |
4.95 |
5.0 |
Ð |
4.95 |
Ð |
Vdc |
|
Vin = 0 or VDD |
|
|
10 |
9.95 |
Ð |
9.95 |
10 |
Ð |
9.95 |
Ð |
|
|
|
|
|
15 |
14.95 |
Ð |
14.95 |
15 |
Ð |
14.95 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Input Voltage |
ª0º Level |
VIL |
|
|
|
|
|
|
|
|
|
Vdc |
(VO = 4.5 or 0.5 Vdc) |
|
|
5.0 |
Ð |
1.5 |
Ð |
2.25 |
1.5 |
Ð |
1.5 |
|
|
(VO = 9.0 or 1.0 Vdc) |
|
|
10 |
Ð |
3.0 |
Ð |
4.50 |
3.0 |
Ð |
3.0 |
|
|
(VO = 13.5 or 1.5 Vdc) |
|
|
15 |
Ð |
4.0 |
Ð |
6.75 |
4.0 |
Ð |
4.0 |
|
|
(VO = 0.5 or 4.5 Vdc) |
ª1º Level |
VIH |
5.0 |
3.5 |
Ð |
3.5 |
2.75 |
Ð |
3.5 |
Ð |
Vdc |
|
|
|
|
||||||||||
(VO = 1.0 or 9.0 Vdc) |
|
|
10 |
7.0 |
Ð |
7.0 |
5.50 |
Ð |
7.0 |
Ð |
|
|
(VO = 1.5 or 13.5 Vdc) |
|
|
15 |
11 |
Ð |
11 |
8.25 |
Ð |
11 |
Ð |
|
|
Output Drive Current |
|
IOH |
|
|
|
|
|
|
|
|
|
mAdc |
(VOH = 2.5 Vdc) |
Source |
|
5.0 |
± 3.0 |
Ð |
± 2.4 |
± 4.2 |
Ð |
± 1.7 |
Ð |
|
|
(VOH = 4.6 Vdc) |
|
|
5.0 |
± 0.64 |
Ð |
± 0.51 |
± 0.88 |
Ð |
± 0.36 |
Ð |
|
|
(VOH = 9.5 Vdc) |
|
|
10 |
± 1.6 |
Ð |
± 1.3 |
± 2.25 |
Ð |
± 0.9 |
Ð |
|
|
(VOH = 13.5 Vdc) |
|
|
15 |
± 4.2 |
Ð |
± 3.4 |
± 8.8 |
Ð |
± 2.4 |
Ð |
|
|
(VOL = 0.4 Vdc) |
Sink |
IOL |
5.0 |
0.64 |
Ð |
0.51 |
0.88 |
Ð |
0.36 |
Ð |
mAdc |
|
(VOL = 0.5 Vdc) |
|
|
10 |
1.6 |
Ð |
1.3 |
2.25 |
Ð |
0.9 |
Ð |
|
|
(VOL = 1.5 Vdc) |
|
|
15 |
4.2 |
Ð |
3.4 |
8.8 |
Ð |
2.4 |
Ð |
|
|
Input Current |
|
Iin |
15 |
Ð |
± 0.1 |
Ð |
± 0.00001 |
± 0.1 |
Ð |
± 1.0 |
μAdc |
|
Input Capacitance |
|
Cin |
Ð |
Ð |
Ð |
Ð |
5.0 |
7.5 |
Ð |
Ð |
pF |
|
(Vin = 0) |
|
|
|
|
|
|
|
|
|
|
|
|
Quiescent Current |
|
IDD |
5.0 |
Ð |
5.0 |
Ð |
0.005 |
5.0 |
Ð |
150 |
μAdc |
|
(Per Package) |
|
|
10 |
Ð |
10 |
Ð |
0.010 |
10 |
Ð |
300 |
|
|
|
|
|
15 |
Ð |
20 |
Ð |
0.015 |
20 |
Ð |
600 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Total Supply Current (5.) (6.) |
I |
5.0 |
|
|
I = (0.58 μA/kHz) f + I |
DD |
|
|
μAdc |
|||
|
|
T |
|
|
|
T |
|
|
|
|
|
|
(Dynamic plus Quiescent, |
|
10 |
|
|
IT = (1.20 μA/kHz) f + IDD |
|
|
|
||||
Per Package) |
|
|
15 |
|
|
IT = (1.70 μA/kHz) f + IDD |
|
|
|
|||
(CL = 50 pF on all outputs, all |
|
|
|
|
|
|
|
|
|
|
|
|
buffers switching) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
4.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.
5.The formulas given are for the typical characteristics only at 25_C.
6.To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL ± 50) Vfk
where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.001.
http://onsemi.com
2
MC14029B
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
All Types |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
Characteristic |
Symbol |
V |
Min |
Typ (8.) |
Max |
Unit |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DD |
|
|
|
|
|
Output Rise and Fall Time |
tTLH, |
|
|
|
|
ns |
|||||||||||
|
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns |
tTHL |
5.0 |
Ð |
100 |
200 |
|
|||||||||||
|
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns |
|
|
|
10 |
Ð |
50 |
100 |
|
|||||||||
|
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns |
|
|
|
15 |
Ð |
40 |
80 |
|
|||||||||
|
Propagation Delay Time |
tPLH, |
|
|
|
|
ns |
|||||||||||
|
Clk to Q |
tPHL |
|
|
|
|
|
|||||||||||
|
|
|
|
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns |
|
|
|
5.0 |
Ð |
200 |
400 |
|
||||||
|
|
|
|
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns |
|
|
|
10 |
Ð |
100 |
200 |
|
||||||
|
|
|
|
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns |
|
|
|
15 |
Ð |
90 |
180 |
|
||||||
|
Clk to |
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
tPLH, |
|
|
|
|
ns |
||||||||
Cout |
|
|
|
|
||||||||||||||
|
|
|
|
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns |
tPHL |
5.0 |
Ð |
250 |
500 |
|
||||||||
|
|
|
|
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns |
|
|
|
10 |
Ð |
130 |
260 |
|
||||||
|
|
|
|
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns |
|
|
|
15 |
Ð |
85 |
190 |
|
||||||
|
|
|
|
to |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
t |
|
, |
|
|
|
|
ns |
|||
Cin |
Cout |
|
|
|
|
|
||||||||||||
|
|
|
|
tPLH, tPHL = (1.7 ns/pF) CL + 95 ns |
PLH |
|
|
|
|
|
|
|||||||
|
|
|
|
t |
PHL |
5.0 |
Ð |
175 |
360 |
|
||||||||
|
|
|
|
tPLH, tPHL = (0.66 ns/pF) CL + 47 ns |
|
10 |
Ð |
50 |
120 |
|
||||||||
|
|
|
|
|
|
|
|
|||||||||||
|
|
|
|
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns |
|
|
|
15 |
Ð |
50 |
100 |
|
||||||
|
PE to Q |
|
|
|
|
|
|
|||||||||||
|
tPLH, |
|
|
|
|
ns |
||||||||||||
|
|
|
|
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns |
t |
PHL |
5.0 |
Ð |
235 |
470 |
|
|||||||
|
|
|
|
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns |
|
10 |
Ð |
100 |
200 |
|
||||||||
|
|
|
|
|
|
|
|
|||||||||||
|
|
|
|
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns |
|
|
|
15 |
Ð |
80 |
160 |
|
||||||
|
PE to |
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
Cout |
t |
|
, |
|
|
|
|
ns |
||||||||||
|
|
|
|
tPLH, tPHL = (1. 7 ns/pF) CL + 465 ns |
PLH |
|
|
|
|
|
|
|||||||
|
|
|
|
t |
PHL |
5.0 |
Ð |
320 |
640 |
|
||||||||
|
|
|
|
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns |
|
10 |
Ð |
145 |
290 |
|
||||||||
|
|
|
|
|
|
|
|
|||||||||||
|
|
|
|
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns |
|
|
|
15 |
Ð |
105 |
210 |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
Clock Pulse Width |
tW(cl) |
5.0 |
180 |
90 |
Ð |
ns |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
10 |
80 |
40 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
15 |
60 |
30 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
Clock Pulse Frequency |
|
fcl |
|
5.0 |
Ð |
4.0 |
2.0 |
MHz |
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
10 |
Ð |
8.0 |
4.0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
15 |
Ð |
10 |
5.0 |
|
|
|
|
|
|
|
|
|
|
||||||||||
|
Preset Removal Time |
trem |
5.0 |
160 |
80 |
Ð |
ns |
|||||||||||
|
The Preset Signal must be low prior to a positive±going |
|
|
|
10 |
80 |
40 |
Ð |
|
|||||||||
|
transition of the clock. |
|
|
|
15 |
60 |
30 |
Ð |
|
|||||||||
|
|
|
|
|
|
|
|
|
||||||||||
|
Clock Rise and Fall Time |
tr(cl) |
5.0 |
Ð |
Ð |
15 |
μs |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
tf(cl) |
10 |
Ð |
Ð |
5 |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1 5 |
Ð |
Ð |
4 |
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
In Setup Time |
|
tsu |
|
5.0 |
150 |
75 |
Ð |
ns |
|||||||
|
Carry |
|
|
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
10 |
60 |
30 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
15 |
40 |
20 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
Up/Down Setup Time |
|
|
|
5.0 |
340 |
170 |
Ð |
ns |
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
10 |
140 |
70 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
15 |
100 |
50 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
Binary/Decade Setup Time |
|
|
|
5.0 |
320 |
160 |
Ð |
ns |
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
10 |
140 |
70 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
15 |
100 |
50 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
Preset Enable Pulse Width |
|
tW |
|
5.0 |
130 |
65 |
Ð |
ns |
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
10 |
70 |
35 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
15 |
50 |
25 |
Ð |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
7.The formulas given are for the typical characteristics only at 25_C.
8.Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.
http://onsemi.com
3
Loading...