MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad TTL/NMOS to PECL* |
MC10H351 |
|
Translator |
||
|
The MC10H351 is a quad translator for interfacing data between a saturated logic section and the PECL section of digital systems when only a +5.0 Vdc power supply is available. The MC10H351 has TTL/NMOS compatible inputs and PECL complementary open±emitter outputs that allow use as an inverting/non±inverting translator or as a differential line driver. When the common strobe input is at a low logic level, it forces all true outputs to the PECL low logic state (≈ +3.2 V) and all inverting outputs to the PECL high logic state (≈ +4.1 V).
The MC10H351 can also be used with the MC10H350 to transmit and receive TTL/NMOS information differentially via balanced twisted pair lines.
•Single +5.0 Power Supply
•All VCC Pins Isolated On Chip
•Differentially Drive Balanced Lines
•tpd = 1.3 nsec Typical
MAXIMUM RATINGS
Characteristic |
|
|
|
|
Symbol |
|
|
|
Rating |
|
|
Unit |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Power Supply |
|
|
|
|
|
|
VCC |
|
|
0 to +7.0 |
|
|
Vdc |
|||
Input Voltage (VCC = 5.0 V) |
|
|
|
|
|
VI |
|
|
0 to VCC |
|
|
Vdc |
||||
Output Current Ð Continuous |
|
|
|
|
|
Iout |
|
|
50 |
|
|
|
mA |
|||
Ð Surge |
|
|
|
|
|
|
|
|
|
100 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Operating Temperature Range |
|
|
|
|
|
TA |
|
|
0 to +75 |
|
|
°C |
||||
Storage Temperature Range Ð Plastic |
|
|
|
Tstg |
|
±55 to +150 |
|
|
°C |
|||||||
|
Ð Ceramic |
|
|
|
|
|
±55 to +165 |
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|||||
ELECTRICAL CHARACTERISTICS (VCC = VCC1 = VCC2 = 5.0 V ± 5.0%) |
||||||||||||||||
|
|
0° |
|
|
|
25° |
|
|
75° |
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
Characteristic |
Symbol |
Min |
|
Max |
|
Min |
Max |
|
Min |
|
Max |
|
Unit |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
Power Supply |
ECL |
Ð |
|
50 |
|
Ð |
45 |
|
Ð |
|
50 |
|
mA |
|||
Current |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TTL |
Ð |
|
20 |
|
Ð |
15 |
|
Ð |
|
20 |
|
mA |
||||
|
|
|
|
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Reverse Current |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
μA |
Pins 7, 8, 12, 14 |
IR |
Ð |
|
25 |
|
Ð |
20 |
|
Ð |
|
25 |
|
|
|||
Pin 9 |
IINH |
Ð |
|
100 |
|
Ð |
80 |
|
Ð |
|
100 |
|
|
|||
Forward Current |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mA |
Pins 7, 8, 12, 14 |
IF |
Ð |
|
±0.8 |
|
Ð |
±0.6 |
|
Ð |
|
±0.8 |
|
|
|||
Pin 9 |
IINL |
Ð |
|
±3.2 |
|
Ð |
±2.4 |
|
Ð |
|
±3.2 |
|
|
|||
Input Breakdown |
V(BR)in |
5.5 |
|
Ð |
|
5.5 |
Ð |
|
5.5 |
|
Ð |
|
|
Vdc |
||
Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
Input Clamp Voltage |
VI |
Ð |
|
±1.5 |
|
Ð |
±1.5 |
|
Ð |
|
±1.5 |
|
Vdc |
|||
(Iin = ±18 mA) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
High Output |
VOH |
3.98 |
|
4.16 |
|
4.02 |
4.19 |
|
4.08 |
|
4.27 |
|
Vdc |
|||
Voltage (1) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
Low Output |
VOL |
3.05 |
|
3.37 |
|
3.05 |
3.37 |
|
3.05 |
|
3.37 |
|
Vdc |
|||
Voltage (1) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
High Input Voltage |
VIH |
2.0 |
|
Ð |
|
2.0 |
Ð |
|
2.0 |
|
Ð |
|
|
Vdc |
||
Low Input Voltage |
VIL |
Ð |
|
0.8 |
|
Ð |
0.8 |
|
Ð |
|
0.8 |
|
Vdc |
|||
(1) With VCC at 5.0 V. VOH/VOL change 1:1 with VCC. *Positive Emitter Coupled Logic
L SUFFIX
CERAMIC PACKAGE
CASE 732±03
P SUFFIX
PLASTIC PACKAGE
CASE 738±03
FN SUFFIX
PLCC
CASE 775±02
LOGIC DIAGRAM
B IN |
7 |
1 |
B OUT |
|
|
2 |
B OUT |
A IN |
8 |
5 |
A OUT |
|
|
4 |
A OUT |
D IN |
12 |
16 |
D OUT |
|
|
17 |
D OUT |
C IN |
14 |
19 |
C OUT |
COMMON |
9 |
18 |
C OUT |
STROBE |
|
|
|
VCC (+5.0 VDC) = PINS 6, 11, 15, 20
GND = PIN 10
DIP
PIN ASSIGNMENT
|
|
|
|
|
|
|
|
|
|
|
|
B OUT |
|
1 |
|
20 |
|
|
ECL VCC |
||
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
B OUT |
|
2 |
|
19 |
|
|
C OUT |
||
|
|
|
|
|
||||||
|
N.C. |
|
3 |
|
18 |
|
|
C OUT |
||
|
|
|
|
|
||||||
|
A OUT |
|
4 |
|
17 |
|
|
D OUT |
||
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
A OUT |
|
5 |
|
16 |
|
|
D OUT |
||
|
|
|
|
|
||||||
|
VCC |
|
6 |
|
15 |
|
|
VCC 2 |
||
|
|
|
|
|
||||||
|
B IN |
|
7 |
|
14 |
|
|
C IN |
||
|
|
|
|
|
||||||
|
A IN |
|
8 |
|
13 |
|
|
N.C. |
||
|
|
|
|
|
||||||
COMMON |
|
9 |
|
12 |
|
|
D IN |
|||
|
|
|
|
|||||||
STROBE |
|
|
|
|
||||||
|
|
|
|
|
|
TTL VCC |
||||
|
GND |
|
10 |
|
11 |
|
|
|||
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±36 of the Motorola MECL Data Book (DL122/D).
3/93
Motorola, Inc. 1996 |
2±77 |
REV 5 |
MC10H351
AC PARAMETERS
|
|
|
0° |
|
25° |
|
75° |
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
Characteristic |
Symbol |
Min |
|
Max |
Min |
|
Max |
Min |
|
Max |
Unit |
|
|
|
|
|
|
|
|
|
|
|
|
Propagation Delay (1) |
tpd |
0.4 |
|
2.2 |
0.4 |
|
2.2 |
0.4 |
|
2.1 |
ns |
Rise Time (20% to 80%) |
tr |
0.4 |
|
1.9 |
0.4 |
|
2.0 |
0.4 |
|
2.1 |
ns |
Fall Time (80% to 20%) |
tf |
0.4 |
|
1.9 |
0.4 |
|
2.0 |
0.4 |
|
2.1 |
ns |
Maximum Operating Frequency |
fmax |
150 |
|
Ð |
150 |
|
Ð |
150 |
|
Ð |
MHz |
(1) Propagation delay is measured on this circuit from +1.5 volts on the input waveform to the 50% point on the output waveform.
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Outputs are terminated through a 50±ohm resistor to VCC ±2.0 Vdc.
MOTOROLA |
2±78 |
MECL Data |
|
|
DL122 Ð Rev 6 |
Loading...