Fairchild Semiconductor DM74ALS174SJX, DM74ALS174SJ, DM74ALS174N, DM74ALS174MX, DM74ALS174M Datasheet

September 1986

Revised February 2000

DM74ALS174 • DM74ALS175

Hex/Quad D-Type Flip-Flops with Clear

General Description

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchronous clear input, and the quad (DM74ALS175) version features complementary outputs from each flip-flop.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

Features

■Advanced oxide-isolated ion-implanted Schottky TTL process

■Pin and functional compatible with LS family counterpart

■Typical clock frequency maximum is 80 MHz

■Switching performance guaranteed over full temperature and VCC supply range

Ordering Code:

Ordering Code	Package Number	Package Description
DM74ALS174M	M16A	16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS174SJ	M16D	16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS174N	N16E	16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74ALS175M	M16A	16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS175SJ	M16D	16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS175N	N16E	16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

DM74ALS174 DM74ALS175

Clear with Flops-Flip Type-D Hex/Quad DM74ALS175 • DM74ALS174

© 2000 Fairchild Semiconductor Corporation

DS006112

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DM74ALS174 • DM74ALS175

Function Table

	Inputs			Outputs
Clear	Clock	D	Q		Q (Note 1)
L	X	X	L				H
H	−	H	H				L
H	−	L	L				H
H	L	X	Q0
							Q	0

H = HIGH Level (steady state) L = LOW Level (steady state) X = Don’t Care

− = Transition from LOW-to-HIGH Level

Q0 = the level of Q before the indicated steady-state input conditions were established

Note 1: applies to DM74ALS175 only

Logic Diagrams

DM74ALS174

DM74ALS175

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2

Absolute Maximum Ratings(Note 2)

Supply Voltage	7V
Input Voltage	7V
Operating Free Air Temperature Range	0°C to +70°C
Storage Temperature Range	−65°C to +150°C
Typical θJA
N Package	77.9°C/W
M Package	107.3°C/W

Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol	Parameter					Min	Nom	Max	Units
VCC	Supply Voltage					4.5	5	5.5	V
VIH	HIGH Level Input Voltage					2			V
VIL	LOW Level Input Voltage							0.8	V
IOH	HIGH Level Output Current							−0.4	mA
IOL	LOW Level Output Current							8	mA
tW	Pulse Width	Clock				10
			HIGH or LOW						ns
					LOW	10
			Clear
tSETUP	Setup Time (Note 3)		Data Input			10−
									ns
			Clear			6−
			Inactive State
tHOLD	Data Hold Time (Note 3)					0−			ns
fCLOCK	Clock Frequency					0		50	MHz
TA	Free Air Operating Temperature					0		70	°C

Note 3: The symbol − indicates that the rising edge of the clock is used as reference.

DM74ALS175 • DM74ALS174

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