WS512K32-XXX
512Kx32 SRAM MODULE, SMD 5962-94611
FEATURES
νAccess Times of 15*, 17, 20, 25, 35, 45, 55ns
νPackaging
•66 pin, PGA Type, 1.075" square, Hermetic Ceramic HIP (Package 400).
•68 lead, 40mm Hermetic Low Profile CQFP, 3.5mm (0.140") (Package 502)1, Package to be developed.
•68 lead, Hermetic CQFP (G2T)1, 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3).
•68 lead, Hermetic CQFP (G1U), 23.9mm (0.940") square (Package 519) 3.57mm (0.140") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3).
•68 lead, Hermetic CQFP (G1U), 23.9mm (0.940") square (Package 524) 4.06mm (0.160") height.
νOrganized as 512Kx32, User Configurable as 1Mx16 or 2Mx8
νCommercial, Industrial and Military Temperature Ranges
νTTL Compatible Inputs and Outputs
ν5 Volt Power Supply
νLow Power CMOS
νBuilt-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation
νWeight
WS512K32-XH1X - 13 grams typical WS512K32-XG2TX1 - 8 grams typical WS512K32-XG1UX - 5 grams typical WS512K32-XG1TX - 5 grams typical WS512K32-XG4TX1 - 20 grams typical
* 15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.
Note 1: Package Not Recommended For New Design
FIG. 1 PIN CONFIGURATION FOR WS512K32N-XH1X |
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TOP VIEW |
PIN DESCRIPTION |
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I/O0-31 |
Data Inputs/Outputs |
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A0-18 |
Address Inputs |
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WE1-4 Write Enables |
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CS1-4 |
Chip Selects |
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OE |
Output Enable |
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VCC |
Power Supply |
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GND |
Ground |
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NC |
Not Connected |
BLOCK DIAGRAM
November 2001 Rev. 9 |
1 |
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com |
WS512K32-XXX
FIG. 2 PIN CONFIGURATION FOR WS512K32-XG4TX1 |
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TOP VIEW |
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PIN DESCRIPTION |
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I/O0-31 |
Data Inputs/Outputs |
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A0-18 |
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Address Inputs |
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WE |
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Write Enables |
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1-4 |
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Chip Selects |
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CS |
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OE |
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Output Enable |
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VCC |
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Power Supply |
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GND |
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Ground |
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NC |
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Not Connected |
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BLOCK DIAGRAM |
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Note 1: Package Not Recommended For New Design
FIG. 3 PIN CONFIGURATION FOR WS512K32-XG2TX1, WS512K32-XG1TX
AND WS512K32-XG1UX
TOP VIEW
The White 68 lead CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the CQFJ has the TCE and lead inspection advantage of the CQFP form.
PIN DESCRIPTION
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I/O0-31 |
Data Inputs/Outputs |
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A0-18 |
Address Inputs |
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1-4 |
Write Enables |
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WE |
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1-4 |
Chip Selects |
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CS |
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Output Enable |
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OE |
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VCC |
Power Supply |
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GND |
Ground |
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NC |
Not Connected |
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BLOCK DIAGRAM
Note 1: Package Not Recommended For New Design
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com |
2 |
WS512K32-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter |
Symbol |
Min |
Max |
Unit |
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Operating Temperature |
TA |
-55 |
+125 |
°C |
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Storage Temperature |
TSTG |
-65 |
+150 |
°C |
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Signal Voltage Relative to GND |
VG |
-0.5 |
Vcc+0.5 |
V |
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Junction Temperature |
TJ |
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150 |
°C |
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Supply Voltage |
VCC |
-0.5 |
7.0 |
V |
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RECOMMENDED OPERATING CONDITIONS
Parameter |
Symbol |
Min |
Max |
Unit |
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Supply Voltage |
VCC |
4.5 |
5.5 |
V |
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Input High Voltage |
VIH |
2.2 |
VCC + 0.3 |
V |
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Input Low Voltage |
VIL |
-0.5 |
+0.8 |
V |
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Operating Temp (Mil) |
TA |
-55 |
+125 |
°C |
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TRUTH TABLE
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Mode |
Data I/O |
Power |
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CS |
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OE |
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WE |
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H |
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X |
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X |
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Standby |
High Z |
Standby |
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L |
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L |
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H |
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Read |
Data Out |
Active |
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L |
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H |
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H |
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Out Disable |
High Z |
Active |
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L |
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X |
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L |
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W r i t e |
Data In |
Active |
CAPACITANCE
(TA = +25°C)
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Parameter |
Symbol |
Conditions |
Max |
Unit |
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capacitance |
COE |
VIN = 0 V, f = 1.0 MHz |
50 |
pF |
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OE |
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1-4 capacitance |
CWE |
VIN = 0 V, f = 1.0 MHz |
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pF |
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WE |
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HIP (PGA) |
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2 0 |
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CQFP G4T |
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5 0 |
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CQFPG2T/G1U/G1T |
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20 |
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CCS |
VIN = 0 V, f = 1.0 MHz |
20 |
pF |
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CS |
1-4 capacitance |
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Data I/O capacitance |
CI/O |
VI/O = 0 V, f = 1.0 MHz |
20 |
pF |
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Addressinputcapacitance |
CAD |
VIN = 0 V, f = 1.0 MHz |
50 |
pF |
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This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter |
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Symbol |
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Conditions |
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Units |
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Min |
Max |
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Input Leakage Current |
ILI |
VCC = 5.5, VIN = GND to VCC |
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1 0 |
µA |
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Output Leakage Current |
ILO |
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= VIH, |
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= VIH, VOUT = GND to VCC |
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1 0 |
µA |
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CS |
OE |
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Operating Supply Current x 32 Mode |
ICC x 32 |
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= VIL, |
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= VIH, f = 5MHz, Vcc = 5.5 |
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660 |
m A |
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CS |
OE |
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Standby Current |
ISB |
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= VIH, |
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= VIH, f = 5MHz, Vcc = 5.5 |
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8 0 |
m A |
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CS |
OE |
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Output |
Low |
Voltage |
VOL |
IOL = 8mA for 15 - 35ns, |
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0.4 |
V |
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IOL = 2.1mA for 45 - 55ns, Vcc = 4.5 |
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Output |
High |
Voltage |
VOH |
IOH = -4.0mA for 15 - 35ns, |
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2.4 |
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V |
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IOH = -1.0mA for 45 - 55ns, |
Vcc = 4.5 |
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NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
DATA RETENTION CHARACTERISTICS
(TA = -55°C to +125°C)
Parameter |
Symbol |
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Conditions |
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Units |
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Min |
Max |
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Data Retention Supply Voltage |
VDR |
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£ VCC -0.2V |
2.0 |
5.5 |
V |
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CS |
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Data Retention Current |
ICCDR1 |
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VCC = 3V |
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28 |
mA |
Low Power Data Retention |
ICCDR2 |
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VCC = 3V |
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16 |
mA |
Current (WS512K32L-XXX) |
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3 |
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com |
WS512K32-XXX
AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter |
Symbol |
- 1 5 * |
-17 |
-20 |
-25 |
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-35 |
-45 |
-55 |
Units |
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Read Cycle |
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Min Max |
Min Max |
Min Max |
Min Max |
Min |
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Max |
Min Max |
Min Max |
|
||||||
Read Cycle Time |
tRC |
1 5 |
|
1 7 |
|
2 0 |
|
2 5 |
|
3 5 |
|
|
4 5 |
|
5 5 |
|
n s |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address Access Time |
tAA |
|
1 5 |
|
1 7 |
|
2 0 |
|
2 5 |
|
|
3 5 |
|
4 5 |
|
5 5 |
n s |
Output Hold from Address Change |
tOH |
0 |
|
0 |
|
0 |
|
0 |
|
0 |
|
|
0 |
|
0 |
|
n s |
Chip Select Access Time |
tACS |
|
1 5 |
|
1 7 |
|
2 0 |
|
2 5 |
|
|
3 5 |
|
4 5 |
|
5 5 |
n s |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Output Enable to Output Valid |
tOE |
|
8 |
|
9 |
|
1 0 |
|
1 2 |
|
|
2 5 |
|
2 5 |
|
2 5 |
n s |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Chip Select to Output in Low Z |
tCLZ1 |
2 |
|
2 |
|
2 |
|
2 |
|
4 |
|
|
4 |
|
4 |
|
n s |
Output Enable to Output in Low Z |
tOLZ1 |
0 |
|
0 |
|
0 |
|
0 |
|
0 |
|
|
0 |
|
0 |
|
n s |
Chip Disable to Output in High Z |
tCHZ1 |
|
1 2 |
|
1 2 |
|
1 2 |
|
1 2 |
|
|
1 5 |
|
2 0 |
|
2 0 |
n s |
Output Disable to Output in High Z |
tOHZ1 |
|
1 2 |
|
1 2 |
|
1 2 |
|
1 2 |
|
|
1 5 |
|
2 0 |
|
2 0 |
n s |
* 15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice. 1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter |
|
Symbol |
-15* |
-17 |
-20 |
-25 |
-35 |
-45 |
-55 |
Units |
||||||||
Write Cycle |
|
|
Min Max |
Min Max |
Min Max |
Min Max |
Min Max |
Min Max |
Min Max |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Write Cycle Time |
t WC |
1 5 |
|
1 7 |
|
2 0 |
|
2 5 |
|
3 5 |
|
4 5 |
|
5 5 |
|
n s |
||
Chip Select to End of Write |
t CW |
1 3 |
|
1 5 |
|
1 5 |
|
1 7 |
|
2 5 |
|
3 5 |
|
5 0 |
|
n s |
||
Address Valid to End of Write |
t AW |
1 3 |
|
1 5 |
|
1 5 |
|
1 7 |
|
2 5 |
|
3 5 |
|
5 0 |
|
n s |
||
Data Valid to End of Write |
t DW |
1 0 |
|
1 1 |
|
1 2 |
|
1 3 |
|
2 0 |
|
2 5 |
|
2 5 |
|
n s |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Write Pulse Width |
t WP |
1 3 |
|
1 5 |
|
1 5 |
|
1 7 |
|
2 5 |
|
3 5 |
|
4 0 |
|
n s |
||
Address |
Setup |
Time |
t AS |
2 |
|
2 |
|
2 |
|
2 |
|
2 |
|
2 |
|
2 |
|
n s |
Address |
Hold |
Time |
t AH |
0 |
|
0 |
|
0 |
|
0 |
|
0 |
|
5 |
|
5 |
|
n s |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Output Active from End of Write |
t OW1 |
2 |
|
2 |
|
3 |
|
4 |
|
4 |
|
5 |
|
5 |
|
n s |
||
Write Enable to Output in High Z |
t WHZ 1 |
|
8 |
|
9 |
|
1 1 |
|
1 3 |
|
1 5 |
|
2 0 |
|
2 0 |
n s |
||
Data Hold Time |
t DH |
0 |
|
0 |
|
0 |
|
0 |
|
0 |
|
0 |
|
0 |
|
n s |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
* |
15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice. |
|
1. |
This parameter is guaranteed by design but |
not tested. |
2 . |
The Address Setup Time of minimum 2ns is |
for the G2T, G1U and H1 packages. tAS minimum for the G4T package is 0ns. |
FIG. 4
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter |
|
Typ |
Unit |
|
|
|
|
|
|
Input |
Pulse Levels |
VIL = 0, VIH = 3.0 |
V |
|
|
|
|
|
|
Input |
Rise and |
Fall |
5 |
n s |
|
|
|
||
Input and Output Reference Level |
1 . 5 |
V |
||
|
|
|
|
|
Output Timing |
Reference Level |
1 . 5 |
V |
|
|
|
|
|
|
N O T E S :
VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 ý.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com |
4 |