NSC DP8422AVX-25, DP8422AVX-20, DP8422AV-25, DP8422AV-20, DP8422ATVX-25 Datasheet

July 1992

DP8420A/21A/22A microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers

General Description

The DP8420A/21A/22A dynamic RAM controllers provide a low cost, single chip interface between dynamic RAM and all 8-, 16and 32-bit systems. The DP8420A/21A/22A generate all the required access control signal timing for DRAMs. An on-chip refresh request clock is used to automatically refresh the DRAM array. Refreshes and accesses

are arbitrated on chip. If necessary, a WAIT or DTACK output inserts wait states into system access cycles, including

burst mode accesses. RAS low time during refreshes and RAS precharge time after refreshes and back to back accesses are guaranteed through the insertion of wait states. Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of precharge. An additional feature of the DP8422A is two access ports to simplify dual accessing. Arbitration among these ports and refresh is done on chip.

Features

Y On chip high precision delay line to guarantee critical DRAM access timing parameters

YmicroCMOS process for low power

YHigh capacitance drivers for RAS, CAS, WE and DRAM address on chip

YOn chip support for nibble, page and static column DRAMs

YByte enable signals on chip allow byte writing in a word size up to 32 bits with no external logic

YSelection of controller speeds: 20 MHz and 25 MHz

YOn board Port A/Port B (DP8422A only)/refresh arbitration logic

YDirect interface to all major microprocessors (application notes available)

Y4 RAS and 4 CAS drivers (the RAS and CAS configuration is programmable)

		Ý of Pins	Ý of Address	Largest	Direct Drive	Access
	Control			DRAM	Memory	Ports
		(PLCC)	Outputs
				Possible	Capacity	Available
	DP8420A	68	9	256 kbit	4 Mbytes	Single Access Port
	DP8421A	68	10	1 Mbit	16 Mbytes	Single Access Port
	DP8422A	84	11	4 Mbit	64 Mbytes	Dual Access Ports (A and B)

Block Diagram

DP8420A/21A/22A DRAM Controller

TL/F/8588 ± 5

FIGURE 1

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

Staggered RefreshTM is a trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation

TL/F/8588

RRD-B30M105/Printed in U. S. A.

Controller/Drivers RAM Dynamic 256k/1M/4M Programmable microCMOS DP8420A/21A/22A

Table of Contents

1.0 INTRODUCTION

2.0SIGNAL DESCRIPTIONS

2.1Address, R/W and Programming Signals

2.2DRAM Control Signals

2.3Refresh Signals

2.4Port A Access Signals

2.5Port B Access Signals (DP8422A)

2.6Common Dual Port Signals (DP8422A)

2.7Power Signals and Capacitor Input

2.8Clock Inputs

3.0PROGRAMMING AND RESETTING

3.1External Reset

3.2Programming Methods

3.2.1Mode Load Only Programming

3.2.2Chip Selected Access Programming

3.3Internal Programming Modes

4.0PORT A ACCESS MODES

4.1Access Mode 0

4.2Access Mode 1

4.3Extending CAS with Either Access Mode

4.4Read-Modify-Write Cycles with Either Access Mode

4.5Additional Access Support Features

4.5.1Address Latches and Column Increment

4.5.2Address Pipelining

4.5.3Delay CAS During Write Accesses

5.0REFRESH OPTIONS

5.1Refresh Control Modes

5.1.1Automatic Internal Refresh

5.1.2Externally Controlled/Burst Refresh

5.1.3Refresh Request/Acknowledge

5.2Refresh Cycle Types

5.2.1Conventional Refresh

5.2.2Staggered RefreshTM

5.2.3Error Scrubbing Refresh

5.3Extending Refresh

5.4Clearing the Refresh Address Counter

5.5Clearing the Refresh Request Clock

6.0PORT A WAIT STATE SUPPORT

6.1WAIT Type Output

6.2DTACK Type Output

6.3Dynamically Increasing the Number of Wait States

6.4Guaranteeing RAS Low Time and RAS Precharge Time

7.0RAS AND CAS CONFIGURATION MODES

7.1Byte Writing

7.2Memory Interleaving

7.3Address Pipelining

7.4Error Scrubbing

7.5Page/Burst Mode

8.0 TEST MODE

9.0DRAM CRITICAL TIMING PARAMETERS

9.1Programmable Values of tRAH and tASC

9.2Calculation of tRAH and tASC

10.0DUAL ACCESSING (DP8422A)

10.1Port B Access Mode

10.2Port B Wait State Support

10.3Common Port A and Port B Dual Port Functions

10.3.1GRANTB Output

10.3.2LOCK Input

11.0 ABSOLUTE MAXIMUM RATINGS

12.0 DC ELECTRICAL CHARACTERISTICS

13.0 AC TIMING PARAMETERS

14.0FUNCTIONAL DIFFERENCES BETWEEN THE DP8420A/21A/22A AND THE DP8420/21/22

15.0 DP8420A/21A/22A USER HINTS

2

1.0 Introduction

The DP8420A/21A/22A are CMOS Dynamic RAM controllers that incorporate many advanced features which include address latches, refresh counter, refresh clock, row, column and refresh address multiplexer, delay line, refresh/access arbitration logic and high capacitive drivers. The programmable system interface allows any manufacturer's microprocessor or bus to directly interface via the DP8420A/21A/22A to DRAM arrays up to 64 Mbytes in size.

After power up, the user must first reset and program the DP8420A/21A/22A before accessing the DRAM. The chip is programmed through the address bus.

Reset:

Due to the differences in power supplies, the internal reset circuit may not always reset correctly; therefore, an External (hardware) Reset must be performed before programming the chip.

Programming:

After resetting the chip, the user can program the controller by either one of two methods: Mode Load Only Programming or Chip Select Access Programming.

Initialization Period:

Once the DP8420A/21A/22A has been programmed for the first time, a 60 ms initialization period is entered. During this time the DRC performs refreshes to the DRAM array so further warm up cycles are unnecessary. The initialization period is entered only after the first programming after a reset.

Accessing Modes:

After resetting and programming the chip, the DP8420A/21A/22A is ready to access the DRAM. There are two modes of accessing with these controllers. Mode 0, which indicates RAS synchronously and Mode 1, which indicates RAS asynchronously.

Refresh Modes:

The DP8420A/21A/22A have expanded refresh capabilities compared to previous DRAM controllers. There are three modes of refreshing available: Internal Automatic Refreshing, Externally Controlled/Burst Refreshing and Refresh Request/Acknowledge Refreshing. Any of these modes can be used together or separately to achieve the desired results.

Refresh Types:

These controllers have three types of refreshing available: Conventional, Staggered and Error Scrubbing. Any refresh control mode can be used with any type of refresh.

Wait Support:

The DP8420A/21A/22A have wait support available as DTACK or WAIT. Both are programmable. DTACK, Data Transfer ACKnowledge, is useful for processors whose wait signal is active high. WAIT is useful for those processors whose wait signal is active low. The user can choose either at programming. These signals are used by the on chip arbiter to insert wait states to guarantee the arbitration between accesses, refreshes and precharge. Both signals are independent of the access mode chosen and both signals can be dynamically delayed further through the WAITIN signal to the DP8420A/21A/22A.

Sequential Accesses (Static Column/Page Mode):

The DP8420A/21A/22A have address latches, used to latch the bank, row and column address inputs. Once the address is latched, a COLumn INCrement (COLINC) feature can be used to increment the column address. The address latches can also be programmed to be fall through. COLINC can be used for Sequential Accesses of Static Column DRAMs. Also, COLINC in conjunction with ECAS inputs can be used for Sequential Accesses to Page Mode DRAMs.

RAS and CAS Configuration (Byte Writing):

The RAS and CAS drivers can be configured to drive a one, two or four bank memory array up to 32 bits in width. The ECAS signals can then be used to select one of four CAS drivers for Byte Writing with no extra logic.

Memory Interleaving:

When configuring the DP820A/21A/22A for more than one bank, Memory Interleaving can be used. By tying the low order address bits to the bank select lines B0 and B1, sequential back to back accesses will not be delayed since these controllers have separate precharge counters per bank.

Address Pipelining:

The DP8420A/21A/22A are capable of performing Address Pipelining. In address pipelining, the DRC will guarantee the column address hold time and switch the internal multiplexor to place the row address on the address bus. At this time, another memory access to another bank can be initiated.

Dual Accessing:

Finally, the DP8422A has all the features previously mentioned and unlike the DP8420A/21A, the DP8422A has a second port to allow a second CPU to access the same memory array. The DP8422A has four signals to support Dual Accessing, these signals are AREQB, ATACKB, LOCK and GRANTB. All arbitration for the two ports and refresh is done on chip by the controller through the insertion of wait states. Since the DP8422A has only one input address bus, the address lines must be multiplexed externally. The signal GRANTB can be used for this purpose.

Terminology:

The following explains the terminology used in this data sheet. The terms negated and asserted are used. Asserted refers to a ``true'' signal. Thus, ``ECAS0 asserted'' means the ECAS0 input is at a logic 0. The term ``COLINC asserted'' means the COLINC input is at a logic 1. The term negated refers to a ``false'' signal. Thus, ``ECAS0 negated'' means the ECAS0 input is at a logic 1. The term ``COLINC negated'' means the input COLINC is at a logic 0. The table shown below clarifies this terminology.

Signal	Action	Logic Level
Active High	Asserted	High
Active High	Negated	Low
Active Low	Asserted	Low
Active Low	Negated	High

3

Connection Diagrams

TL/F/8588 ± 4	TL/F/8588 ± 3
Top View	Top View
FIGURE 2	FIGURE 3

Order Number DP8420AV-20 or DP8420AV-25 See NS Package Number V68A

Order Number DP8421AV-20 or DP8421AV-25 See NS Package Number V68A

TL/F/8588 ± 2

Top View

FIGURE 4

Order Number DP8422AV-20 or DP8422AV-25

See NS Package Number V84A

4

2.0 Signal Descriptions

Pin

Device (If not

Input/

Description

Name

Applicable to All)

Output

2.1 ADDRESS, R/W AND PROGRAMMING SIGNALS

R0 ± 10

DP8422A

I

ROW ADDRESS: These inputs are used to specify the row address during an access

R0 ± 9

DP8420A/21A

I

to the DRAM. They are also used to program the chip when ML is asserted (except

R10).

C0 ± 10

DP8422A

I

COLUMN ADDRESS: These inputs are used to specify the column address during an

C0 ± 9

DP8420A/21A

I

access to the DRAM. They are also used to program the chip when ML is asserted

(except C10).

B0, B1

I

BANK SELECT: Depending on programming, these inputs are used to select a group

of RAS and CAS outputs to assert during an access. They are also used to program

the chip when ML is asserted.

ECAS0 ± 3

I

ENABLE CAS: These inputs are used to enable a single or group of CAS outputs

when asserted. In combination with the B0, B1 and the programming bits, these

inputs select which CAS output or CAS outputs will assert during an access. The

ECAS signals can also be used to toggle a group of CAS outputs for page/nibble

mode accesses. They also can be used for byte write operations. If ECAS0 is

negated during programming, continuing to assert the ECAS0 while negating AREQ

or AREQB during an access, will cause the CAS outputs to be extended while the

RAS outputs are negated (the ECASn inputs have no effect during scrubbing

refreshes).

WIN

I

WRITE ENABLE IN: This input is used to signify a write operation to the DRAM. If

ECAS0 is asserted during programming, the WE output will follow this input. This

input asserted will also cause CAS to delay to the next positive clock edge if address

bit C9 is asserted during programming.

COLINC

I

COLUMN INCREMENT: When the address latches are used, and RFIP is negated,

(EXTNDRF)

I

this input functions as COLINC. Asserting this signal causes the column address to

be incremented by one. When RFIP is asserted, this signal is used to extend the

refresh cycle by any number of periods of CLK until it is negated.

ML

I

MODE LOAD: This input signal, when low, enables the internal programming register

that stores the programming information.

2.2 DRAM CONTROL SIGNALS

Q0 ± 10

DP8422A

O

DRAM ADDRESS: These outputs are the multiplexed output of the R0 ± 9, 10 and

Q0 ± 9

DP8421A

O

C0 ± 9, 10 and form the DRAM address bus. These outputs contain the refresh

Q0 ± 8

DP8421A

O

address whenever RFIP is asserted. They contain high capacitive drivers with 20X

series damping resistors.

RAS0 ± 3

O

ROW ADDRESS STROBES: These outputs are asserted to latch the row address

contained on the outputs Q0 ± 8, 9, 10 into the DRAM. When RFIP is asserted, the

RAS outputs are used to latch the refresh row address contained on the Q0 ± 8, 9, 10

outputs in the DRAM. These outputs contain high capacitive drivers with 20X series

damping resistors.

CAS0 ± 3

O

COLUMN ADDRESS STROBES: These outputs are asserted to latch the column

address contained on the outputs Q0 ± 8, 9, 10 into the DRAM. These outputs have

high capacitive drivers with 20X series damping resistors.

WE

O

WRITE ENABLE or REFRESH REQUEST: This output asserted specifies a write

operation to the DRAM. When negated, this output specifies a read operation to the

(RFRQ)

O

DRAM. When the DP8420A/21A/22A is programmed in address pipelining mode or

when ECAS0 is negated during programming, this output will function as RFRQ.

When asserted, this pin specifies that 13 ms or 15 ms have passed. If DISRFSH is

negated, the DP8420A/21A/22A will perform an internal refresh as soon as possible.

If DISRFRSH is asserted, RFRQ can be used to externally request a refresh through

the input RFSH. This output has a high capacitive driver and a 20X series damping

resistor.

5

2.0 Signal Descriptions (Continued)

Pin

Device (If not

Input/

Description

Name

Applicable to All)

Output

2.3 REFRESH SIGNALS

RFIP

O

REFRESH IN PROGRESS: This output is asserted prior to a refresh cycle and is

negated when all the RAS outputs are negated for that refresh.

RFSH

I

REFRESH: This input asserted with DISRFRSH already asserted will request a

refresh. If this input is continually asserted, the DP8420A/21A/22A will perform

refresh cycles in a burst refresh fashion until the input is negated. If RFSH is asserted

with DISRFSH negated, the internal refresh address counter is cleared (useful for

burst refreshes).

DISRFSH

I

DISABLE REFRESH: This input is used to disable internal refreshes and must be

asserted when using RFSH for externally requested refreshes.

2.4 PORT A ACCESS SIGNALS

ADS

I

ADDRESS STROBE or ADDRESS LATCH ENABLE: Depending on programming,

(ALE)

I

this input can function as ADS or ALE. In mode 0, the input functions as ALE and

when asserted along with CS causes an internal latch to be set. Once this latch is set

an access will start from the positive clock edge of CLK as soon as possible. In Mode

1, the input functions as ADS and when asserted along with CS, causes the access

RAS to assert if no other event is taking place. If an event is taking place, RAS will be

asserted from the positive edge of CLK as soon as possible. In both cases, the low

going edge of this signal latches the bank, row and column address if programmed to

do so.

CS

I

CHIP SELECT: This input signal must be asserted to enable a Port A access.

AREQ

I

ACCESS REQUEST: This input signal in Mode 0 must be asserted some time after

the first positive clock edge after ALE has been asserted. When this signal is

negated, RAS is negated for the access. In Mode 1, this signal must be asserted

before ADS can be negated. When this signal is negated, RAS is negated for the

access.

WAIT

O

WAIT or DTACK: This output can be programmed to insert wait states into a CPU

access cycle. With R7 negated during programming, the output will function as a

(DTACK)

O

WAIT type output. In this case, the output will be active low to signal a wait condition.

With R7 asserted during programming, the output will function as DTACK. In this

case, the output will be negated to signify a wait condition and will be asserted to

signify the access has taken place. Each of these signals can be delayed by a

number of positive clock edges or negative clock levels of CLK to increase the

microprocessor's access cycle through the insertion of wait states.

WAITIN

I

WAIT INCREASE: This input can be used to dynamically increase the number of

positive clock edges of CLK until DTACK will be asserted or WAIT will be negated

during a DRAM access.

6

2.0 Signal Descriptions (Continued)

Pin

Device (If not

Input/

Description

Name

Applicable to All)

Output

2.5 PORT B ACCESS SIGNALS

AREQB

DP8422A

I

PORT B ACCESS REQUEST: This input asserted will latch the row, column and bank

only

address if programmed, and requests an access to take place for Port B. If the

access can take place, RAS will assert immediately. If the access has to be delayed,

RAS will assert as soon as possible from a positive edge of CLK.

ATACKB

DP8422A

O

ADVANCED TRANSFER ACKNOWLEDGE PORT B: This output is asserted when

only

the access RAS is asserted for a Port B access. This signal can be used to generate

the appropriate DTACK or WAIT type signal for Port B's CPU or bus.

2.6 COMMON DUAL PORT SIGNALS

GRANTB

DP8422A

O

GRANT B: This output indicates which port is currently granted access to the DRAM

only

array. When GRANTB is asserted, Port B has access to the array. When GRANTB is

negated, Port A has access to the DRAM array. This signal is used to multiplex the

signals R0 ± 8, 9, 10; C0 ± 8, 9, 10; B0 ± 1; WIN; LOCK and ECAS0 ± 3 to the DP8422A

when using dual accessing.

LOCK

DP8422A

I

LOCK: This input can be used by the currently granted port to ``lock out'' the other

only

port from the DRAM array by inserting wait states into the locked out port's access

cycle until LOCK is negated.

2.7 POWER SIGNALS AND CAPACITOR INPUT

VCC

I

POWER: Supply Voltage.

GND

I

GROUND: Supply Voltage Reference.

CAP

I

CAPACITOR: This input is used by the internal PLL for stabilization. The value of the

ceramic capacitor should be 0.1 mF and should be connected between this input and

ground.

2.8 CLOCK INPUTS

There are two clock inputs to the DP8420A/21A/22A, CLK and DELCLK. These two clocks may both be tied to the same clock input, or they may be two separate clocks, running at different frequencies, asynchronous to each other.

CLK		I		SYSTEM CLOCK: This input may be in the range of 0 Hz up to 25 MHz. This input is
				generally a constant frequency but it may be controlled externally to change
				frequencies or perhaps be stopped for some arbitrary period of time.
				This input provides the clock to the internal state machine that arbitrates between
				accesses and refreshes. This clock's positive edges and negative levels are used to
				extend the WAIT (DTACK) signals. Ths clock is also used as the reference for the
				RAS precharge time and RAS low time during refresh.
				All Port A and Port B accesses are assumed to be synchronous to the system clock
				CLK.
DELCLK		I		DELAY LINE CLOCK: The clock input DELCLK, may be in the range of 6 MHz to
				20 MHz and should be a multiple of 2 (i.e., 6, 8, 10, 12, 14, 16, 18, 20 MHz) to have
				the DP8420A/21A/22A switching characteristics hold. If DELCLK is not one of the
				above frequencies the accuracy of the internal delay line will suffer. This is because
				the phase locked loop that generates the delay line assumes an input clock
				frequency of a multiple of 2 MHz.
				For example, if the DELCLK input is at 7 MHz and we choose a divide by 3 (program
				bits C0 ± 2) this will produce 2.333 MHz which is 16.667% off of 2 MHz. Therefore, the
				DP8420A/21A/22A delay line would produce delays that are shorter (faster delays)
				than what is intended. If divide by 4 was chosen the delay line would be longer
				(slower delays) than intended (1.75 MHz instead of 2 MHz). (See Section 10 for more
				information.)
				This clock is also divided to create the internal refresh clock.

7

3.0 Programming and Resetting

Due to the variety in power supplies power-up times, the internal power up reset circuit may not work in every design; therefore, an EXTERNAL RESET must be performed before the DRAM controller can be programmed and used.

After going through the reset procedure, the DP8420A/21A/22A can be programmed by either of two methods; Mode Load Only Programming or Chip Select Access Programming. After programming the DRC for the first time after reset, the chip enters a 60 ms initialization period, during this period the controller performs refreshes every 13 ms or 15 ms, this makes further DRAM warm up cycles unnecessary. After this stage the chip can be reprogrammed as many times as the user wishes and the 60 ms period will not be entered into unless the chip is reset and programmed again.

During the 60 ms initialization period, RFIP is asserted low and RAS toggles every 13 ms or 15 ms depending on the programming bit for refresh (C3). CAS will be inactive (logic 1) and the ``Q'' outputs will count from 0 to 2047 refreshing the entire DRAM array. The actual initialization time period is given by the following formula. T e 4096* (Clock Divisor Select)* (Refresh Clock Fine Tune)/(DELCLK Frq.)

3.1 EXTERNAL RESET

At power up, if the internal power up reset worked, all internal latches and flip-flops are cleared and the part is ready to be programmed. The power up state can also be achieved by performing an External Reset, which is required to insure proper operation. External Reset is achieved by asserting ML and DISRFSH for at least 16 positive clock edges. In order to perform simply a Reset, the ML signal must be negated before DISRFSH is negated as shown in Figure 5a . This procedure will only reset the controller which now is ready for programming.

While performing an External Reset, if the user negates DISRFSH at least one clock period before negating ML, as shown in Figure 5b , ML negated will program the DP8420A/21A/22A with the values in R0 ± 9, C0 ± 9, B0 ± 1 and ECAS0. The 60 ms initialization period will be entered since it is the first programming after reset. This is a good way of resetting and programming the part at the same time. Make sure the right programming bits are on the address lines before ML is negated.

The DRC may be Reset and programmed any time on the fly, but the user must make sure that No Access or Refresh is in progress.

TL/F/8588 ± E1

FIGURE 5a. Chip Reset but Not Programmed

TL/F/8588 ± E2

FIGURE 5b. Chip Reset and Programmed

8

3.0 Programming and Resetting (Continued)

3.2 PROGRAMMING METHODS

3.2.1 Mode Load Only Programming

To use this method the user asserts ML enabling the internal programming register. After ML is asserted, a valid programming selection is placed on the address bus, B0, B1 and ECAS0 inputs, then ML is negated. When ML is negated the programming bits are latched into the internal programming register and the DP8420A/21A/22A is programmed, see Figure 6 . When programming the chip, the controller must not be refreshing, RFIP must be high (1) to have a successful programming.

3.2.2 Chip Selected Access Programming

The chip can also be programmed by performing a chip selected access. To program the chip using this method, ML is asserted, then CS is asserted and a valid programming selection is placed on the address bus. When AREQ is asserted, the programming bits affecting the wait logic become effective immediately, then DTACK is asserted allowing the access to terminate. After the access, ML is negated and the rest of the programming bits take effect.

TL/F/8588 ± G3

FIGURE 6. ML Only Programming

TL/F/8588 ± G4

FIGURE 7. CS Access Programming

9

3.0Programming and Resetting (Continued)

3.3PROGRAMMING BIT DEFINITIONS

	Symbol				Description
	ECAS0		Extend CAS/Refresh Request Select

0The CASn outputs will be negated with the RASn outputs when AREQ (or AREQB, DP8422A only) is negated. The WE output pin will function as write enable.

1The CASn outputs will be negated, during an acccess (Port A (or Port B, DP8422A only)) when their corresponding ECASn inputs are negated. This feature allows the CAS outputs to be extended beyond the RAS outputs negating. Scrubbing refreshes are NOT affected. During scrubbing refreshes the CAS outputs will negate along with the RAS outputs regardless of the state of the ECAS inputs.

The WE output will function as ReFresh ReQuest (RFRQ) when this mode is programmed.

B1	Access Mode Select

0ACCESS MODE 0: ALE pulsing high sets an internal latch. On the next positive edge of CLK, the access (RAS) will start. AREQ will terminate the access.

1ACCESS MODE 1: ADS asserted starts the access (RAS) immediately. AREQ will terminate the access.

B0	Address Latch Mode

0ADS or ALE asserted for Port A or AREQB asserted for Port B with the appropriate GRANT latch the input row, column and bank address.

1The row, column and bank latches are fall through.

C9	Delay CAS during WRITE Accesses

0CAS is treated the same for both READ and WRITE accesses.

1During WRITE accesses, CAS will be asserted by the event that occurs last: CAS asserted by the internal delay line or CAS asserted on the positive edge of CLK after RAS is asserted.

C8	Row Address Hold Time

0Row Address Hold Time e 25 ns minimum

1Row Address Hold Time e 15 ns minimum

C7	Column Address Setup Time

0Column Address Setup Time e 10 ns miniumum

1Column Address Setup Time e 0 ns minimum

C6, C5, C4

RAS and CAS Configuration Modes/Error Scrubbing during Refresh

0, 0, 0

RAS0 ± 3 and CAS0 ± 3 are all selected during an access. ECASn must be asserted for CASn to be asserted.

B0 and B1 are not used during an access. Error scrubbing during refresh.

0, 0, 1

RAS and CAS pairs are selected during an access by B1. ECASn must be asserted for CASn to be asserted.

B1 e 0 during an access selects

± 1 and

± 1.

RAS0

CAS0

B1 e 1 during an access selects

RAS2

± 3 and

CAS2

± 3.

B0 is not used during an Access.

Error scrubbing during refresh.

0, 1, 0

RAS and CAS singles are selected during an access by B0 ± 1. ECASn must be asserted for CASn to be asserted.

B1 e 0, B0 e 0 during an access selects

and

RAS0

CAS0.

B1 e 0, B0 e 1 during an access selects

and

RAS1

CAS1.

B1 e 1, B0 e 0 during an access selects

and

RAS2

CAS2.

B1 e 1, B0 e 1 during an access selects

and

RAS3

CAS3.

Error scrubbing during refresh.

0, 1, 1

RAS0 ± 3 and CAS0 ± 3 are all selected during an access. ECASn must be asserted for CASn to be asserted.

B1, B0 are not used during an access.

No error scrubbing. (RAS only refreshing)

1, 0, 0

RAS pairs are selected by B1. CAS0 ± 3 are all selected. ECASn must be asserted for CASn to be asserted.

B1 e 0 during an access selects

± 1 and

± 3.

RAS0

CAS0

B1 e 1 during an access selects

RAS2

± 3 and

CAS0

± 3.

B0 is not used during an access.

No error scrubbing.

10

3.0 Programming and Resetting (Continued)

3.3 PROGRAMMING BIT DEFINITIONS (Continued)

Symbol

Description

C6, C5, C4

RAS and CAS Configuration Modes (Continued)

1, 0, 1

RAS and CAS pairs are selected by B1. ECASn must be asserted for CASn to be asserted.

B1 e 0 during an access selects

± 1 and

± 1.

RAS0

CAS0

B1 e 1 during an access selects

RAS2

± 3 and

CAS2

± 3.

B0 is not used during an access.

No error scrubbing.

1, 1, 0

RAS singles are selected by B0 ± 1. CAS0 ± 3 are all selected. ECASn must be asserted for CASn to be

asserted.

B1 e 0, B0 e 0 during an access selects

and

± 3.

RAS0

CAS0

B1 e 0, B0 e 1 during an access selects

RAS1

and

CAS0

± 3.

B1 e 1, B0 e 0 during an access selects

RAS2

and

CAS0

± 3.

B1 e 1, B0 e 1 during an access selects

RAS3

and

CAS0

± 3.

No error scrubbing.

1, 1, 1

RAS and CAS singles are selected by B0, 1. ECASn must be asserted for CASn to be asserted.

B1 e 0, B0 e 0 during an access selects

and

RAS0

CAS0.

B1 e 0, B0 e 1 during an access selects

and

RAS1

CAS1.

B1 e 1, B0 e 0 during an access selects

and

RAS2

CAS2.

B1 e 1, B0 e 1 during an access selects

RAS3

and

CAS3.

No error scrubbing.

C3

Refresh Clock Fine Tune Divisor

0Divide delay line/refresh clock further by 30 (If DELCLK/Refresh Clock Clock Divisor e 2 MHz e 15 ms refresh period).

1 Divide delay line/refresh clock further by 26 (If DELCLK/Refresh Clock Clock Divisor e 2 MHz e 13 ms refresh period).

C2, C1, C0	Delay Line/Refresh Clock Divisor Select
0, 0, 0	Divide DELCLK by 10 to get as close to 2 MHz as possible.
0, 0, 1	Divide DELCLK by 9 to get as close to 2 MHz as possible.
0, 1, 0	Divide DELCLK by 8 to get as close to 2 MHz as possible.
0, 1, 1	Divide DELCLK by 7 to get as close to 2 MHz as possible.
1, 0, 0	Divide DELCLK by 6 to get as close to 2 MHz as possible.
1, 0, 1	Divide DELCLK by 5 to get as close to 2 MHz as possible.
1, 1, 0	Divide DELCLK by 4 to get as close to 2 MHz as possible.
1, 1, 1	Divide DELCLK by 3 to get as close to 2 MHz as possible.
R9	Refresh Mode Select

0RAS0 ± 3 will all assert and negate at the same time during a refresh.

1Staggered Refresh. RAS outputs during refresh are separated by one positive clock edge. Depending on the configuration mode chosen, either one or two RASs will be asserted.

R8	Address Pipelining Select

0Address pipelining is selected. The DRAM controller will switch the DRAM column address back to the row address after guaranteeing the column address hold time.

1Non-address pipelining is selected. The DRAM controller will hold the column address on the DRAM address bus until the access RASs are negated.

R7	WAIT or DTACK Select

0WAIT type output is selected.

1DTACK (Data Transfer ACKnowledge) type output is selected.

R6	Add Wait States to the Current Access if WAITIN is Low

0WAIT or DTACK will be delayed by one additional positive edge of CLK.

1WAIT or DTACK will be delayed by two additional positive edges of CLK.

11

3.0Programming and Resetting (Continued)

3.3PROGRAMMING BIT DEFINITIONS (Continued)

Symbol

Description

R5, R4

WAIT/DTACK during Burst (See Section 5.1.2 or 5.2.2)

NO WAIT STATES; If R7 e 0 during programming,

will remain negated during burst portion of access.

0, 0

WAIT

If R7 e 1 programming,

DTACK

will remain asserted during burst portion of access.

1T; If R7 e 0 during programming,

will assert when the

inputs are negated with

asserted.

0, 1

WAIT

ECAS

AREQ

WAIT will negate from the positive edge of CLK after the ECASs have been asserted.

If R7 e 1 during programming,

will negate when the

inputs are negated with

asserted.

DTACK

ECAS

AREQ

DTACK will assert from the positive edge of CLK after the ECASs have been asserted.

(/2T; If R7 e 0 during programming,

will assert when the

inputs are negated with

asserted.

1, 0

WAIT

ECAS

AREQ

WAIT will negate on the negative level of CLK after the ECASs have been asserted.

If R7 e 1 during programming,

will negate when the

inputs are negated with

asserted.

DTACK

ECAS

AREQ

DTACK will assert from the negative level of CLK after the ECASs have been asserted.

0T; If R7 e 0 during programming,

will assert when the

inputs are negated.

will negate when

1, 1

WAIT

ECAS

WAIT

the ECAS inputs are asserted.

If R7 e 1 during programming,

will negate when the

inputs are negated.

will assert when

DTACK

ECAS

DTACK

the ECAS inputs are asserted.

R3, R2

WAIT/DTACK Delay Times (See Section 5.1.1 or 5.2.1)

NO WAIT STATES; If R7 e 0 during programming,

will remain high during non-delayed accesses.

0, 0

WAIT

WAIT

will negate when RAS is negated during delayed accesses.

NO WAIT STATES; If R7 e 1 during programming,

will be asserted when

is asserted.

DTACK

RAS

(/2T; If R7 e 0 during programming,

will negate on the negative level of CLK, after the access

0, 1

WAIT

RAS.

1T; If R7 e 1 during programming,

DTACK

will be asserted on the positive edge of CLK after the access

RAS.

NO WAIT STATES, (/2T; If R7 e 0 during programming,

will remain high during non-delayed accesses.

1, 0

WAIT

WAIT will negate on the negative level of CLK, after the access RAS, during delayed accesses.

(/2T; If R7 e 1 during programming,

will be asserted on the negative level of CLK after the access

DTACK

RAS.

1T; If R7 e 0 during programming,

1, 1

WAIT

will negate on the positive edge of CLK after the access RAS.

1(/2T; If R7 e 1 during programming,

DTACK

will be asserted on the negative level of CLK after the positive edge

of CLK after the access RAS.

R1, R0

RAS Low and RAS Precharge Time

asserted during refresh e 2 positive edges of CLK.

0, 0

RAS

RAS

precharge time e 1 positive edge of CLK.

RAS will start from the first positive edge of CLK after GRANTB transitions (DP8422A).

asserted during refresh e 3 positive edges of CLK.

0, 1

RAS

RAS

precharge time e 2 positive edges of CLK.

RAS will start from the second positive edge of CLK after GRANTB transitions (DP8422A).

asserted during refresh e 2 positive edges of CLK.

1, 0

RAS

RAS

precharge time e 2 positive edges of CLK.

RAS will start from the first positive edge of CLK after GRANTB transitions (DP8422A).

asserted during refresh e 4 positive edges of CLK.

1, 1

RAS

RAS

precharge time e 3 positive edges of CLK.

RAS will start from the second positive edge of CLK after GRANTB transitions (DP8422A).

12

4.0 Port A Access Modes

The DP8420A/21A/22A have two general purpose access modes. Mode 0 RAS synchronous and Mode 1 RAS asynchronous. One of these modes is selected at programming through the B1 input. A Port A access to DRAM is initiated by two input signals: ADS (ALE) and CS. The access is always terminated by one signal: AREQ. These input signals should be synchronous to the input clock.

4.1 ACCESS MODE 0

Mode 0, synchronous access, is selected by negating the input B1 during programming (B1e0). To initiate a Mode 0 access, ALE is pulse high and CS is asserted. If precharge time was met, a refresh of DRAM or a Port B access was not in progress, the RAS (RASs) would be asserted on the

first rising edge of clock. If a refresh or a Port B access is in progress or precharge time is required, the controller will wait until these events have taken place and assert RAS (RASs) on the next positive edge of clock.

Sometime after the first positive edge of clock after ALE and CS have been asserted, the input AREQ must be asserted. In single port applications, once AREQ is asserted, CS can be negated. On the other hand, ALE can stay asserted several periods of clock; however, ALE must be negated before or during the period of CLK in which AREQ is negated.

The controller samples AREQ on the every rising edge of clock after DTACK is asserted. The access will end when AREQ is sampled negated.

TL/F/8588 ± 60

FIGURE 8a. Access Mode 0

13

4.0Port A Access Modes (Continued)

4.2ACCESS MODE 1

Mode 1, asynchronous access, is selected by asserting the input B1 during programming (B1e1). This mode allows accesses to start immediately from the access request input, ADS. To initiate a Mode 1 access, CS is asserted followed by ADS asserted. If precharge time was met, a refresh of the DRAM or a Port B access was not in progress, the RAS (RASs) would be asserted from ADS being asserted. If a refresh or Port B access is in progress or precharge time is required, the controller will wait until these events have tak-

en place and assert RAS (RASs) from the next rising edge of clock.

When ADS is asserted or sometime after, AREQ must be asserted. At this time, ADS can be negated and AREQ will continue the access. Also, ADS can continue to be asserted after AREQ has been asserted and negated; however, a new access will not start until ADS is negated and asserted again. When address pipelining is not implemented, ADS and AREQ can be tied together.

The access will end when AREQ is negated.

TL/F/8588 ± 62

FIGURE 8b. Access Mode 1

14

4.0 Port A Access Modes (Continued)

4.3 EXTENDING CAS WITH EITHER ACCESS MODE

In both access modes, once AREQ is negated, RAS and DTACK if programmed will be negated. If ECAS0 was asserted (0) during programming, CAS (CASs) will be negated

with AREQ. If ECAS0 was negated (1) during programming, CAS (CASs) will continue to be asserted after RAS has been negated, given that the appropriate ECAS inputs are asserted. This allows a DRAM to have data present on the data out bus while gaining RAS precharge time.

TL/F/8588 ± 61

FIGURE 9a. Access Mode 0 Extending CAS

TL/F/8588 ± 63

FIGURE 9b. Access Mode 1 Extending CAS

15

4.0Port A Access Modes (Continued)

4.4READ-MODIFY-WRITE CYCLES WITH EITHER ACCESS MODE

There are 2 methods by which this chip can be used to do read-modify-write access cycles. The first method involves doing a late write access where the WIN input is asserted some delay after CAS is asserted. The second method involves doing a page mode read access followed by a page mode write access with RAS held low (see Figure 9c ).

CASn must be toggled using the ECASn inputs and WIN has to be changed from negated to asserted (read to write) while CAS is negated. This method is better than changing

WIN from negated to asserted in a late write access because here a problem may arise with DATA IN and DATA OUT being valid at the same time. This may result in a data line trying to drive two different levels simultaneously. The page mode method of a read-modify-write access allows the user to have transceivers in the system because the data in (read data) is guaranteed to be high impedance during the time the data out (write data) is valid.

TL/F/8588 ± G2

*There may be idle states inserted here by the CPU.

FIGURE 9c. Read-Modify-Write Access Cycle

16

4.0 Port A Access Modes (Continued)

4.5 ADDITIONAL ACCESS SUPPORT FEATURES

To support the different modes of accessing, the DP8420A/21A/22A offer other access features. These additional features include: Address Latches and Column Increment (for page/burst mode support), Address Pipelining, and Delay CAS (to allow the user with a multiplexed bus to ensure valid data is present before CAS is asserted).

4.5.1 Address Latches and Column Increment

The Address Latches can be programmed, through programming bit B0. They can be programmed to either latch the address or remain in a fall-through mode. If the address latches are used to latch the address, the controller will function as follows:

In Mode 0, the rising edge of ALE places the latches in fallthrough, once ALE is negated, the address present in the row, column and bank input is latched.

In Mode 1, the address latches are in fall through mode until ADS is asserted. ADS asserted latches the address.

Once the address is latched, the column address can be incremented with the input COLINC. COLINC can be used for sequential accesses of static column DRAMs. COLINC can also be used with the ECAS inputs to support sequential accesses to page mode DRAMs as shown in Figure 10 . COLINC should only be asserted when the signal RFIP is negated during an access since this input functions as extended refresh when RFIP is asserted. COLINC must be negated (0) when the address is being latched (ADS falling edge in Mode 1). If COLINC is asserted with all of the bits of the column address asserted (ones), the column address will return to zero.

TL/F/8588 ± C4

FIGURE 10. Column Increment

The address latches function differently with the DP8422A. The DP8422A will latch the address of the currently granted port. If Port A is currently granted, the address will be latched as described in Section 4.5.1. If Port A is not granted, and requests an access, the address will be latched on the first or second positive edge of CLK after GRANTB has been negated depending on the programming bits R0, R1.

For Port B, if GRANTB is asserted, the address will be latched with AREQB asserted. If GRANTB is negated, the address will latch on the first or second positive edge of CLK after GRANTB is asserted depending on the programming bits R0, R1.

17

4.0 Port A Access Modes (Continued)

4.5.2 Address Pipelining

Address pipelining is the overlapping of accesses to different banks of DRAM. If the majority of successive accesses are to a different bank, the accesses can be overlapped. Because of this overlapping, the cycle time of the DRAM accesses are greatly reduced. The DP8420A/21A/22A can be programmed to allow a new row address to be placed on the DRAM address bus after the column address hold time has been met. At this time, a new access can be initiated with ADS or ALE, depending on the access mode, while AREQ is used to sustain the current access. The DP8422A supports address pipelining for Port A only. This mode cannot be used with page, static column or nibble modes of operations because the DRAM column address is switched back to the row address after CAS is asserted. This mode is programmed through address bit R8 (see Figures 11a and 11b ). In this mode, the output WE always functions as RFRQ.

During address pipelining in Mode 0, shown in Figure 11c , ALE cannot be pulsed high to start another access until AREQ has been asserted for the previous access for at least one period of CLK. DTACK, if programmed, will be negated once AREQ is negated. WAIT, if programmed to insert wait states, will be asserted once ALE and CS are asserted.

In Mode 1, shown in Figure 11d , ADS can be negated once AREQ is asserted. After meeting the minimum negated pulse width for ADS, ADS can again be asserted to start a new access. DTACK, if programmed, will be negated once AREQ is negated. WAIT, if programmed, will be asserted once ADS is asserted.

In either mode with either type of wait programmed, the DP8420A/21A/22A will still delay the access for precharge if sequential accesses are to the same bank or if a refresh takes place.

TL/F/8588 ± G0

FIGURE 11a. Non-Address Pipelined Mode

TL/F/8588 ± G1

FIGURE 11b. Address Pipelined Mode

18