NSC CLC532MDC, CLC532AMC, CLC532AJP, CLC532AJE, 5962-9203501MCA Datasheet
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June 1999 |
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CLC532
High-Speed 2:1 Analog Multiplexer
General Description
The CLC532 is a high-speed 2:1 multiplexer with active input and output stages. The CLC532 also employs a closed-loop design which dramatically improves accuracy. This monolithicdevice is constructed using an advanced high-performance bipolar process.
The CLC532 has been specifically designed to provide settling times of 17ns to 0.01%. This, coupled with the adjustable noise-bandwidth, makes the CLC532 an ideal choice for infrared and CCD imaging systems. Channel-to-channel isolation is better than 80dB @ 10MHz. Low distortion (80dBc) and spurious signal levels make the CLC532 a very suitable choice for both I/Q processors and receivers.
TheCLC532isofferedoverboththeindustrialandmilitarytemperature ranges. The Industrial versions, CLC532AJP\AJE\AID, are specified from -40°C to +85°C and are packaged in 14-pin plastic DIP's, 14-pin SOIC'sand14-pinSide-Brazedpackages. Theextendedtemperature versions,CLC532A8B/A8D/A8L-2,arespecifiedfrom-55°Cto+125°C and are packaged in a 14-pin hermetic DIP and 20-terminal LCC packages. (Contact factory for LCC and CERDIP availability.)
Ordering Information ...
CLC532AJP |
-40oC to +85oC |
14-pin plastic DIP |
CLC532AJE |
-40oC to +85oC |
14-pin plastic SOIC |
CLC532ALC |
-40oC to +85oC |
dice |
CLC532AMC |
-55oC to +125oC |
dice, MIL-STD-833 |
CLC532A8B |
-55oC to +125oC |
14-pin CERDIP; |
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MIL-STD-883 |
CLC532A8L-2A |
-55oC to +125oC |
20-terminal LCC; |
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MIL-STD-883 |
Contact factory for other packages and DESC SMD number.
Features
■12-bit settling (0.01%) - 17ns
■Low noise - 32 Vrms
■High isolation - 80dB @ 10MHz
■Low distortion - 80dBc @ 5MHz
■Adjustable bandwidth - 190MHz (max)
Applications
■Infrared system multiplexing
■CCD sensor signals
■Radar I/Q switching
■High definition video HDTV
■Test and calibration
Speed-High |
CLC532 |
Multiplexer Analog 2:1 |
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Typical Application
CHANNEL A |
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CCOMP1 |
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2 |
INA |
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1 |
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RIN |
12 |
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CLC532 |
11 |
VOUT |
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6 |
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CHANNEL B |
10 |
RL |
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4 |
INB |
DREF |
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3 |
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7 |
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RIN |
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CCOMP2 |
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CHANNEL |
SELECT OUTPUT |
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1 |
Channel A |
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SELECT |
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0 |
Channel B |
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1999 National Semiconductor Corporation
20-Terminal LCC
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DGND |
NC |
IN |
NC |
GND |
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B |
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8 |
7 |
6 |
5 |
4 |
INDEX CORNER |
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DREF |
9 |
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3 |
INA |
SELECT 10 |
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2 |
GND |
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NC 11 |
TOP VIEW |
1 |
NC |
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VEE |
12 |
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20 |
+Vcc |
VEE |
13 |
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19 |
+Vcc |
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14 15 |
16 |
17 |
18 |
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COMP |
NC |
OUTPUT |
NC |
COMP |
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2 |
1 |
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Pinout
DIP & SOIC
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GND |
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1 |
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14 |
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+VCC |
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INA |
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2 |
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13 |
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+VCC |
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GND |
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3 |
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12 |
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COMP1 |
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INB |
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4 |
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11 |
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OUTPUT |
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DGND |
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5 |
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10 |
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COMP2 |
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DREF |
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6 |
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9 |
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VEE |
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SELECT |
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7 |
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8 |
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VEE |
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http://www.national.com
Printed in the U.S.A.
Electrical Characteristics (+VCC=+5.0V; -VEE=-5.2V; RIN=50Ω; RL=500Ω; CCOMP=10pF; ECL Mode, pin 6 = NC)
PARAMETER1 |
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CONDITIONS |
TYP |
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MAX/MIN RATINGS2 |
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UNITS |
SYMBOL |
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Case Temperature |
CLC532AJP/AJE/AIB |
+25° C |
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-40° C |
+25° C |
+85° C |
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FREQUENCY DOMAIN PERFORMANCE |
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-3dB bandwidth |
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VOUT<0.1Vpp |
190 |
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140 |
140 |
110 |
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MHz |
SSBW |
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-3dB bandwidth |
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VOUT=2Vpp |
45 |
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35 |
35 |
30 |
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MHz |
LSBW |
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gain flatness |
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VOUT<0.1Vpp |
0.2 |
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0.7 |
0.7 |
0.8 |
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dB |
GFP |
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peaking |
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0.1MHz to 200MHz |
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rolloff |
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0.1MHz to 100MHz |
1.0 |
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1.8 |
1.8 |
2.6 |
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dB |
GFR |
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linear phase deviation |
dc to 100MHz |
2.0 |
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deg |
LPD |
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differential |
gain |
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CCOMP = 5pF; RL=150Ω |
0.05 |
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% |
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DG |
differential |
phase |
CCOMP = 5pF; RL=150Ω |
0.01 |
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75 |
75 |
74 |
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deg |
DP |
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crosstalk rejection |
2Vpp, 10MHz |
80 |
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dB |
CT10 |
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2Vpp, 20MHz |
74 |
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69 |
69 |
68 |
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dB |
CT20 |
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2Vpp, 30MHz |
68 |
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63 |
63 |
62 |
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dB |
CT30 |
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TIME DOMAIN PERFORMANCE |
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rise and fall time |
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0.5V step |
2.7 |
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3.3 |
3.3 |
3.8 |
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ns |
TRS |
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2V step |
10 |
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12.5 |
12.5 |
14.5 |
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ns |
TRL |
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settling time |
2V step; from 50% VOUT |
±0.0025% |
35 |
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24 |
24 |
27 |
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ns |
TS14 |
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±0.01% |
17 |
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ns |
TSP |
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±0.1% |
13 |
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18 |
18 |
21 |
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ns |
TSS |
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overshoot |
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2.0V step |
2 |
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5 |
5 |
6 |
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% |
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OS |
slew rate |
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160 |
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130 |
130 |
110 |
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V/µs |
SR |
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SWITCH PERFORMANCE |
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channel to channel switching time |
50% SELECT to 10%VOUT |
5 |
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7 |
7 |
8 |
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ns |
SWT10 |
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(2V step at output) |
50% SELECT to 90%VOUT |
15 |
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20 |
20 |
23 |
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ns |
SWT90 |
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switching |
transient |
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30 |
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mV |
ST |
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DISTORTION AND NOISE PERFORMANCE |
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2nd harmonic distortion |
2Vpp, 5MHz |
80 |
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67 |
67 |
67 |
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dBc |
HD2 |
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3rd harmonic distortion |
2Vpp, 5MHz |
86 |
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68 |
68 |
68 |
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dBc |
HD3 |
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equivalent |
input |
noise |
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spot noise voltage |
>1MHz |
3.1 |
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nV/√ |
Hz |
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SNF |
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integrated noise |
1MHz to 100MHz |
32 |
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42 |
42 |
46 |
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µVrms |
INV |
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spot noise current |
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3 |
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pA/√ |
Hz |
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SNC |
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STATIC AND DC PERFORMANCE |
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* analog output offset voltage |
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1 |
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6.5 |
3.5 |
5.5 |
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mV |
VOS |
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temperature coefficient |
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15 |
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90 |
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20 |
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µV/°C |
DVIO |
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analog output offset voltage matching |
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TBD |
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mV |
VOSM |
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* analog input bias current |
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50 |
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250 |
120 |
120 |
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µA |
IBN |
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temperature coefficient |
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0.3 |
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2.0 |
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0.8 |
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µA/°C |
DIBN |
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analog input bias current matching |
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TBD |
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µA |
IBNM |
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analog input resistance |
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200 |
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90 |
120 |
120 |
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kΩ |
RIN |
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analog input capacitance |
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2 |
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3.0 |
2.5 |
2.5 |
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pF |
CIN |
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* gain accuracy |
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±2V |
0.998 |
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0.988 |
0.988 |
0.988 |
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V/V |
GA |
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gain matching |
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±2V |
TBD |
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V/V |
GAM |
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integral endpoint non-linearity |
±1V (full scale) |
0.02 |
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0.05 |
0.03 |
0.03 |
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%FS |
ILIN |
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output voltage |
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no load |
±3.4 |
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2.4 |
2.8 |
2.8 |
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V |
VO |
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output current |
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45 |
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20 |
30 |
30 |
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mA |
IO |
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output resistance |
dc |
1.5 |
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4.0 |
2.5 |
2.5 |
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Ω |
RO |
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DIGITAL INPUT PERFORMANCE |
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ECL mode (pin 6 floating) |
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input voltage logic HIGH |
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-1.1 |
-1.1 |
-1.1 |
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V |
VIH1 |
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input voltage logic LOW |
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-1.5 |
-1.5 |
-1.5 |
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V |
VIL1 |
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input current logic HIGH |
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14 |
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50 |
30 |
30 |
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µA |
IIH1 |
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input current logic LOW |
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50 |
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270 |
110 |
110 |
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µA |
IIL1 |
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TTL mode (pin 6 = +5V) |
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input voltage logic HIGH |
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2.0 |
2.0 |
2.0 |
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V |
VIH2 |
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input voltage logic LOW |
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0.8 |
0.8 |
0.8 |
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V |
VIL2 |
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input current logic HIGH |
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14 |
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50 |
30 |
30 |
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µA |
IIH2 |
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input current logic LOW |
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50 |
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270 |
110 |
110 |
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µA |
IIL2 |
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POWER REQUIREMENTS |
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* supply current (+VCC = +5.0V) |
no load |
23 |
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30 |
28 |
25 |
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mA |
ICC |
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* supply current (-VEE = -5.2V) |
no load |
24 |
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31 |
30 |
26 |
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mA |
IEE |
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nominal power dissipation |
no load |
240 |
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mW |
PD |
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* power supply rejection ratio |
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73 |
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60 |
64 |
64 |
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dB |
PSRR |
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Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.
http://www.national.com |
2 |
Recommended Operating Conditions
positive supply voltage (+VCC) |
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+5V |
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negative supply voltage (-VEE) |
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-5.2V or -5.0V |
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differential voltage between any two GND’s |
10mV |
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analog input voltage range |
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±2V |
SELECT input voltage range (TTL mode) |
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0.0V to +3.0V |
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SELECT input voltage range (ECL mode) |
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-2.0V to 0.0V |
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CCOMP range2 |
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0pF to 100pF |
thermal data |
θJC(°C/W) |
θJA(°C/W) |
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14-pin plastic |
55 |
100 |
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14-pin Cerdip |
35 |
85 |
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14-pin SOIC |
35 |
105 |
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20-terminal LCC |
35 |
50 |
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Absolute Maximum Ratings3
positive supply voltage (+VCC) |
-0.5V to +7.0V |
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negative supply voltage (-VEE) |
+0.5V to -7.0V |
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differential voltage between any two GND’s |
200mV |
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analog input voltage range |
-VEE to +VCC |
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digital |
input voltage range |
-VEE to +VCC |
output short circuit duration (output shorted to GND) |
Infinite |
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junction |
temperature |
+150°C |
operating temperature range |
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CLC532AJP/AJE/AIB |
-40°C to +85°C |
storage temperature range |
-65°C to +150°C |
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lead solder duration (+300°C) |
10 sec |
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ESD rating |
<500V |
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transistor count |
74 |
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Note 1: Test levels are as follows:
*AJ : 100% tested at +25°C.
Note 2: The CLC532 does not require external CCOMP capacitors for proper operation.
Note 3: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability.
System Timing Diagram
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SETTLING ERROR |
A |
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WINDOW |
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SELECT |
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B |
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TSx |
SWT90 |
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SWT10 |
TRx |
TRx |
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90% |
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OUTPUT |
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10% |
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CHANNEL A = +1V |
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OS |
CHANNEL B = -1V |
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... where TSx is TS14 or TSP or TSS, and TRx is TRS ro TSL.
Switching Transient Timing Diagram
A
SELECT
B
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~ |
2ns |
ST |
~ |
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OUTPUT
Channel A = 0V
Channel B = 0V
3 |
http://www.national.com |
CLC532 Electrical Characteristics (+25°C unless specified)
http://www.national.com |
4 |
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