June 1989
54LS174/DM54LS174/DM74LS174,
54LS175/DM54LS175/DM74LS175 Hex/Quad D Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad (175) versions feature complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.
Features
YLS174 contains six flip-flops with single-rail outputs
YLS175 contains four flip-flops with double-rail outputs
YBuffered clock and direct clear inputs
YIndividual data input to each flip-flop
YApplications include:
Buffer/storage registers
Shift registers
Pattern generators
YTypical clock frequency 40 MHz
YTypical power dissipation per flip-flop 14 mW
YAlternate Military/Aerospace device (54LS174, 54LS175) is available. Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagrams
Dual-In-Line Package |
Dual-In-Line Package |
TL/F/6404 ± 1
Order Number 54LS174DMQB, 54LS174FMQB, 54LS174LMQB, DM54LS174J,
DM54LS174W, DM74LS174M or DM74LS174N See NS Package Number E20A, J16A, M16A, N16E or W16A
Function Table (Each Flip-Flop)
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Inputs |
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Outputs |
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Clear |
Clock |
D |
Q |
Q² |
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L |
X |
X |
L |
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H |
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H |
u |
H |
H |
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L |
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H |
u |
L |
L |
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H |
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H |
L |
X |
Q0 |
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Q0 |
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TL/F/6404 ± 2
Order Number 54LS175DMQB, 54LS175FMQB, 54LS175LMQB, DM54LS175J
DM54LS175W, DM74LS175M or DM74LS175N See NS Package Number E20A, J16A, M16A, N16E or W16A
H e High Level (steady state) L e Low Level (steady state) X e Don't Care
u e Transition from low to high level
Q0 e The level of Q before the indicated steady-state input conditions were established.
² e LS175 only
54LS175/DM54LS175/DM74LS175 54LS174/DM54LS174/DM74LS174, Clear with Flops-Flip D Hex/Quad
C1995 National Semiconductor Corporation |
TL/F/6404 |
RRD-B30M105/Printed in U. S. A. |
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage |
7V |
Input Voltage |
7V |
Operating Free Air Temperature Range |
b55§C to a125§C |
DM54LS and 54LS |
|
DM74LS |
0§C to a70§C |
Storage Temperature Range |
b65§C to a150§C |
Note: The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings. The ``Recommended Operating Conditions'' table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol |
Parameter |
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DM54LS174 |
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DM74LS174 |
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Units |
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Min |
Nom |
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Max |
Min |
Nom |
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Max |
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VCC |
Supply Voltage |
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4.5 |
5 |
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5.5 |
4.75 |
5 |
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5.25 |
V |
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VIH |
High Level Input Voltage |
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2 |
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2 |
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V |
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VIL |
Low Level Input Voltage |
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0.7 |
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0.8 |
V |
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IOH |
High Level Output Current |
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b0.4 |
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b0.4 |
mA |
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IOL |
Low Level Output Current |
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4 |
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8 |
mA |
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fCLK |
Clock Frequency (Note 1) |
0 |
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30 |
0 |
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30 |
MHz |
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fCLK |
Clock Frequency (Note 2) |
0 |
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25 |
0 |
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25 |
MHz |
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tW |
Pulse Width |
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Clock |
20 |
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20 |
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ns |
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(Note 6) |
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Clear |
20 |
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20 |
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tSU |
Data Setup Time (Note 6) |
20 |
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20 |
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ns |
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tH |
Data Hold Time (Note 6) |
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0 |
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0 |
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ns |
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tREL |
Clear Release Time (Note 6) |
25 |
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25 |
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ns |
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TA |
Free Air Operating Temperature |
b55 |
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125 |
0 |
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70 |
§C |
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'LS174 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol |
Parameter |
Conditions |
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Min |
Typ |
Max |
Units |
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(Note 3) |
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VI |
Input Clamp Voltage |
VCC e Min, II e b18 mA |
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b1.5 |
V |
VOH |
High Level Output |
VCC e Min, IOH e Max |
DM54 |
2.5 |
3.4 |
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V |
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Voltage |
VIL e Max, VIH e Min |
DM74 |
2.7 |
3.4 |
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VOL |
Low Level Output |
VCC e Min, IOL e Max |
DM54 |
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0.25 |
0.4 |
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Voltage |
VIL e Max, VIH e Min |
DM74 |
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0.35 |
0.5 |
V |
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IOL e 4 mA, VCC e Min |
DM74 |
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0.25 |
0.4 |
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II |
Input Current@Max |
VCC e Max, VI e 7V |
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0.1 |
mA |
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Input Voltage |
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IIH |
High Level Input Current |
VCC e Max, VI e 2.7V |
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20 |
mA |
IIL |
Low Level Input |
VCC e Max |
Clock |
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b0.4 |
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Current |
VI e 0.4V |
Clear |
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b0.4 |
mA |
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Data |
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b0.36 |
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IOS |
Short Circuit |
VCC e Max |
DM54 |
b20 |
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b100 |
mA |
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Output Current |
(Note 4) |
DM74 |
b20 |
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b100 |
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ICC |
Supply Current |
VCC e Max (Note 5) |
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16 |
26 |
mA |
Note 1: CL e 15 pF, RL e 2 kX, TA e 25§C and VCC e 5V. |
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Note 2: CL e 50 pF, RL e 2 kX, TA e 25§C and VCC e 5V. |
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Note 3: All typicals are at VCC e 5V, TA e 25§C. |
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Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. |
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Note 5: With all outputs open and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to the clock. Note 6: TA e 25§C and VCC e 5V.
2
'LS174 Switching Characteristics
at VCC e 5V and TA e 25§C (See Section 1 for Test Waveforms and Output Load)
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From (Input) |
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RL e 2 kX |
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Symbol |
Parameter |
To (Output) |
CL e 15 pF |
CL e 50 pF |
Units |
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Min |
Max |
Min |
Max |
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fMAX |
Maximum Clock Frequency |
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30 |
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25 |
|
MHz |
tPLH |
Propagation Delay Time |
Clock to |
|
30 |
|
32 |
ns |
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Low to High Level Output |
Output |
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tPHL |
Propagation Delay Time |
Clock to |
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30 |
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36 |
ns |
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High to Low Level Output |
Output |
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tPHL |
Propagation Delay Time |
Clear to |
|
35 |
|
42 |
ns |
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High to Low Level Output |
Output |
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Recommended Operating Conditions
Symbol |
Parameter |
|
|
DM54LS175 |
|
|
DM74LS175 |
|
Units |
|||
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Min |
Nom |
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Max |
Min |
Nom |
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Max |
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VCC |
Supply Voltage |
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4.5 |
5 |
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5.5 |
4.75 |
5 |
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5.25 |
V |
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VIH |
High Level Input Voltage |
|
2 |
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|
2 |
|
|
|
V |
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VIL |
Low Level Input Voltage |
|
|
|
|
0.7 |
|
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0.8 |
V |
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IOH |
High Level Output Current |
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|
|
b0.4 |
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b0.4 |
mA |
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IOL |
Low Level Output Current |
|
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|
4 |
|
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8 |
mA |
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fCLK |
Clock Frequency (Note 1) |
0 |
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|
30 |
0 |
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30 |
MHz |
||
fCLK |
Clock Frequency (Note 2) |
0 |
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|
25 |
0 |
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|
25 |
MHz |
||
tW |
Pulse Width |
|
Clock |
20 |
|
|
|
20 |
|
|
|
ns |
|
(Note 3) |
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Clear |
20 |
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|
20 |
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tSU |
Data Setup Time (Note 3) |
20 |
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|
20 |
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|
ns |
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tH |
Data Hold Time (Note 3) |
|
0 |
|
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|
0 |
|
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|
ns |
|
tREL |
Clear Release Time (Note 3) |
25 |
|
|
|
25 |
|
|
|
ns |
||
TA |
Free Air Operating Temperature |
b55 |
|
|
125 |
0 |
|
|
70 |
§C |
||
Note 1: CL e 15 pF, RL e 2 kX, TA e 25§C and VCC e 5V.
Note 2: CL e 50 pF, RL e 2 kX, TA e 25§C and VCC e 5V.
Note 3: TA e 25§C and VCC e 5V.
3
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