NSC DM54LS374J-883, DM54LS374E-883, DM54LS374W-883, DM54LS374MW8 Datasheet

May 1992

DM54LS373/DM74LS373,

DM54LS374/DM74LS374

TRI-STATEÉ Octal D-Type Transparent

Latches and Edge-Triggered Flip-Flops

General Description

These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. (Continued)

Features

Y Choice of 8 latches or 8 D-type flip-flops in a single package

YTRI-STATE bus-driving outputs

YFull parallel-access for loading

YBuffered control inputs

YP-N-P inputs reduce D-C loading on data lines

Connection Diagrams

Dual-In-Line Packages

'LS373

Order Number

DM54LS373J,

DM54LS373W,

DM74LS373N or

DM74LS373WM

See NS Package Number

J20A, M20B, N20A or

W20A

TL/F/6431 ± 1

'LS374

Order Number

DM54LS374J,

DM54LS374W,

DM74LS374WM or

DM74LS374N

See NS Package Number

J20A, M20B, N20A or

W20A

TL/F/6431 ± 2

TRI-STATEÉ is a registered trademark of National Semiconductor Corp.

Type-D Octal STATE-TRI	DM54LS373/DM74LS373,
and Latches Transparent	DM54LS374/DM74LS374
Flops-Flip Triggered-Edge

C1995 National Semiconductor Corporation

TL/F/6431

RRD-B30M105/Printed in U. S. A.

e Don't Care

General Description (Continued)

The eight latches of the DM54/74LS373 are transparent D- type latches meaning that while the enable (G) is high the Q outputs will follow the data (D) inputs. When the enable is taken low the output will be latched at the level of the data that was set up.

The eight flip-flops of the DM54/74LS374 are edge-trig- gered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.

A buffered output control input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are off.

Function Tables

DM54/74LS373

	Output	Enable	D	Output
	Control	G
	L	H	H	H
	L	H	L	L
	L	L	X	Q0
	H	X	X	Z

DM54/74LS374

	Output	Clock	D	Output
	Control
	L	u	H	H
	L	u	L	L
	L	L	X	Q0
	H	X	X	Z

H e High Level (Steady State), L e Low Level (Steady State), X u e Transition from low-to-high level, Z e High Impedance State

Q0 e The level of the output before steady-state input conditions were established.

Logic Diagrams

DM54/74LS373	DM54/74LS374
Transparent Latches	Positive-Edge-Triggered Flip-Flops

TL/F/6431 ± 3

TL/F/6431 ± 4

2

Absolute Maximum Ratings (See Note)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage	7V
Input Voltage	7V
Storage Temperature Range	b65§C to a150§C
Operating Free Air Temperature Range	b55§C to a125§C
DM54LS
DM74LS	0§C to a70§C

Note: The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings. The ``Recommended Operating Conditions'' table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol

Parameter

DM54LS373

DM74LS373

Units

Min

Nom

Max

Min

Nom

Max

VCC

Supply Voltage

4.5

5

5.5

4.75

5

5.25

V

VIH

High Level Input Votage

2

2

V

VIL

Low Level Input Voltage

0.7

0.8

V

IOH

High Level Output Current

b1

b2.6

mA

IOL

Low Level Output Current

12

24

mA

tW

Pulse Width

Enable High

15

15

ns

(Note 2)

Enable Low

15

15

tSU

Data Setup Time (Notes 1 & 2)

5v

5v

ns

tH

Data Hold Time (Notes 1 & 2)

20v

20v

ns

TA

Free Air Operating Temperature

b55

125

0

70

§C

Note 1: The symbol (v) indicates the falling edge of the clock pulse is used for reference.

Note 2: TA e 25§C and VCC e 5V.

'LS373 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Symbol	Parameter	Conditions		Min	Typ	Max	Units
					(Note 1)
VI	Input Clamp Voltage	VCC e Min, II e b18 mA				b1.5	V
VOH	High Level Output Voltage	VCC e Min	DM54	2.4	3.4
		IOH e Max
							V
		VIL e Max
			DM74
		VIH e Min		2.4	3.1
VOL	Low Level Output Voltage	VCC e Min	DM54		0.25	0.4
		IOL e Max
		VIL e Max	DM74
		VIH e Min			0.35	0.5	V
		IOL e 12 mA	DM74			0.4
		VCC e Min
II	Input Current @ Max	VCC e Max, VI e 7V				0.1	mA
	Input Voltage
IIH	High Level Input Current	VCC e Max, VI e 2.7V				20	mA
IIL	Low Level Input Current	VCC e Max, VI e 0.4V				b0.4	mA
IOZH	Off-State Output Current	VCC e Max, VO e 2.7V
	with High Level Output	VIH e Min, VIL e Max				20	mA
	Voltage Applied
IOZL	Off-State Output Current	VCC e Max, VO e 0.4V
	with Low Level Output	VIH e Min, VIL e Max				b20	mA
	Voltage Applied
IOS	Short Circuit	VCC e Max	DM54	b20		b100	mA
	Output Current	(Note 2)	DM74	b50		b225
ICC	Supply Current	VCC e Max, OC e 4.5V,			24	40	mA
		Dn, Enable e GND

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