NSC CLC533MDC, CLC533AJP, CLC533AJE-TR13, CLC533AJE, 5962-9320301MEA Datasheet

N June 1999

CLC533

High-Speed 4:1 Analog Multiplexer

General Description

The CLC533 is a high-speed 4:1 multiplexer employing active input and output stages. The CLC533 also employs a closed-loop design which dramatically improves accuracy over conventional analog multiplexer circuits. This monolithic device is constructed using an advanced high-performance bipolar process.

The CLC533 has been specifically designed to provide a 24ns settling time to 0.01%. This coupled with the adjustable bandwidth, makes the CLC533 an ideal choice for infrared and CCD imaging systems, with channel-to-channel isolation of 80dB @ 10MHz. Low distortion and spurious signal levels (-80dBc) make the CLC533 a very suitable choice for I/Q processors in radar receivers.

The CLC533 is offered over both the industrial and military temperature ranges. The industrial versions, CLC533AJP\AJE\AIB, are specified from -40°C to +85°C and are packaged in 16-pin plastic DIPs, SOIC’s and CERDIP packages. The extended temperature versions, CLC533A8B/A8L-2A, are specified from -55°C to +125°C and are packaged in 16-pin CERDIP and 20-terminal LCC packages.

Ordering Information ...

Features

■12-bit settling (0.01%) – 17ns

■Low noise – 42 Vrms

■Isolation – 80dB @ 10MHz

■110MHz -3dB bandwidth (Av = +2)

■Low distortion – 80dB @ 5MHz

■Adjustable bandwidth – 180MHz (max)

Applications

■Infrared system multiplexing

■CCD sensor signals

■Radar I/Q switching

■High definition video HDTV

■Test and calibration

CLC533AJP	-40°C to +85°C	16-pin plastic	DIP
CLC533AJE	-40°C to +85°C	16-pin plastic SOIC
CLC533ALC	-40°C to +85°C	dice
CLC533A8B	-55°C to +125°C	16-pin CERDIP,
		MIL-STD-883
CLC533AMC	-40°C to +85°C	dice, MIL-STD-833
CLC533A8L-2A	-55°C to +125°C	20-terminal LCC,
		MIL-STD-883

Contact factory for other packages and DESC SMD number.

Functional Diagram

	IN	GND	NC	IN	GND
	c			B
	8	7	6	5	4
GND	9				3	INA
IND 10					2	GND
NC 11					1	NC
Vee	12				20	OUTPUT
A1	13				19	COMP1
	14 15 16 17 18
	A	COMP	NC	D	V
	0			REF	cc
		2

A1	A0	OUT	Pinout
			DIP & SOIC
0	0	A
0	1	B
1	0	C
1	1	D
ECL Mode - DREF = open
TTL Mode - DREF = +5V

Speed-High	CLC533
Multiplexer Analog 4:1

© 1999 National Semiconductor Corporation

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Printed in the U.S.A.

CLC533 Electrical Characteristics (+Vcc = +5.0V; -Vee = -5.2V; Rin = 50Ω; RL = 500Ω; CCOMP = 8pf; ECL Mode, pin 13 = NC)

PARAMETERS		CONDITIONS	TYP	MIN/MAX RATINGS2			UNITS	SYMBOL
Ambient Temperature		CLC533AJP/AJE/AIB	+25°C	-40°C	+25°C	+85°C
FREQUENCY DOMAIN RESPONSE		VOUT < 0.1Vpp	180	130	130	110	MHz	SSBW
-3dB bandwidth
-3dB bandwidth		VOUT = 2Vpp	45	35	35	30	MHz	LSBW
gain flatness		VOUT < 0.1Vpp	0.2	0.5	0.5	0.5	dB	GFP
peaking		0.1MHz to 200MHz
rolloff		0.1MHz to 100MHz	1.0	2.0	2.0	3.0	dB	GFR
linear phase deviation		dc to 100MHz	2.0				deg	LPD
crosstalk rejection - 1 channel		2Vpp, 10MHz	80	74	74	74	dB	CT10
		2Vpp, 20MHz	74	68	68	68	dB	CT20
		2Vpp, 30MHz	68	62	62	62	dB	CT30
crosstalk rejection - 3 channels		2Vpp, 10MHz	80	74	74	74	dB	3CT10
		2Vpp, 20MHz	74	68	68	68	dB	3CT20
		2Vpp, 30MHz	68	62	62	62	dB	3CT30
TIME DOMAIN PERFORMANCE
rise and fall time		0.5V step	2.7	3.3	3.3	3.8	ns	TRS
settling time2		2V step	10	12.5	12.5	14.5	ns	TRL
	2V step	±0.01%	17	24	24	27	ns	TSP
		±0.1%	13	18	18	21	ns	TSS
overshoot		2.0V step	2	5	5	6	%	OS
slew rate			160	130	130	110	V/µs	SR
SWITCH PERFORMANCE
channel to channel switching time		50% SELECT to 10%VOUT	6	8	8	9	ns	SWT10
(2V step at output)		50% SELECT to 90%VOUT	16	21	21	24	ns	SWT90
switching transient			30				mV	ST
DISTORTION AND NOISE PERFORMANCE
2nd harmonic distortion		2Vpp, 5MHz	80	67	67	67	dBc	HD2
3rd harmonic distortion		2Vpp, 5MHz	86	67	67	67	dBc	HD3
equivalent input noise							nV/√Hz
spot noise voltage		> 1MHz	4.2					SNF
integrated noise		1MHz to 100MHz	42	54		51	mVrms	INV
spot noise current			5				pA/√Hz	SNF
STATIC AND DC PERFORMANCE
* analog output offset			1	12	3.5	4.5	mV	VOS
temperature coefficient			15	90		20	µV/°C	DVIO
* analog input bias current			50	280	120	120	µA	IBN
temperature coefficient			0.3	2.0		0.8	µA/°C	DIBN
analog input resistance			200	90	120	120	kΩ	RIN
analog input capacitance			2	3.0	2.5	2.5	pF	CIN
* gain accuracy		±2V	0.994	0.988	0.988	0.988	V/V	GA
integral endpoint linearity		±1V (full scale)	0.02	0.05	0.03	0.03	%FS	ILIN
output voltage		no load	±3.4	2.4	2.8	2.8	V	VO
output current			45	20	50	50	mA	IO
output resistance		DC	1.5	4.0	2.5	2.5	Ω	RO
DIGITAL INPUT PERFORMANCE
ECL mode (DREF floating)				-1.1	-1.1	-1.1	V	VIH1
input voltage logic HIGH
input voltage logic LOW				-1.5	-1.5	-1.5	V	VIL1
input current logic HIGH			200	220	80	80	µA	IIH1
input current logic LOW			200	220	80	80	µA	IIL1
TTL mode (DREF = +5V)				2.0	2.0	2.0	V	VIH2
input voltage logic HIGH
input voltage logic LOW				0.8	0.8	0.8	V	VIL2
input current logic HIGH			200	220	80	80	µA	IIH2
input current logic LOW			200	220	80	80	µA	IIL2
POWER REQUIREMENTS
* supply current (+VCC = +5.0V)		no load	28	38	36	36	mA	ICC
* supply current (-Vee = -5.2V)		no load	28.5	39	37	37	mA	IEE
nominal power dissipation		no load	288				mW	PD
* power supply rejection ratio				-53	-60	-60	dB	PSRR

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.

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CLC533 Typical Performance Characteristics (TA = 25°C, +Vcc = +5V, -Vee = -5.2V, RL = 500Ω unless specified)

Small Signal Gain/Phase vs. Load*

*with recommended CCOMP

Digitalized Pulse Response

±

±

3

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