NSC JM38510R75601SR, JM38510R75601S2, JM38510R75601BS, JM38510R75601BR, JM38510R75601B2 Datasheet
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July 1998
54AC273
Octal D Flip-Flop
General Description
The '273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.
All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
Features
nIdeal buffer for microprocessor or memory
nEight edge-triggered D flip-flops
nBuffered common clock
nBuffered, asynchronous master reset
nSee '377 for clock enable version
nSee '373 for transparent latch version
nSee '374 for TRI-STATE® version
nOutputs source/sink 24 mA
n'ACT has TTL-compatible inputs
nStandard Military Drawing (SMD)
Ð'AC273: 5962-87756
Logic Symbols
IEEE/IEC
DS100288-1
DS100288-2
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Pin Names |
Description |
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D0±D7 |
Data Inputs |
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Master Reset |
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MR |
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CP |
Clock Pulse Input |
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Q0±Q7 |
Data Outputs |
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TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT™ is a trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation |
DS100288 |
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Flop-Flip D Octal 54AC273
54AC273
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PrintDate=1998/07/27 PrintTime=08:02:05 44014 ds100288 Rev. No. 1 cmserv Proof |
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Connection Diagrams
Pin Assignment |
Pin Assignment |
for DIP and Flatpak |
for LCC |
DS100288-3
DS100288-4
Mode Select-Function Table
Operating Mode |
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Inputs |
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Outputs |
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CP |
Dn |
Qn |
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MR |
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Reset (Clear) |
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L |
X |
X |
L |
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Load `1' |
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H |
N |
H |
H |
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Load `0' |
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H |
N |
L |
L |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Transition
Logic Diagram
DS100288-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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PrintDate=1998/07/27 PrintTime=08:02:05 44014 ds100288 Rev. No. 1 cmserv Proof |
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to V CC + 0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC + 0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to to V CC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
±50 mA |
DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
±50 mA |
Storage Temperature (TSTG) |
−65ÊC to +150ÊC |
Junction Temperature (TJ) |
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CDIP |
175ÊC |
Recommended Operating
Conditions
Supply Voltage (VCC) |
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'AC |
2.0V to 6.0V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
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54AC |
−55ÊC to +125ÊC |
Minimum Input Edge Rate ( V/ |
t) |
'AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications.
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DC Characteristics for 'AC Family Devices |
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54AC |
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Symbol |
Parameter |
VCC |
TA = |
Units |
Conditions |
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(V) |
−55ÊC to +125ÊC |
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Guaranteed |
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Limits |
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VIH |
Minimum High Level |
3.0 |
2.1 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
3.15 |
V |
or VCC − 0.1V |
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5.5 |
3.85 |
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VIL |
Maximum Low Level |
3.0 |
0.9 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
1.35 |
V |
or VCC − 0.1V |
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5.5 |
1.65 |
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VOH |
Minimum High Level |
3.0 |
2.9 |
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IOUT = −50 µA |
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Output Voltage |
4.5 |
4.4 |
V |
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5.5 |
5.4 |
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(Note 2) |
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VIN = VIL or VIH |
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3.0 |
2.4 |
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IOH = −12 mA |
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4.5 |
3.7 |
V |
IOH = −24 mA |
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5.5 |
4.7 |
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IOH = −24 mA |
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VOL |
Maximum Low Level |
3.0 |
0.1 |
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IOUT = 50 µA |
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Output Voltage |
4.5 |
0.1 |
V |
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5.5 |
0.1 |
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(Note 2) |
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VIN = VIL or VIH |
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3.0 |
0.50 |
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IOL = 12 mA |
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4.5 |
0.50 |
V |
IOL = 24 mA |
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5.5 |
0.50 |
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IOL = 24 mA |
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IIN |
Maximum Input |
5.5 |
±1.0 |
µA |
VI = VCC, GND |
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Leakage Current |
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IOLD |
(Note 3) |
5.5 |
50 |
mA |
VOLD = 1.65V Max |
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Minimum Dynamic |
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IOHD |
5.5 |
−50 |
mA |
V OHD = 3.85V Min |
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Output Current |
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www.national.com |
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PrintDate=1998/07/27 PrintTime=08:02:05 44014 ds100288 Rev. No. 1 cmserv Proof |
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