NSC DS90LV001MWC, DS90LV001MDC, DS90LV001TMX, DS90LV001TM, DS90LV001TLDX Datasheet

April 2001

DS90LV001

3.3V LVDS-LVDS Buffer

General Description

The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the 'stub length' or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like.

The DS90LV001, available in the LLP (Leadless Leadframe Package) package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance.

A wide input dynamic range will allow the DS90LV001 to receive differential signals from LVPECL as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-LVDS translator.

An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options, an 8 pin LLP and SOIC.

Features

nSingle +3.3 V Supply

nLVDS receiver inputs accept LVPECL signals

nTRI-STATE outputs

nReceiver input threshold < ±100 mV

nFast propagation delay of 1.4 ns (typ)

nLow jitter 800 Mbps fully differential data path

n100 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 800 Mbps

nCompatible with ANSI/TIA/EIA-644-A LVDS standard

n8 pin SOIC and space saving (70%) LLP package

nIndustrial Temperature Range

Connection Diagram

Top View

DS101338-5

Order Number DS90LV001TM, DS90LV001TLD

See NS Package Number M08A, LDA08A

Block Diagram

DS101338-2

Buffer LVDS-LVDS 3V.3 DS90LV001

© 2001 National Semiconductor Corporation

DS101338

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DS90LV001

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

	Supply Voltage (VCC)	−0.3V to +4V
	LVCMOS/LVTTL Input Voltage	−0.3V to (V CC + 0.3V)
	(EN)
	LVDS Receiver Input Voltage
	(IN+, IN−)	−0.3V to +4V
	LVDS Driver Output Voltage
	(OUT+, OUT−)	−0.3V to +4V
	LVDS Output Short Circuit	Continuous
	Current
	Junction Temperature	+150ÊC
	Storage Temperature Range	−65ÊC to +150ÊC
	Lead Temperature Range
	Soldering (4 sec.)	+260ÊC

Maximum Package Power Dissipation at 25ÊC

M Package	726 mW
Derate M Package	5.8 mW/ÊC above +25ÊC
LDA Package	2.44 W
Derate LDA Package	19.49 mW/ÊC above
	+25ÊC
ESD Ratings
(HBM, 1.5kW, 100pF)	³2.5kV
(EIAJ, 0W, 200pF)	³250V

Recommended Operating

Conditions

	Min	Typ	Max	Units
Supply Voltage (VCC)	3.0	3.3	3.6	V
Receiver Input Voltage	0		VCC	V
Operating Free Air	−40	+25	+85	ÊC
Temperature

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)

Symbol		Parameter	Conditions		Min	Typ	Max	Units
	LVCMOS/LVTTL DC SPECIFICATIONS (EN)
	VIH	High Level Input Voltage			2.0		VCC	V
	VIL	Low Level Input Voltage			GND		0.8	V
	IIH	High Level Input Current	VIN = 3.6V or 2.0V, VCC = 3.6V			+7	+20	µA
	IIL	Low Level Input Current	VIN = GND or 0.8V, VCC = 3.6V			±1	±10	µA
	VCL	Input Clamp Voltage	ICL = −18 mA			−0.6	−1.5	V
	LVDS OUTPUT DC SPECIFICATIONS (OUT)
	VOD	Differential Output Voltage	RL = 100W		250	325	450	mV
	DVOD	Change in Magnitude of VOD for Complimentary	Figure 1 and Figure 2				20	mV
		Output States
	VOS	Offset Voltage	RL = 100W		1.080	1.19	1.375	V
	DVOS	Change in Magnitude of VOS for Complimentary	Figure 1				20	mV
		Output States
	IOZ	Output TRI-STATE Current	EN = 0V, VOUT = VCC or GND			±1	±10	µA
	IOFF	Power-Off Leakage Current	VCC = 0V, VOUT = 3.6V or GND			±1	±10	µA
	IOS	Output Short Circuit Current (Note 4)	EN = VCC, VOUT+ and VOUT− = 0V			−16	−24	mA
	IOSD	Differential Output Short Circuit Current (Note 4)	EN = VCC, VOD = 0V			−7	−12	mA
	LVDS RECEIVER DC SPECIFICATIONS (IN)
	VTH	Differential Input High Threshold	VCM = +0.05V, +1.2V or +3.25V			0	+100	mV
	VTL	Differential Input Low Threshold			−100	0		mV
	VCMR	Common Mode Voltage Range	VID = 100mV, VCC = 3.3V		0.05		3.25	V
	IIN	Input Current	VIN = +3.0V	VCC = 3.6V or 0V		±1	±10	µA
			VIN = 0V			±1	±10	µA
	DIIN	Change in Magnitude of IIN	VIN = +3.0V	VCC = 3.6V or 0V		1	6	µA
			VIN = 0V			1	6	µA
	SUPPLY CURRENT
	ICCD	Total Supply Current	EN = VCC, RL = 100W, CL = 5 pF			47	70	mA
	ICCZ	TRI-STATE Supply Current	EN = 0V			22	35	mA

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AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)

Symbol		Parameter	Conditions	Min	Typ	Max	Units
	tPHLD	Differential Propagation Delay High to Low	RL = 100Ω, CL = 5pF	1.0	1.4	2.0	ns
	tPLHD	Differential Propagation Delay Low to High	Figure 3 and Figure 4	1.0	1.4	2.0	ns
	tSKD1	Pulse Skew |tPLHD − t PHLD| (Note 5) (Note 6)			20	200	ps
	tSKD3	Part to Part Skew (Note 5) (Note 7)			0	60	ps
	tSKD4	Part to Part Skew (Note 5) (Note 8)				400	ps
	tLHT	Rise Time (Note 5)	RL = 100Ω, CL = 5pF	200	320	450	ps
	tHLT	Fall Time (Note 5)	Figure 3 and Figure 5	200	310	450	ps
	tPHZ	Disable Time (Active High to Z)	RL = 100Ω, CL = 5pF		3	25	ns
	tPLZ	Disable Time (Active Low to Z)	Figure 6 and Figure 7		3	25	ns
	tPZH	Enable Time (Z to Active High)			25	45	ns
	tPZL	Enable Time (Z to Active Low)			25	45	ns
	tDJ	LVDS Data Jitter, Deterministic (Peak-to-Peak)	VID = 300mV; PRBS = 223 − 1 data;		100	135	ps
		(Note 9)	VCM = 1.2V at 800Mbps (NRZ)
	tRJ	LVDS Clock Jitter, Random (Note 9)	VID = 300mV; VCM = 1.2V at 400MHz		2.2	3.5	ps
			clock

Note 1: ªAbsolute Maximum Ratingsº are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of ªElectrical Characteristicsº specifies conditions of device operation.

Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and VOD.

Note 3: All typical are given for VCC = +3.3V and TA = +25ÊC, unless otherwise stated.

Note 4: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.

Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and temperature) range.

Note 6: tSKD1, |tPLHD − t PHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel.

Note 7: tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5ÊC of each other within the operating temperature range.

Note 8: tSKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.

Note 9: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT range with the following test equipment setup: HP8133A (pattern pulse generator), 5 feet of RG142B cable with DUT test board and HP83480A (digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with RG142B cable exhibit a tDJ = 21ps and tRJ = 1.8ps.

DS90LV001

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DS90LV001

DC Test Circuits

DS101338-3

FIGURE 1. Differential Driver DC Test Circuit

DS101338-8

FIGURE 2. Differential Driver Full Load DC Test Circuit

AC Test Circuits and Timing Diagrams

DS101338-6

FIGURE 3. LVDS Output Load

DS101338-7

FIGURE 4. Propagation Delay Low-to-High and High-to-Low

DS101338-9

FIGURE 5. LVDS Output Transition Time

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